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| author | Ashish Chaudhari <ashish@ettus.com> | 2014-08-19 12:09:05 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2014-08-19 12:09:05 -0700 |
| commit | d31ffb2ef869b05fc4aeafd6bf588e62dca7ee82 (patch) | |
| tree | 2fcd613229f08288fbf92785cd6a1d5359631521 /fpga/usrp3/top/x300/Makefile.x300.inc | |
| parent | 83249208bdc17603358019be0910d0a74ec41085 (diff) | |
| parent | 3347e831f002da769632dfe0c70ea17c2d749a8a (diff) | |
| download | uhd-d31ffb2ef869b05fc4aeafd6bf588e62dca7ee82.tar.gz uhd-d31ffb2ef869b05fc4aeafd6bf588e62dca7ee82.tar.bz2 uhd-d31ffb2ef869b05fc4aeafd6bf588e62dca7ee82.zip | |
Merge branch 'maint'
Diffstat (limited to 'fpga/usrp3/top/x300/Makefile.x300.inc')
| -rw-r--r-- | fpga/usrp3/top/x300/Makefile.x300.inc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/fpga/usrp3/top/x300/Makefile.x300.inc b/fpga/usrp3/top/x300/Makefile.x300.inc index 1395b5f00..6e13e4fed 100644 --- a/fpga/usrp3/top/x300/Makefile.x300.inc +++ b/fpga/usrp3/top/x300/Makefile.x300.inc @@ -49,7 +49,7 @@ synthesis_tool "XST (VHDL/Verilog)" \ simulator "ISim (VHDL/Verilog)" \ "Preferred Language" "Verilog" \ "Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE +"Display Incremental Messages" FALSE ################################################## # Sources @@ -142,7 +142,8 @@ MAP_PROPERTIES = \ "Map Effort Level" High \ "Extra Effort" Normal \ "Perform Timing-Driven Packing and Placement" TRUE \ -"Enable Multi-Threading 2" +"Enable Multi-Threading 2" \ +"Starting Placer Cost Table (1-100)" $$(( $$RANDOM % 100 + 1 )) #"Map to Input Functions" 4 \ PLACE_ROUTE_PROPERTIES = \ @@ -160,6 +161,6 @@ GEN_PROG_FILE_PROPERTIES = \ "Done (Output Events)" 5 \ "Enable Bitstream Compression" FALSE \ "Enable Outputs (Output Events)" 6 \ -"Wait for DCI Match (Output Events)" NoWait +"Wait for DCI Match (Output Events)" NoWait SIM_MODEL_PROPERTIES = "" |