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| author | Ben Hilburn <ben.hilburn@ettus.com> | 2013-12-03 10:35:35 -0800 |
|---|---|---|
| committer | Ben Hilburn <ben.hilburn@ettus.com> | 2013-12-03 10:35:35 -0800 |
| commit | 4b4365a517938b365af57674a3ab1462432c2c3a (patch) | |
| tree | 04386aca95f77810f8127067d05a1dd60356044a /fpga/usrp3/top/python/check_inout.py | |
| parent | abc682eda8d84d5a366ca32ca87e81e0890e69e2 (diff) | |
| download | uhd-4b4365a517938b365af57674a3ab1462432c2c3a.tar.gz uhd-4b4365a517938b365af57674a3ab1462432c2c3a.tar.bz2 uhd-4b4365a517938b365af57674a3ab1462432c2c3a.zip | |
b2xx: Updating FPGA source with recent bugfixes.
Diffstat (limited to 'fpga/usrp3/top/python/check_inout.py')
| -rwxr-xr-x | fpga/usrp3/top/python/check_inout.py | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/fpga/usrp3/top/python/check_inout.py b/fpga/usrp3/top/python/check_inout.py index d3b63dc34..ff371d378 100755 --- a/fpga/usrp3/top/python/check_inout.py +++ b/fpga/usrp3/top/python/check_inout.py @@ -2,8 +2,19 @@ # # Copyright 2010 Ettus Research LLC # - - +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# # Description: # generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf. # outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes |