Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 187 insertions, 0 deletions

diff --git a/fpga/usrp3/top/n3xx/n3xx_serial_dac_arb.vhd b/fpga/usrp3/top/n3xx/n3xx_serial_dac_arb.vhd
new file mode 100644
index 000000000..9049bd845
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/n3xx_serial_dac_arb.vhd
@@ -0,0 +1,187 @@
+-------------------------------------------------------------------------------
+-- Title      : N3xx serial DAC interface with arbiter
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : spec_serial_dac.vhd
+-- Author     : Tomasz Wlostowski, modifications by dbaker
+-- Company    : CERN BE-Co-HT
+-- Platform   : fpga-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity n3xx_serial_dac_arb is
+  generic(
+    g_invert_sclk    : boolean;
+    g_num_extra_bits : integer
+    );
+  port(
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    val1_i  : in std_logic_vector(15 downto 0);
+    load1_i : in std_logic;
+    val2_i  : in std_logic_vector(15 downto 0);
+    load2_i : in std_logic;
+
+    dac_cs_n_o  : out std_logic_vector(1 downto 0);
+    dac_clr_n_o : out std_logic;
+    dac_sclk_o  : out std_logic;
+    dac_din_o   : out std_logic);
+
+end n3xx_serial_dac_arb;
+
+architecture behavioral of n3xx_serial_dac_arb is
+
+  component n3xx_serial_dac
+    generic (
+      g_num_data_bits  : integer;
+      g_num_extra_bits : integer;
+      g_num_cs_select  : integer);
+    port (
+      clk_i         : in  std_logic;
+      rst_n_i       : in  std_logic;
+      value_i       : in  std_logic_vector(g_num_data_bits-1 downto 0);
+      cs_sel_i      : in  std_logic_vector(g_num_cs_select-1 downto 0);
+      load_i        : in  std_logic;
+      sclk_divsel_i : in  std_logic_vector(2 downto 0);
+      dac_cs_n_o    : out std_logic_vector(g_num_cs_select-1 downto 0);
+      dac_sclk_o    : out std_logic;
+      dac_sdata_o   : out std_logic;
+      xdone_o       : out std_logic);
+  end component;
+
+  signal d1, d2             : std_logic_vector(15 downto 0) := (others=>'0');
+  signal d1_ready, d2_ready : std_logic := '0';
+
+
+  signal dac_data     : std_logic_vector(15 downto 0) := (others=>'0');
+  signal dac_load     : std_logic := '0';
+  signal dac_cs_sel   : std_logic_vector(1 downto 0) := (others=>'0');
+  signal dac_done     : std_logic := '0';
+  signal dac_sclk_int : std_logic := '0';
+
+  type t_state is (WAIT_DONE, LOAD_DAC, WAIT_DATA);
+
+  signal state : t_state;
+
+  signal trig0    : std_logic_vector(31 downto 0);
+  signal trig1    : std_logic_vector(31 downto 0);
+  signal trig2    : std_logic_vector(31 downto 0);
+  signal trig3    : std_logic_vector(31 downto 0);
+  signal CONTROL0 : std_logic_vector(35 downto 0);
+
+begin  -- behavioral
+
+  dac_clr_n_o <= '1';
+
+  U_DAC : n3xx_serial_dac
+    generic map (
+      g_num_data_bits  => 16,
+      g_num_extra_bits => g_num_extra_bits,
+      g_num_cs_select  => 2)
+    port map (
+      clk_i         => clk_i,
+      rst_n_i       => rst_n_i,
+      value_i       => dac_data,
+      cs_sel_i      => dac_cs_sel,
+      load_i        => dac_load,
+      sclk_divsel_i => "001",
+      dac_cs_n_o    => dac_cs_n_o,
+      dac_sclk_o    => dac_sclk_int,
+      dac_sdata_o   => dac_din_o,
+      xdone_o       => dac_done);
+
+
+  p_drive_sclk: process(dac_sclk_int)
+    begin
+      if(g_invert_sclk) then
+        dac_sclk_o <= not dac_sclk_int;
+       else
+        dac_sclk_o <= dac_sclk_int;
+       end if;
+      end process;
+
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        d1         <= (others => '0');
+        d1_ready   <= '0';
+        d2         <= (others => '0');
+        d2_ready   <= '0';
+        dac_load   <= '0';
+        dac_cs_sel <= (others => '0');
+        state      <= WAIT_DATA;
+      else
+
+        if(load1_i = '1' or load2_i = '1') then
+
+          if(load1_i = '1') then
+            d1_ready <= '1';
+            d1       <= val1_i;
+          end if;
+
+          if(load2_i = '1') then
+            d2_ready <= '1';
+            d2       <= val2_i;
+          end if;
+        else
+          case state is
+            when WAIT_DATA =>
+              if(d1_ready = '1') then
+                dac_cs_sel <= "01";
+                dac_data   <= d1;
+                dac_load   <= '1';
+                d1_ready   <= '0';
+                state      <= LOAD_DAC;
+              elsif(d2_ready = '1') then
+                dac_cs_sel <= "10";
+                dac_data   <= d2;
+                dac_load   <= '1';
+                d2_ready   <= '0';
+                state      <= LOAD_DAC;
+              end if;
+
+            when LOAD_DAC=>
+              dac_load <= '0';
+              state    <= WAIT_DONE;
+
+            when WAIT_DONE =>
+              if(dac_done = '1') then
+                state <= WAIT_DATA;
+              end if;
+            when others => null;
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+
+
+end behavioral;