Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

24 files changed, 2111 insertions, 0 deletions

diff --git a/fpga/usrp3/top/n3xx/dts/dma-common.dtsi b/fpga/usrp3/top/n3xx/dts/dma-common.dtsi
new file mode 100644
index 000000000..65d33cb76
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/dma-common.dtsi
@@ -0,0 +1,588 @@
+/*
+ * Copyright (c) 2017 National Instruments Corp
+ *
+ * SPDX-License-Identifier: GPL-2.0 OR X11
+ */
+
+&fpga_full {
+	tx_dma0: dma@43CA0000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43CA0000 0x10000>;
+		interrupts = <0 53 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <0>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <1>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	tx_dma1: dma@43CB0000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43CB0000 0x10000>;
+		interrupts = <0 53 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <0>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <1>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	tx_dma2: dma@43CC0000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43CC0000 0x10000>;
+		interrupts = <0 53 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <0>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <1>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	tx_dma3: dma@43CD0000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43CD0000 0x10000>;
+		interrupts = <0 53 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <0>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <1>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	tx_dma4: dma@43CE0000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43CE0000 0x10000>;
+		interrupts = <0 53 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <0>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <1>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	tx_dma5: dma@43CF0000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43CF0000 0x10000>;
+		interrupts = <0 53 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <0>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <1>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	tx_dma6: dma@43D00000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43D00000 0x10000>;
+		interrupts = <0 53 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <0>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <1>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	tx_dma7: dma@43D10000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43D10000 0x10000>;
+		interrupts = <0 53 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <0>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <1>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	tx_dma8: dma@43D20000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43D20000 0x10000>;
+		interrupts = <0 53 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <0>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <1>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	tx_dma9: dma@43D30000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43D30000 0x10000>;
+		interrupts = <0 53 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <0>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <1>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	rx_dma0: dma@43C00000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43C00000 0x10000>;
+		interrupts = <0 52 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <1>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <0>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	rx_dma1: dma@43C10000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43C10000 0x10000>;
+		interrupts = <0 52 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <1>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <0>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	rx_dma2: dma@43C20000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43C20000 0x10000>;
+		interrupts = <0 52 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <1>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <0>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	rx_dma3: dma@43C30000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43C30000 0x10000>;
+		interrupts = <0 52 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <1>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <0>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	rx_dma4: dma@43C40000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43C40000 0x10000>;
+		interrupts = <0 52 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <1>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <0>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	rx_dma5: dma@43C50000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43C50000 0x10000>;
+		interrupts = <0 52 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <1>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <0>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	rx_dma6: dma@43C60000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43C60000 0x10000>;
+		interrupts = <0 52 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <1>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <0>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	rx_dma7: dma@43C70000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43C70000 0x10000>;
+		interrupts = <0 52 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <1>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <0>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	rx_dma8: dma@43C80000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43C80000 0x10000>;
+		interrupts = <0 52 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <1>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <0>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+	rx_dma9: dma@43C90000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x43C90000 0x10000>;
+		interrupts = <0 52 4>;
+		interrupt-parent = <&intc>;
+		clocks = <&clkc 15>;
+		#dma-cells = <1>;
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-type = <1>;
+				adi,source-bus-width = <0x20>;
+				adi,destination-bus-type = <0>;
+				adi,destination-bus-width = <0x20>;
+				adi,length-width = <24>;
+			};
+		};
+	};
+
+
+	usrp_rx_dma0: usrp-rx-dma@43c00000 {
+		compatible = "ettus,usrp-rx-dma";
+		dmas = <&rx_dma0 0>;
+		dma-names = "dma";
+		port-id = <0>;
+		status = "okay";
+
+		regmap = <&dma_conf0>;
+		offset = <0x0>;
+	};
+
+	usrp_rx_dma1: usrp-rx-dma@43c10000 {
+		compatible = "ettus,usrp-rx-dma";
+		dmas = <&rx_dma1 0>;
+		dma-names = "dma";
+		port-id = <1>;
+
+		regmap = <&dma_conf0>;
+		offset = <0x4>;
+	};
+
+	usrp_rx_dma2: usrp-rx-dma@43c20000 {
+		compatible = "ettus,usrp-rx-dma";
+		dmas = <&rx_dma2 0>;
+		dma-names = "dma";
+		port-id = <2>;
+
+		regmap = <&dma_conf0>;
+		offset = <0x8>;
+	};
+
+	usrp_rx_dma3: usrp-rx-dma@43c30000 {
+		compatible = "ettus,usrp-rx-dma";
+		dmas = <&rx_dma3 0>;
+		dma-names = "dma";
+		port-id = <3>;
+
+		regmap = <&dma_conf0>;
+		offset = <0xc>;
+	};
+
+	usrp_rx_dma4: usrp-rx-dma@43c40000 {
+		compatible = "ettus,usrp-rx-dma";
+		dmas = <&rx_dma4 0>;
+		dma-names = "dma";
+		port-id = <4>;
+
+		regmap = <&dma_conf0>;
+		offset = <0x10>;
+	};
+
+	usrp_rx_dma5: usrp-rx-dma@43c50000 {
+		compatible = "ettus,usrp-rx-dma";
+		dmas = <&rx_dma5 0>;
+		dma-names = "dma";
+		port-id = <5>;
+
+		regmap = <&dma_conf0>;
+		offset = <0x14>;
+	};
+
+	usrp_rx_dma6: usrp-rx-dma@43c60000 {
+		compatible = "ettus,usrp-rx-dma";
+		dmas = <&rx_dma6 0>;
+		dma-names = "dma";
+		port-id = <6>;
+
+		regmap = <&dma_conf0>;
+		offset = <0x18>;
+	};
+
+	usrp_rx_dma7: usrp-rx-dma@43c70000 {
+		compatible = "ettus,usrp-rx-dma";
+		dmas = <&rx_dma7 0>;
+		dma-names = "dma";
+		port-id = <7>;
+
+		regmap = <&dma_conf0>;
+		offset = <0x1c>;
+	};
+
+	usrp_rx_dma8: usrp-rx-dma@43c80000 {
+		compatible = "ettus,usrp-rx-dma";
+		dmas = <&rx_dma8 0>;
+		dma-names = "dma";
+		port-id = <8>;
+
+		regmap = <&dma_conf0>;
+		offset = <0x20>;
+	};
+
+	usrp_rx_dma9: usrp-rx-dma@43c90000 {
+		compatible = "ettus,usrp-rx-dma";
+		dmas = <&rx_dma9 0>;
+		dma-names = "dma";
+		port-id = <9>;
+
+		regmap = <&dma_conf0>;
+		offset = <0x24>;
+	};
+
+	usrp_tx_dma0: usrp-tx-dma@43ca0000 {
+		compatible = "ettus,usrp-tx-dma";
+		dmas = <&tx_dma0 0>;
+		dma-names = "dma";
+		port-id = <0>;
+	};
+
+	usrp_tx_dma1: usrp-tx-dma@43cb0000 {
+		compatible = "ettus,usrp-tx-dma";
+		dmas = <&tx_dma1 0>;
+		dma-names = "dma";
+		port-id = <1>;
+	};
+
+	usrp_tx_dma2: usrp-tx-dma@43cc0000 {
+		compatible = "ettus,usrp-tx-dma";
+		dmas = <&tx_dma2 0>;
+		dma-names = "dma";
+		port-id = <2>;
+		status = "okay";
+	};
+
+	usrp_tx_dma3: usrp-tx-dma@43cd0000 {
+		compatible = "ettus,usrp-tx-dma";
+		dmas = <&tx_dma3 0>;
+		dma-names = "dma";
+		port-id = <3>;
+	};
+
+	usrp_tx_dma4: usrp-tx-dma@43ce0000 {
+		compatible = "ettus,usrp-tx-dma";
+		dmas = <&tx_dma4 0>;
+		dma-names = "dma";
+		port-id = <4>;
+		status = "okay";
+	};
+
+	usrp_tx_dma5: usrp-tx-dma@43cf0000 {
+		compatible = "ettus,usrp-tx-dma";
+		dmas = <&tx_dma5 0>;
+		dma-names = "dma";
+		port-id = <5>;
+	};
+
+	usrp_tx_dma6: usrp-tx-dma@43d00000 {
+		compatible = "ettus,usrp-tx-dma";
+		dmas = <&tx_dma6 0>;
+		dma-names = "dma";
+		port-id = <6>;
+	};
+
+	usrp_tx_dma7: usrp-tx-dma@43d10000 {
+		compatible = "ettus,usrp-tx-dma";
+		dmas = <&tx_dma7 0>;
+		dma-names = "dma";
+		port-id = <7>;
+	};
+
+	usrp_tx_dma8: usrp-tx-dma@43d20000 {
+		compatible = "ettus,usrp-tx-dma";
+		dmas = <&tx_dma8 0>;
+		dma-names = "dma";
+		port-id = <8>;
+	};
+
+	usrp_tx_dma9: usrp-tx-dma@43d30000 {
+		compatible = "ettus,usrp-tx-dma";
+		dmas = <&tx_dma9 0>;
+		dma-names = "dma";
+		port-id = <9>;
+	};
+
+	dma_conf0: dma_conf0@42080000 {
+		compatible = "syscon";
+		reg = <0x42080000 0x1000>;
+		status = "okay";
+	};
+};
diff --git a/fpga/usrp3/top/n3xx/dts/n300-common.dtsi b/fpga/usrp3/top/n3xx/dts/n300-common.dtsi
new file mode 100644
index 000000000..1042d9531
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/n300-common.dtsi
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2017 National Instruments Corp
+ *
+ * SPDX-License-Identifier: GPL-2.0 OR X11
+ */
+
+&fpga_full {
+	uio@40010000 {
+		compatible = "usrp-uio";
+		reg = <0x40010000 0x2000>;
+		reg-names = "mboard-regs";
+		status = "okay";
+	};
+
+    uio@40014000 {
+		compatible = "usrp-uio";
+		reg = <0x40014000 0x4000>;
+		reg-names = "dboard-regs-0";
+		status = "okay";
+	};
+
+	uio@42100000 {
+		compatible = "usrp-uio";
+		reg = <0x42100000 0x1000>;
+		reg-names = "dboard-jtag-0";
+		status = "okay";
+	};
+};
+
+&spi0 {
+	status = "okay";
+
+	cs-gpios = <0>, <0>, <0>, <&gpio0 62 0>;
+
+	spidev0: spidev@0 {
+		compatible = "rohm,dh2228fv";
+		reg = <0>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+
+	spidev1: spidev@1 {
+		compatible = "rohm,dh2228fv";
+		reg = <1>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+
+	spidev2: spidev@2 {
+		compatible = "rohm,dh2228fv";
+		reg = <2>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+
+	spidev3: spidev@3 {
+		compatible = "rohm,dh2228fv";
+		reg = <3>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+};
diff --git a/fpga/usrp3/top/n3xx/dts/n300-fpga.dtsi b/fpga/usrp3/top/n3xx/dts/n300-fpga.dtsi
new file mode 100644
index 000000000..d6bbee1a3
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/n300-fpga.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2017 National Instruments Corp
+ */
+
+&fpga_full {
+	firmware-name = "n300.bin";
+};
diff --git a/fpga/usrp3/top/n3xx/dts/n310-common.dtsi b/fpga/usrp3/top/n3xx/dts/n310-common.dtsi
new file mode 100644
index 000000000..14be62eaf
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/n310-common.dtsi
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2017 National Instruments Corp
+ */
+
+&fpga_full {
+	uio@40010000 {
+		compatible = "usrp-uio";
+		reg = <0x40010000 0x2000>;
+		reg-names = "mboard-regs";
+		status = "okay";
+	};
+
+	uio@40014000 {
+		compatible = "usrp-uio";
+		reg = <0x40014000 0x4000>;
+		reg-names = "dboard-regs-0";
+		status = "okay";
+	};
+
+	uio@40018000 {
+		compatible = "usrp-uio";
+		reg = <0x40018000 0x4000>;
+		reg-names = "dboard-regs-1";
+		status = "okay";
+	};
+
+	uio@42100000 {
+		compatible = "usrp-uio";
+		reg = <0x42100000 0x1000>;
+		reg-names = "dboard-jtag-0";
+		status = "okay";
+	};
+
+	uio@42200000 {
+		compatible = "usrp-uio";
+		reg = <0x42200000 0x1000>;
+		reg-names = "dboard-jtag-1";
+		status = "okay";
+	};
+
+};
+
+&spi0 {
+	status = "okay";
+
+	cs-gpios = <0>, <0>, <0>, <&gpio0 62 0>;
+
+	spidev0: spidev@0 {
+		compatible = "rohm,dh2228fv";
+		reg = <0>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+
+	spidev1: spidev@1 {
+		compatible = "rohm,dh2228fv";
+		reg = <1>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+
+	spidev2: spidev@2 {
+		compatible = "rohm,dh2228fv";
+		reg = <2>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+
+	spidev3: spidev@3 {
+		compatible = "rohm,dh2228fv";
+		reg = <3>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+};
+
+&spi1 {
+	status = "okay";
+
+	cs-gpios = <0>, <0>, <0>, <&gpio0 63 0>;
+
+	spidev4: spidev@0 {
+		compatible = "rohm,dh2228fv";
+		reg = <0>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+
+	spidev5: spidev@1 {
+		compatible = "rohm,dh2228fv";
+		reg = <1>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+
+	spidev6: spidev@2 {
+		compatible = "rohm,dh2228fv";
+		reg = <2>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+
+	spidev7: spidev@3 {
+		compatible = "rohm,dh2228fv";
+		reg = <3>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+};
diff --git a/fpga/usrp3/top/n3xx/dts/n310-fpga.dtsi b/fpga/usrp3/top/n3xx/dts/n310-fpga.dtsi
new file mode 100644
index 000000000..3859c84f0
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/n310-fpga.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2017 National Instruments Corp
+ */
+
+&fpga_full {
+	firmware-name = "n310.bin";
+};
diff --git a/fpga/usrp3/top/n3xx/dts/n320-common.dtsi b/fpga/usrp3/top/n3xx/dts/n320-common.dtsi
new file mode 100644
index 000000000..e7fd557b3
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/n320-common.dtsi
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2018 National Instruments Corp
+ */
+
+&fpga_full {
+	uio@40010000 {
+		compatible = "usrp-uio";
+		reg = <0x40010000 0x2000>;
+		reg-names = "mboard-regs";
+		status = "okay";
+	};
+
+	uio@40014000 {
+		compatible = "usrp-uio";
+		reg = <0x40014000 0x4000>;
+		reg-names = "dboard-regs-0";
+		status = "okay";
+	};
+
+	uio@40018000 {
+		compatible = "usrp-uio";
+		reg = <0x40018000 0x4000>;
+		reg-names = "dboard-regs-1";
+		status = "okay";
+	};
+
+	uio@42100000 {
+		compatible = "usrp-uio";
+		reg = <0x42100000 0x1000>;
+		reg-names = "dboard-jtag-0";
+		status = "okay";
+	};
+
+	uio@42200000 {
+		compatible = "usrp-uio";
+		reg = <0x42200000 0x1000>;
+		reg-names = "dboard-jtag-1";
+		status = "okay";
+	};
+};
+
+&spi0 {
+	status = "okay";
+
+	cs-gpios = <0>, <0>, <0>, <&gpio0 67 0>, <&gpio0 68 0>;
+
+	spidev0: spidev@0 {
+		compatible = "rohm,dh2228fv";
+		reg = <0>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+
+	spidev1: spidev@1 {
+		compatible = "rohm,dh2228fv";
+		reg = <1>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+
+	spidev2: spidev@2 {
+		compatible = "rohm,dh2228fv";
+		reg = <2>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+
+	spidev3: spidev@3 {
+		compatible = "rohm,dh2228fv";
+		reg = <3>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+
+	spidev4: spidev@4 {
+		compatible = "rohm,dh2228fv";
+		reg = <4>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+};
+
+&spi1 {
+	status = "okay";
+
+	cs-gpios = <0>, <0>, <0>, <&gpio0 69 0>, <&gpio0 70 0>;
+
+	spidev5: spidev@0 {
+		compatible = "rohm,dh2228fv";
+		reg = <0>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+
+	spidev6: spidev@1 {
+		compatible = "rohm,dh2228fv";
+		reg = <1>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+
+	spidev7: spidev@2 {
+		compatible = "rohm,dh2228fv";
+		reg = <2>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+
+	spidev8: spidev@3 {
+		compatible = "rohm,dh2228fv";
+		reg = <3>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+
+	spidev9: spidev@4 {
+		compatible = "rohm,dh2228fv";
+		reg = <4>;
+		status = "okay";
+		spi-max-frequency = <1000000>;
+	};
+};
+
+&usrpio_i2c0 {
+	rhodium_lodist_gpio: rhodium-lodist-gpio@22 {
+		compatible = "nxp,tca6424";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
diff --git a/fpga/usrp3/top/n3xx/dts/n320-fpga.dtsi b/fpga/usrp3/top/n3xx/dts/n320-fpga.dtsi
new file mode 100644
index 000000000..5934138a9
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/n320-fpga.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2018 National Instruments Corp
+ */
+
+&fpga_full {
+	firmware-name = "n320.bin";
+};
diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_AA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_AA.dts
new file mode 100644
index 000000000..f0099f08b
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_AA.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2017 National Instruments Corp
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "n300-fpga.dtsi"
+
+&fpga_full {
+	uio@40004000 {
+		compatible = "usrp-uio";
+		reg = <0x40004000 0x1000>;
+		reg-names = "misc-auro-regs0";
+		status = "okay";
+	};
+
+
+	uio@4000c000 {
+		compatible = "usrp-uio";
+		reg = <0x4000c000 0x1000>;
+		reg-names = "misc-auro-regs1";
+		status = "okay";
+	};
+};
+
+#include "n300-common.dtsi"
+#include "dma-common.dtsi"
diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_HA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_HA.dts
new file mode 100644
index 000000000..6cdce8022
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_HA.dts
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2017 National Instruments Corp
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "n300-fpga.dtsi"
+
+&fpga_full {
+	nixge0: ethernet@40000000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40000000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth1_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 29 4>, <0 30 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+
+		fixed-link {
+			speed = <1000>;
+			full-duplex;
+ 			/* 114 = 54 (MIOs) + 60 (EMIO 60) */
+ 			link-gpios = <&gpio0 114 0>;
+		};
+	};
+
+	uio@40006000 {
+		compatible = "usrp-uio";
+		reg = <0x40006000 0x2000>;
+		reg-names = "misc-enet-regs0";
+		status = "okay";
+	};
+
+	uio@4000c000 {
+		compatible = "usrp-uio";
+		reg = <0x4000c000 0x1000>;
+		reg-names = "misc-auro-regs1";
+		status = "okay";
+	};
+};
+
+#include "n300-common.dtsi"
+#include "dma-common.dtsi"
diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_HG.dts b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_HG.dts
new file mode 100644
index 000000000..7f94f1126
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_HG.dts
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2017 National Instruments Corp
+ *
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "n300-fpga.dtsi"
+
+&fpga_full {
+	nixge0: ethernet@40000000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40000000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth1_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 29 4>, <0 30 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+
+		fixed-link {
+			speed = <1000>;
+			full-duplex;
+			/* 114 = 54 (MIOs) + 60 (EMIO 60) */
+			link-gpios = <&gpio0 114 0>;
+		};
+	};
+
+	uio@40006000 {
+		compatible = "usrp-uio";
+		reg = <0x40006000 0x2000>;
+		reg-names = "misc-enet-regs0";
+		status = "okay";
+	};
+
+	nixge1: ethernet@40008000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40008000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth2_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 31 4>, <0 32 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+		phy-handle = <&ethernet_phy2>;
+
+		mdio {
+			ethernet_phy2: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <4>;
+			};
+		};
+	};
+
+	uio@4000e000 {
+		compatible = "usrp-uio";
+		reg = <0x4000e000 0x2000>;
+		reg-names = "misc-enet-regs1";
+		status = "okay";
+	};
+};
+
+#include "n300-common.dtsi"
+#include "dma-common.dtsi"
diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_WX.dts b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_WX.dts
new file mode 100644
index 000000000..904149270
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_WX.dts
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2018 National Instruments Corp
+ *
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "n300-fpga.dtsi"
+
+&fpga_full {
+	uio@40006000 {
+		compatible = "usrp-uio";
+		reg = <0x40006000 0x2000>;
+		reg-names = "misc-enet-regs0";
+		status = "okay";
+	};
+
+	nixge1: ethernet@40008000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40008000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth2_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 31 4>, <0 32 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+		phy-handle = <&ethernet_phy2>;
+
+		mdio {
+			ethernet_phy2: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <4>;
+			};
+		};
+	};
+
+	uio@4000e000 {
+		compatible = "usrp-uio";
+		reg = <0x4000e000 0x2000>;
+		reg-names = "misc-enet-regs1";
+		status = "okay";
+	};
+
+	uio@43d40000 {
+		compatible = "usrp-uio";
+		reg = <0x43d40000 0x40000>;
+		reg-names = "wr-regs";
+		status = "okay";
+	};
+
+	uart2@42c00000 {
+		compatible = "xlnx,xps-uartlite-1.00.a";
+		reg = <0x42c00000 0x1000>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 54 4>;
+	};
+};
+
+#include "n300-common.dtsi"
+#include "dma-common.dtsi"
diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_XA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_XA.dts
new file mode 100644
index 000000000..984591d08
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_XA.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2017 National Instruments Corp
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "n300-fpga.dtsi"
+
+&fpga_full {
+	nixge0: ethernet@40000000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40000000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth1_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 29 4>, <0 30 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+		phy-handle = <&ethernet_phy1>;
+
+		mdio {
+			ethernet_phy1: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <4>;
+			};
+		};
+	};
+
+	uio@40006000 {
+		compatible = "usrp-uio";
+		reg = <0x40006000 0x2000>;
+		reg-names = "misc-enet-regs0";
+		status = "okay";
+	};
+
+	uio@4000c000 {
+		compatible = "usrp-uio";
+		reg = <0x4000c000 0x1000>;
+		reg-names = "misc-auro-regs1";
+		status = "okay";
+	};
+};
+
+#include "n300-common.dtsi"
+#include "dma-common.dtsi"
diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_XG.dts b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_XG.dts
new file mode 100644
index 000000000..3f01d18b1
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_XG.dts
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2017 National Instruments Corp
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "n300-fpga.dtsi"
+
+&fpga_full {
+	nixge0: ethernet@40000000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40000000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth1_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 29 4>, <0 30 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+		phy-handle = <&ethernet_phy1>;
+
+		mdio {
+			ethernet_phy1: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <4>;
+			};
+		};
+	};
+
+	uio@40006000 {
+		compatible = "usrp-uio";
+		reg = <0x40006000 0x2000>;
+		reg-names = "misc-enet-regs0";
+		status = "okay";
+	};
+
+	nixge1: ethernet@40008000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40008000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth2_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 31 4>, <0 32 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+		phy-handle = <&ethernet_phy2>;
+
+		mdio {
+			ethernet_phy2: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <4>;
+			};
+		};
+	};
+
+	uio@4000e000 {
+		compatible = "usrp-uio";
+		reg = <0x4000e000 0x2000>;
+		reg-names = "misc-enet-regs1";
+		status = "okay";
+	};
+};
+
+#include "n300-common.dtsi"
+#include "dma-common.dtsi"
diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_AA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_AA.dts
new file mode 100644
index 000000000..637e6371d
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_AA.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2017 National Instruments Corp
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "n310-fpga.dtsi"
+
+&fpga_full {
+	uio@40004000 {
+		compatible = "usrp-uio";
+		reg = <0x40004000 0x1000>;
+		reg-names = "misc-auro-regs0";
+		status = "okay";
+	};
+
+
+	uio@4000c000 {
+		compatible = "usrp-uio";
+		reg = <0x4000c000 0x1000>;
+		reg-names = "misc-auro-regs1";
+		status = "okay";
+	};
+};
+
+#include "n310-common.dtsi"
+#include "dma-common.dtsi"
diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_HA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_HA.dts
new file mode 100644
index 000000000..bc03736e3
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_HA.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2017 National Instruments Corp
+ *
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "n310-fpga.dtsi"
+
+&fpga_full {
+	nixge0: ethernet@40000000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40000000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth1_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 29 4>, <0 30 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+
+		fixed-link {
+			speed = <1000>;
+			full-duplex;
+			/* 114 = 54 (MIOs) + 60 (EMIO 60) */
+			link-gpios = <&gpio0 114 0>;
+		};
+	};
+
+	uio@40006000 {
+		compatible = "usrp-uio";
+		reg = <0x40006000 0x2000>;
+		reg-names = "misc-enet-regs0";
+		status = "okay";
+	};
+
+	uio@4000c000 {
+		compatible = "usrp-uio";
+		reg = <0x4000c000 0x1000>;
+		reg-names = "misc-auro-regs1";
+		status = "okay";
+	};
+};
+
+#include "n310-common.dtsi"
+#include "dma-common.dtsi"
diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_HG.dts b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_HG.dts
new file mode 100644
index 000000000..0039d3b0a
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_HG.dts
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2017 National Instruments Corp
+ *
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "n310-fpga.dtsi"
+
+&fpga_full{
+	nixge0: ethernet@40000000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40000000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth1_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 29 4>, <0 30 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+
+		fixed-link {
+			speed = <1000>;
+			full-duplex;
+			/* 114 = 54 (MIOs) + 60 (EMIO 60) */
+			link-gpios = <&gpio0 114 0>;
+		};
+
+	};
+
+	uio@40006000 {
+		compatible = "usrp-uio";
+		reg = <0x40006000 0x2000>;
+		reg-names = "misc-enet-regs0";
+		status = "okay";
+	};
+
+	nixge1: ethernet@40008000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40008000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth2_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 31 4>, <0 32 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+		phy-handle = <&ethernet_phy2>;
+
+		mdio {
+			ethernet_phy2: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <4>;
+			};
+		};
+	};
+
+	uio@4000e000 {
+		compatible = "usrp-uio";
+		reg = <0x4000e000 0x2000>;
+		reg-names = "misc-enet-regs1";
+		status = "okay";
+	};
+};
+
+#include "n310-common.dtsi"
+#include "dma-common.dtsi"
diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_WX.dts b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_WX.dts
new file mode 100644
index 000000000..41ee3c0a8
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_WX.dts
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2018 National Instruments Corp
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "n310-fpga.dtsi"
+
+&fpga_full {
+	uio@40006000 {
+		compatible = "usrp-uio";
+		reg = <0x40006000 0x2000>;
+		reg-names = "misc-enet-regs0";
+		status = "okay";
+	};
+
+	nixge1: ethernet@40008000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40008000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth2_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 31 4>, <0 32 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+		phy-handle = <&ethernet_phy2>;
+
+		mdio {
+			ethernet_phy2: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <4>;
+			};
+		};
+	};
+
+	uio@4000e000 {
+		compatible = "usrp-uio";
+		reg = <0x4000e000 0x2000>;
+		reg-names = "misc-enet-regs1";
+		status = "okay";
+	};
+
+	uio@43d40000 {
+		compatible = "usrp-uio";
+		reg = <0x43d40000 0x40000>;
+		reg-names = "wr-regs";
+		status = "okay";
+	};
+
+	uart2@42c00000 {
+		compatible = "xlnx,xps-uartlite-1.00.a";
+		reg = <0x42c00000 0x1000>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 54 4>;
+	};
+};
+
+#include "n310-common.dtsi"
+#include "dma-common.dtsi"
diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_XA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_XA.dts
new file mode 100644
index 000000000..0838595dd
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_XA.dts
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2017 National Instruments Corp
+ *
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "n310-fpga.dtsi"
+
+&fpga_full {
+	nixge0: ethernet@40000000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40000000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth1_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 29 4>, <0 30 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+		phy-handle = <&ethernet_phy1>;
+
+		mdio {
+			ethernet_phy1: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <4>;
+			};
+		};
+	};
+
+	uio@40006000 {
+		compatible = "usrp-uio";
+		reg = <0x40006000 0x2000>;
+		reg-names = "misc-enet-regs0";
+		status = "okay";
+	};
+
+	uio@4000c000 {
+		compatible = "usrp-uio";
+		reg = <0x4000c000 0x1000>;
+		reg-names = "misc-auro-regs1";
+		status = "okay";
+	};
+};
+
+#include "n310-common.dtsi"
+#include "dma-common.dtsi"
diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_XG.dts b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_XG.dts
new file mode 100644
index 000000000..204f91515
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_XG.dts
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2017 National Instruments Corp
+ *
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "n310-fpga.dtsi"
+
+&fpga_full {
+	nixge0: ethernet@40000000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40000000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth1_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 29 4>, <0 30 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+		phy-handle = <&ethernet_phy1>;
+
+		mdio {
+			ethernet_phy1: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <4>;
+			};
+		};
+	};
+
+	uio@40006000 {
+		compatible = "usrp-uio";
+		reg = <0x40006000 0x2000>;
+		reg-names = "misc-enet-regs0";
+		status = "okay";
+	};
+
+	nixge1: ethernet@40008000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40008000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth2_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 31 4>, <0 32 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+		phy-handle = <&ethernet_phy2>;
+
+		mdio {
+			ethernet_phy2: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <4>;
+			};
+		};
+	};
+
+	uio@4000e000 {
+		compatible = "usrp-uio";
+		reg = <0x4000e000 0x2000>;
+		reg-names = "misc-enet-regs1";
+		status = "okay";
+	};
+};
+
+#include "n310-common.dtsi"
+#include "dma-common.dtsi"
diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_AQ.dts b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_AQ.dts
new file mode 100644
index 000000000..6382192b8
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_AQ.dts
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2018 National Instruments Corp
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "n320-fpga.dtsi"
+
+&fpga_full {
+	nixge0: ethernet@40000000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40000000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth1_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 29 4>, <0 30 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+		phy-handle = <&ethernet_phy1>;
+
+		mdio {
+			ethernet_phy1: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <4>;
+			};
+		};
+	};
+
+	uio@40006000 {
+		compatible = "usrp-uio";
+		reg = <0x40006000 0x2000>;
+		reg-names = "misc-enet-regs0";
+		status = "okay";
+	};
+
+	nixge1: ethernet@40008000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40008000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth2_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 31 4>, <0 32 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+		phy-handle = <&ethernet_phy2>;
+
+		mdio {
+			ethernet_phy2: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <4>;
+			};
+		};
+	};
+
+	uio@4000e000 {
+		compatible = "usrp-uio";
+		reg = <0x4000e000 0x2000>;
+		reg-names = "misc-enet-regs1";
+		status = "okay";
+	};
+
+	uio@40020000 {
+		compatible = "usrp-uio";
+		reg = <0x40020000 0x1000>;
+		reg-names = "misc-auro-regs0";
+		status = "okay";
+	};
+
+	uio@40024000 {
+		compatible = "usrp-uio";
+		reg = <0x40024000 0x1000>;
+		reg-names = "misc-auro-regs1";
+		status = "okay";
+	};
+
+	uio@40028000 {
+		compatible = "usrp-uio";
+		reg = <0x40028000 0x1000>;
+		reg-names = "misc-auro-regs2";
+		status = "okay";
+	};
+
+
+	uio@4002c000 {
+		compatible = "usrp-uio";
+		reg = <0x4002c000 0x1000>;
+		reg-names = "misc-auro-regs3";
+		status = "okay";
+	};
+
+	qsfp_i2c: qsfp-i2c@43D80000 {
+		compatible = "xlnx,xps-iic-2.00.a";
+		clocks = <&clkc 15>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 55 4>;
+		reg = <0x43D80000 0x10000>;
+	};
+};
+
+#include "n320-common.dtsi"
+#include "dma-common.dtsi"
diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_HG.dts b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_HG.dts
new file mode 100644
index 000000000..d08aeb87b
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_HG.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2018 National Instruments Corp
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "n320-fpga.dtsi"
+
+&fpga_full {
+	nixge0: ethernet@40000000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40000000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth1_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 29 4>, <0 30 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+
+		fixed-link {
+			speed = <1000>;
+			full-duplex;
+			/* 114 = 54 (MIOs) + 60 (EMIO 60) */
+			link-gpios = <&gpio0 114 0>;
+		};
+	};
+
+	uio@40006000 {
+		compatible = "usrp-uio";
+		reg = <0x40006000 0x2000>;
+		reg-names = "misc-enet-regs0";
+		status = "okay";
+	};
+
+	nixge1: ethernet@40008000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40008000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth2_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 31 4>, <0 32 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+		phy-handle = <&ethernet_phy2>;
+
+		mdio {
+			ethernet_phy2: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <4>;
+			};
+		};
+	};
+
+	uio@4000e000 {
+		compatible = "usrp-uio";
+		reg = <0x4000e000 0x2000>;
+		reg-names = "misc-enet-regs1";
+		status = "okay";
+	};
+};
+
+#include "n320-common.dtsi"
+#include "dma-common.dtsi"
diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_WX.dts b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_WX.dts
new file mode 100644
index 000000000..8b133ce98
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_WX.dts
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2018 National Instruments Corp
+ *
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "n320-fpga.dtsi"
+
+&fpga_full {
+	uio@40006000 {
+		compatible = "usrp-uio";
+		reg = <0x40006000 0x2000>;
+		reg-names = "misc-enet-regs0";
+		status = "okay";
+	};
+
+	nixge1: ethernet@40008000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40008000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth2_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 31 4>, <0 32 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+		phy-handle = <&ethernet_phy2>;
+
+		mdio {
+			ethernet_phy2: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <4>;
+			};
+		};
+	};
+
+	uio@4000e000 {
+		compatible = "usrp-uio";
+		reg = <0x4000e000 0x2000>;
+		reg-names = "misc-enet-regs1";
+		status = "okay";
+	};
+
+	uio@43d40000 {
+		compatible = "usrp-uio";
+		reg = <0x43d40000 0x40000>;
+		reg-names = "wr-regs";
+		status = "okay";
+	};
+
+	uart2@42c00000 {
+		compatible = "xlnx,xps-uartlite-1.00.a";
+		reg = <0x42c00000 0x1000>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 54 4>;
+	};
+};
+
+#include "n320-common.dtsi"
+#include "dma-common.dtsi"
diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_XG.dts b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_XG.dts
new file mode 100644
index 000000000..f585dbddb
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_XG.dts
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2018 National Instruments Corp
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "n320-fpga.dtsi"
+
+&fpga_full {
+	nixge0: ethernet@40000000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40000000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth1_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 29 4>, <0 30 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+		phy-handle = <&ethernet_phy1>;
+
+		mdio {
+			ethernet_phy1: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <4>;
+			};
+		};
+	};
+
+	uio@40006000 {
+		compatible = "usrp-uio";
+		reg = <0x40006000 0x2000>;
+		reg-names = "misc-enet-regs0";
+		status = "okay";
+	};
+
+	nixge1: ethernet@40008000 {
+		compatible = "ni,xge-enet-2.00";
+		reg = <0x40008000 0x6000>;
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth2_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 31 4>, <0 32 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+		phy-handle = <&ethernet_phy2>;
+
+		mdio {
+			ethernet_phy2: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <4>;
+			};
+		};
+	};
+
+	uio@4000e000 {
+		compatible = "usrp-uio";
+		reg = <0x4000e000 0x2000>;
+		reg-names = "misc-enet-regs1";
+		status = "okay";
+	};
+};
+
+#include "n320-common.dtsi"
+#include "dma-common.dtsi"
diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_XQ.dts b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_XQ.dts
new file mode 100644
index 000000000..037447932
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_XQ.dts
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2018 National Instruments Corp
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "n320-fpga.dtsi"
+
+&fpga_full {
+	nixge0: ethernet@40000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "ni,xge-enet-3.00";
+		reg = <0x40000000 0x4000
+		       0x40020000 0x2000>;
+		reg-names = "dma", "ctrl";
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth1_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 29 4>, <0 30 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+		phy-handle = <&ethernet_phy1>;
+
+		mdio {
+			ethernet_phy1: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <4>;
+			};
+		};
+	};
+
+	uio@40022000 {
+		compatible = "usrp-uio";
+		reg = <0x40022000 0x2000>;
+		reg-names = "misc-enet-regs0";
+		status = "okay";
+	};
+
+	nixge1: ethernet@40008000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "ni,xge-enet-3.00";
+		reg = <0x40008000 0x4000
+		       0x40024000 0x2000>;
+		reg-names = "dma", "ctrl";
+
+		clocks = <&clkc 15>;
+		clock-names = "bus_clk";
+
+		nvmem-cells = <&eth2_addr>;
+		nvmem-cell-names = "address";
+
+		interrupts = <0 31 4>, <0 32 4>;
+		interrupt-names = "rx", "tx";
+		interrupt-parent = <&intc>;
+		status = "okay";
+
+		phy-mode = "xgmii";
+		phy-handle = <&ethernet_phy2>;
+
+		mdio {
+			ethernet_phy2: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <4>;
+			};
+		};
+	};
+
+	uio@40026000 {
+		compatible = "usrp-uio";
+		reg = <0x40026000 0x2000>;
+		reg-names = "misc-enet-regs1";
+		status = "okay";
+	};
+
+	uio@40006000 {
+		compatible = "usrp-uio";
+		reg = <0x40006000 0x2000>;
+		reg-names = "misc-enet-regs2";
+		status = "okay";
+	};
+
+	uio@43d40000 {
+		compatible = "usrp-uio";
+		reg = <0x43d40000 0x40000>;
+		reg-names = "wr-regs";
+		status = "okay";
+	};
+
+	uart2@42c00000 {
+		compatible = "xlnx,xps-uartlite-1.00.a";
+		reg = <0x42c00000 0x1000>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 54 4>;
+	};
+
+	qsfp_i2c: qsfp-i2c@43D80000 {
+		compatible = "xlnx,xps-iic-2.00.a";
+		clocks = <&clkc 15>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 55 4>;
+		reg = <0x43D80000 0x10000>;
+	};
+};
+
+#include "n320-common.dtsi"
+#include "dma-common.dtsi"