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| author | Wade Fife <wade.fife@ettus.com> | 2020-08-17 12:43:12 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-08-19 12:28:22 -0500 |
| commit | 2e910c5307702c3f3efb6dc8cb60f4f71ce11e67 (patch) | |
| tree | a46d69540c9f4b5ec336d8edb2110de4ea492751 /fpga/usrp3/top/n3xx/dboards/mg/n3xx.v | |
| parent | c9d55d870dbccbc07ca9a7afaf2e0ac64944111c (diff) | |
| download | uhd-2e910c5307702c3f3efb6dc8cb60f4f71ce11e67.tar.gz uhd-2e910c5307702c3f3efb6dc8cb60f4f71ce11e67.tar.bz2 uhd-2e910c5307702c3f3efb6dc8cb60f4f71ce11e67.zip | |
fpga: e31x: Fix timeout for timekeeper registers
Fixing an issue in which a very slow radio_clk (due to low sample clock
rate) could cause bus transactions to be issued to the timekeeper
faster than it could service them, resulting in a timeout. This change
replaces RegPort with CtrlPort so that proper flow control can be
maintained to the timekeeper.
Diffstat (limited to 'fpga/usrp3/top/n3xx/dboards/mg/n3xx.v')
0 files changed, 0 insertions, 0 deletions