diff options
| author | Martin Braun <martin.braun@ettus.com> | 2020-01-23 16:10:22 -0800 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2020-01-28 09:35:36 -0800 |
| commit | bafa9d95453387814ef25e6b6256ba8db2df612f (patch) | |
| tree | 39ba24b5b67072d354775272e687796bb511848d /fpga/usrp3/top/e320 | |
| parent | 3075b981503002df3115d5f1d0b97d2619ba30f2 (diff) | |
| download | uhd-bafa9d95453387814ef25e6b6256ba8db2df612f.tar.gz uhd-bafa9d95453387814ef25e6b6256ba8db2df612f.tar.bz2 uhd-bafa9d95453387814ef25e6b6256ba8db2df612f.zip | |
Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.
This commit also updates the license files and paths therein.
We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.
== Original Codebase and Rebasing ==
The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/
It can be used for bisecting, reference, and a more detailed history.
The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.
If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:
- Create a directory to store patches (this should be an empty
directory):
mkdir ~/patches
- Now make sure that your FPGA codebase is based on the same state as
the code that was merged:
cd src/fpga # Or wherever your FPGA code is stored
git rebase v4.0.0.0-pre-uhd-merge
Note: The rebase command may look slightly different depending on what
exactly you're trying to rebase.
- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:
git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches
Note: Make sure that only patches are stored in your output directory.
It should otherwise be empty. Make sure that you picked the correct
range of commits, and only commits you wanted to rebase were exported
as patch files.
- Go to the UHD repository and apply the patches:
cd src/uhd # Or wherever your UHD repository is stored
git am --directory fpga ~/patches/*
rm -rf ~/patches # This is for cleanup
== Contributors ==
The following people have contributed mainly to these files (this list
is not complete):
Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Diffstat (limited to 'fpga/usrp3/top/e320')
67 files changed, 54529 insertions, 0 deletions
diff --git a/fpga/usrp3/top/e320/.gitignore b/fpga/usrp3/top/e320/.gitignore new file mode 100644 index 000000000..1b0a8a728 --- /dev/null +++ b/fpga/usrp3/top/e320/.gitignore @@ -0,0 +1,8 @@ +build +build-* +isim* +fuse* +tmp* +*.log +*.jou +*impact* diff --git a/fpga/usrp3/top/e320/Makefile b/fpga/usrp3/top/e320/Makefile new file mode 100644 index 000000000..b15d4317c --- /dev/null +++ b/fpga/usrp3/top/e320/Makefile @@ -0,0 +1,100 @@ +# +# Copyright 2018-2019 Ettus Research, a National Instruments Brand +# + +# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target +##------------------- +##USRP E3XX FPGA Help +##------------------- +##Usage: +## make <Targets> <Options> +## +##Output: +## build/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header +## build/usrp_<product>_fpga_<image_type>.dts: Device tree source file +## build/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary) + +1G_DEFS=SFP_1GBE=1 BUILD_1G=1 $(OPTIONS) +XG_DEFS=SFP_10GBE=1 BUILD_10G=1 $(OPTIONS) +AA_DEFS=SFP_AURORA=1 BUILD_AURORA=1 $(OPTIONS) + +# Set build option (check RTL, run synthesis, or do a full build) +ifndef TARGET + ifdef CHECK + TARGET = rtl + else ifdef SYNTH + TARGET = synth + else + TARGET = bin + endif +endif +TOP ?= e320 + +DEFAULT_IMAGE_CORE_FILE_E320=e320_rfnoc_image_core.v +DEFAULT_EDGE_FILE_E320=$(abspath e320_static_router.hex) + +# vivado_build($1=Device, $2=Definitions) +vivado_build = make -f Makefile.e320.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_$1) + +# post_build($1=Device, $2=Option) +ifeq ($(TARGET),bin) + post_build = @\ + mkdir -p build; \ + echo "Exporting bitstream file..."; \ + cp build-$(1)_$(2)/e320.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \ + echo "Exporting build report..."; \ + cp build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \ + echo "Build DONE ... $(1)_$(2)"; +else + post_build = @echo "Skipping bitfile export." +endif + +## +##Supported Targets +##----------------- + +all: E320_1G E320_XG ##(Default target) + +##E320_1G: 1GigE on SFP+ Port. +E320_1G: build/usrp_e320_fpga_1G.dts + $(call vivado_build,E320,$(1G_DEFS) E320=1) + $(call post_build,E320,1G) + +##E320_XG: 10GigE on SFP+ Port. +E320_XG: build/usrp_e320_fpga_XG.dts + $(call vivado_build,E320,$(XG_DEFS) E320=1) + $(call post_build,E320,XG) + +##E320_AA: Aurora on SFP+ Port. +E320_AA: build/usrp_e320_fpga_AA.dts + $(call vivado_build,E320,$(AA_DEFS) E320=1) + $(call post_build,E320,AA) + + +build/%.dts: dts/%.dts dts/*.dtsi + -mkdir -p build + ${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $< + +clean: ##Clean up all target build outputs. + @echo "Cleaning targets..." + @rm -rf build-E3*_* + @rm -rf build + +cleanall: ##Clean up all target and ip build outputs. + @echo "Cleaning targets and IP..." + @rm -rf build-ip + @rm -rf build-E3*_* + @rm -rf build + +help: ##Show this help message. + @grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//' + +## +##Supported Options +##----------------- +##GUI=1 Launch the build in the Vivado GUI. +##CHECK=1 Launch the syntax checker instead of building a bitfile. +##SYNTH=1 Launch the build but stop after synthesis. +##TOP=<module> Specify a top module for syntax checking. (Optional. Default is the bitfile top) + +.PHONY: all clean cleanall help diff --git a/fpga/usrp3/top/e320/Makefile.e320.inc b/fpga/usrp3/top/e320/Makefile.e320.inc new file mode 100644 index 000000000..a20e6c0ff --- /dev/null +++ b/fpga/usrp3/top/e320/Makefile.e320.inc @@ -0,0 +1,141 @@ +# +# Copyright 2018-2019 Ettus Research, a National Instruments Brand +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = <Input arg> +# NAME = <Input arg> +# PART_ID = <Input arg> +# ARCH = <Input arg> + +################################################## +# Include other makefiles +################################################## + +BASE_DIR = $(abspath ..) +IP_DIR = $(abspath ./ip) +include $(BASE_DIR)/../tools/make/viv_design_builder.mak + +include $(IP_DIR)/Makefile.inc +include ../n3xx/coregen_dsp/Makefile.srcs +include $(LIB_DIR)/ip/Makefile.inc +include $(LIB_DIR)/hls/Makefile.inc +include $(LIB_DIR)/control/Makefile.srcs +include $(LIB_DIR)/fifo/Makefile.srcs +include $(LIB_DIR)/simple_gemac/Makefile.srcs +include $(LIB_DIR)/axi/Makefile.srcs +include $(LIB_DIR)/timing/Makefile.srcs +include $(LIB_DIR)/packet_proc/Makefile.srcs +include $(LIB_DIR)/xge/Makefile.srcs +include $(LIB_DIR)/xge_interface/Makefile.srcs +include $(LIB_DIR)/dsp/Makefile.srcs +include $(LIB_DIR)/io_cap_gen/Makefile.srcs +include $(LIB_DIR)/rfnoc/Makefile.srcs +# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and +# DUC, and of course the radio. Any other block needs to use the +# RFNOC_OOT_MAKEFILE_SRCS variable (see below). +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs +# If out-of-tree modules want to be compiled into this image, then they need to +# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files. +# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual +# source files. +include $(RFNOC_OOT_MAKEFILE_SRCS) + +IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE) +EDGE_FILE ?= $(DEFAULT_EDGE_FILE) + +################################################## +# Sources +################################################## +TOP_SRCS = \ +e320.v \ +e320_core.v \ +e320_clocking.v \ +n3xx_sfp_wrapper.v \ +n3xx_mgt_io_core.v \ +$(IMAGE_CORE) + +MB_XDC = \ +mb_pins.xdc \ +mb_timing.xdc + +ifdef BUILD_10G +MB_XDC += $(abspath e320_10ge.xdc) +endif + +ifdef BUILD_1G +MB_XDC += $(abspath e320_1ge.xdc) +endif + +ifdef BUILD_AURORA +MB_XDC += $(abspath e320_aurora.xdc) +endif + +ifdef SFP_10GBE +MB_XDC += $(abspath e320_10ge_port0.xdc) +endif + +ifndef NO_DRAM_FIFOS +DRAM_SRCS = $(IP_DRAM_XCI_SRCS) $(abspath e320_dram.xdc) +else +DRAM_SRCS = +endif + +# The XDC files must be read in a specific order, motherboard first and then daughterboard. +# Outside of that, all the other sources can be read in any order desired. +DESIGN_SRCS = \ +$(abspath $(TOP_SRCS)) \ +$(CONTROL_LIB_SRCS) \ +$(IP_XCI_SRCS) \ +$(TEN_GIGE_PHY_SRCS) \ +$(XGE_SRCS) \ +$(XGE_INTERFACE_SRCS) \ +$(PACKET_PROC_SRCS) \ +$(AXI_SRCS) \ +$(FIFO_SRCS) \ +$(ONE_GIGE_PHY_SRCS) \ +$(SIMPLE_GEMAC_SRCS) \ +$(AURORA_PHY_SRCS) \ +$(BD_SRCS) \ +$(TIMING_SRCS) \ +$(CAT_CAP_GEN_SRCS) \ +$(DRAM_SRCS) \ +$(COREGEN_DSP_SRCS) \ +$(DSP_SRCS) \ +$(LIB_IP_XCI_SRCS) \ +$(LIB_HLS_IP_SRCS) \ +$(EXTRAM_SRCS) \ +$(CAP_GEN_GENERIC_SRCS) \ +$(RFNOC_SRCS) \ +$(RFNOC_OOT_SRCS) \ +$(RFNOC_FRAMEWORK_SRCS) \ +$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \ +$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \ +$(RFNOC_BLOCK_RADIO_SRCS) \ +$(abspath $(MB_XDC)) + +EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(EDGE_FILE)" + +################################################## +# Dependency Targets +################################################## +.SECONDEXPANSION: + +VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) + +# DESIGN_SRCS and VERILOG_DEFS must be defined +bin: .prereqs $$(DESIGN_SRCS) ip + $(call BUILD_VIVADO_DESIGN,$(abspath ./build_e320.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID)) + +synth: .prereqs $$(DESIGN_SRCS) ip + $(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) + +rtl: .prereqs $$(DESIGN_SRCS) ip + $(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) + +.PHONY: bin rtl diff --git a/fpga/usrp3/top/e320/build_e320.tcl b/fpga/usrp3/top/e320/build_e320.tcl new file mode 100644 index 000000000..757195865 --- /dev/null +++ b/fpga/usrp3/top/e320/build_e320.tcl @@ -0,0 +1,39 @@ +# +# Copyright 2016 Ettus Research +# + +source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl +source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl + +# STEP#1: Create project, add sources, refresh IP +vivado_utils::initialize_project + +# STEP#2: Run synthesis +vivado_utils::synthesize_design +vivado_utils::generate_post_synth_reports + +# STEP#3: Run implementation strategy +set e3xx_strategy [dict create] +dict set e3xx_strategy "opt_design.is_enabled" 1 +dict set e3xx_strategy "opt_design.directive" "Default" +dict set e3xx_strategy "post_opt_power_opt_design.is_enabled" 0 +dict set e3xx_strategy "place_design.directive" "Default" +dict set e3xx_strategy "post_place_power_opt_design.is_enabled" 0 +dict set e3xx_strategy "post_place_phys_opt_design.is_enabled" 1 +dict set e3xx_strategy "post_place_phys_opt_design.directive" "Default" +dict set e3xx_strategy "route_design.directive" "Default" +dict set e3xx_strategy "route_design.more_options" "-tns_cleanup" +dict set e3xx_strategy "post_route_phys_opt_design.is_enabled" 1 +dict set e3xx_strategy "post_route_phys_opt_design.directive" "Default" +vivado_strategies::implement_design $e3xx_strategy + +# STEP#4: Generate reports +vivado_utils::generate_post_route_reports + +# STEP#5: Generate a bitstream, netlist and debug probes +set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [get_designs *] +set byte_swap_bin 1 +vivado_utils::write_implementation_outputs $byte_swap_bin + +# Cleanup +vivado_utils::close_batch_project diff --git a/fpga/usrp3/top/e320/dev_config.json b/fpga/usrp3/top/e320/dev_config.json new file mode 100644 index 000000000..eb6ce9dc0 --- /dev/null +++ b/fpga/usrp3/top/e320/dev_config.json @@ -0,0 +1,3 @@ +{ + "warning": { "ignore": ["."]} +} diff --git a/fpga/usrp3/top/e320/dts/dma-common.dtsi b/fpga/usrp3/top/e320/dts/dma-common.dtsi new file mode 100644 index 000000000..0f3dde41d --- /dev/null +++ b/fpga/usrp3/top/e320/dts/dma-common.dtsi @@ -0,0 +1,358 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +&fpga_full { + tx_dma0: dma@43CA0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CA0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma1: dma@43CB0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CB0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma2: dma@43CC0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CC0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma3: dma@43CD0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CD0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma4: dma@43CE0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CE0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma5: dma@43CF0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CF0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma0: dma@43C00000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C00000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma1: dma@43C10000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C10000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma2: dma@43C20000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C20000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma3: dma@43C30000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C30000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma4: dma@43C40000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C40000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma5: dma@43C50000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C50000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + + usrp_rx_dma0: usrp-rx-dma@43c00000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma0 0>; + dma-names = "dma"; + port-id = <0>; + status = "okay"; + + regmap = <&dma_conf0>; + offset = <0x0>; + }; + + usrp_rx_dma1: usrp-rx-dma@43c10000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma1 0>; + dma-names = "dma"; + port-id = <1>; + + regmap = <&dma_conf0>; + offset = <0x4>; + }; + + usrp_rx_dma2: usrp-rx-dma@43c20000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma2 0>; + dma-names = "dma"; + port-id = <2>; + + regmap = <&dma_conf0>; + offset = <0x8>; + }; + + usrp_rx_dma3: usrp-rx-dma@43c30000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma3 0>; + dma-names = "dma"; + port-id = <3>; + + regmap = <&dma_conf0>; + offset = <0xc>; + }; + + usrp_rx_dma4: usrp-rx-dma@43c40000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma4 0>; + dma-names = "dma"; + port-id = <4>; + + regmap = <&dma_conf0>; + offset = <0x10>; + }; + + usrp_rx_dma5: usrp-rx-dma@43c50000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma5 0>; + dma-names = "dma"; + port-id = <5>; + + regmap = <&dma_conf0>; + offset = <0x14>; + }; + + usrp_tx_dma0: usrp-tx-dma@43ca0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma0 0>; + dma-names = "dma"; + port-id = <0>; + }; + + usrp_tx_dma1: usrp-tx-dma@43cb0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma1 0>; + dma-names = "dma"; + port-id = <1>; + }; + + usrp_tx_dma2: usrp-tx-dma@43cc0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma2 0>; + dma-names = "dma"; + port-id = <2>; + status = "okay"; + }; + + usrp_tx_dma3: usrp-tx-dma@43cd0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma3 0>; + dma-names = "dma"; + port-id = <3>; + }; + + usrp_tx_dma4: usrp-tx-dma@43ce0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma4 0>; + dma-names = "dma"; + port-id = <4>; + status = "okay"; + }; + + usrp_tx_dma5: usrp-tx-dma@43cf0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma5 0>; + dma-names = "dma"; + port-id = <5>; + }; + + dma_conf0: dma_conf0@42080000 { + compatible = "syscon"; + reg = <0x42080000 0x1000>; + status = "okay"; + }; +}; diff --git a/fpga/usrp3/top/e320/dts/e320-common.dtsi b/fpga/usrp3/top/e320/dts/e320-common.dtsi new file mode 100644 index 000000000..470596f33 --- /dev/null +++ b/fpga/usrp3/top/e320/dts/e320-common.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +&fpga_full { + uio@40010000 { + compatible = "usrp-uio"; + reg = <0x40010000 0x2000>; + reg-names = "mboard-regs"; + status = "okay"; + }; + + uio@40014000 { + compatible = "usrp-uio"; + reg = <0x40014000 0x4000>; + reg-names = "dboard-regs"; + status = "okay"; + }; +}; + +&spi0 { + status = "okay"; + + cs-gpios = <0>, <0>, <0>, <&gpio0 62 0>; + + spidev0: spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + status = "okay"; + spi-max-frequency = <1000000>; + }; +}; + +&spi1 { + status = "okay"; + + cs-gpios = <0>, <0>, <0>, <&gpio0 63 0>; + + spidev1: spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + status = "okay"; + spi-max-frequency = <1000000>; + }; +}; diff --git a/fpga/usrp3/top/e320/dts/e320-fpga.dtsi b/fpga/usrp3/top/e320/dts/e320-fpga.dtsi new file mode 100644 index 000000000..3f245d0a2 --- /dev/null +++ b/fpga/usrp3/top/e320/dts/e320-fpga.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +&fpga_full { + firmware-name = "e320.bin"; +}; diff --git a/fpga/usrp3/top/e320/dts/usrp_e320_fpga_1G.dts b/fpga/usrp3/top/e320/dts/usrp_e320_fpga_1G.dts new file mode 100644 index 000000000..c1d76ae4f --- /dev/null +++ b/fpga/usrp3/top/e320/dts/usrp_e320_fpga_1G.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "e320-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + /* 114 = 54 (MIOs) + 60 (EMIO 60) */ + link-gpios = <&gpio0 114 0>; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; // FIXME: Addresses + reg-names = "misc-enet-regs"; + status = "okay"; + }; +}; + +#include "e320-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/e320/dts/usrp_e320_fpga_AA.dts b/fpga/usrp3/top/e320/dts/usrp_e320_fpga_AA.dts new file mode 100644 index 000000000..04f67d002 --- /dev/null +++ b/fpga/usrp3/top/e320/dts/usrp_e320_fpga_AA.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "e320-fpga.dtsi" + +&fpga_full { + uio@40004000 { + compatible = "usrp-uio"; + reg = <0x40004000 0x1000>; //FIXME + reg-names = "misc-auro-regs"; + status = "okay"; + }; +}; + +#include "e320-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/e320/dts/usrp_e320_fpga_XG.dts b/fpga/usrp3/top/e320/dts/usrp_e320_fpga_XG.dts new file mode 100644 index 000000000..3c64cfbf7 --- /dev/null +++ b/fpga/usrp3/top/e320/dts/usrp_e320_fpga_XG.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "e320-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; //FIXME + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; //FIXME + reg-names = "misc-enet-regs"; + status = "okay"; + }; +}; + +#include "e320-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/e320/e320.v b/fpga/usrp3/top/e320/e320.v new file mode 100644 index 000000000..8d766e325 --- /dev/null +++ b/fpga/usrp3/top/e320/e320.v @@ -0,0 +1,1739 @@ +///////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: e320 +// Description: +// E320 Top Level +// +///////////////////////////////////////////////////////////////////// + +`default_nettype none +module e320 ( + + // 5V Power Enable + output wire ENA_PAPWR, + + // GPIO + output wire EN_GPIO_2V5, + output wire EN_GPIO_3V3, + output wire EN_GPIO_VAR_SUPPLY, + inout wire [7:0] GPIO_PREBUFF, + inout wire [7:0] GPIO_DIR, + output wire GPIO_OE_N, + + // GPS + output wire CLK_GPS_PWR_EN, + output wire GPS_INITSURV_N, + output wire GPS_RST_N, + input wire GPS_ALARM, + input wire GPS_LOCK, + input wire GPS_PHASELOCK, + input wire GPS_SURVEY, + input wire GPS_WARMUP, + + // SFP + input wire SFP1_RX_P, + input wire SFP1_RX_N, + output wire SFP1_TX_P, + output wire SFP1_TX_N, + input wire SFP1_RXLOS, + input wire SFP1_TXFAULT, + input wire SFP1_MOD_ABS, // Unused + output wire SFP1_RS0, + output wire SFP1_RS1, + output wire SFP1_TXDISABLE, + + // MGT Clocks + + output wire CLK_PLL_SCLK, + output wire CLK_PLL_SDATA, + output wire CLK_PLL_SLE, + + input wire CLK_MGT_125M_P, + input wire CLK_MGT_125M_N, + input wire CLK_MGT_156_25M_P, + input wire CLK_MGT_156_25M_N, + + // PS Connections + inout wire [53:0] PS_MIO, + inout wire PS_CLK, + inout wire PS_SRST_B, + inout wire PS_POR_B, + inout wire DDR_MODCLK_P, + inout wire DDR_MODCLK_N, + inout wire PS_DDR3_CKE, + inout wire PS_DDR3_RESET_N, + inout wire [31:0] PS_DDR3_DQ, + inout wire [14:0] PS_DDR3_ADDR, + inout wire [3:0] PS_DDR3_DM, + inout wire [2:0] PS_DDR3_BA, + inout wire [3:0] PS_DDR3_DQS_P, + inout wire [3:0] PS_DDR3_DQS_N, + inout wire PS_DDR3_ODT, + inout wire PS_DDR3_VRN, + inout wire PS_DDR3_VRP, + inout wire PS_DDR3_WE_N, + inout wire PS_DDR3_CS_N, + inout wire PS_DDR3_CAS_N, + inout wire PS_DDR3_RAS_N, + + // PL DRAM Interface + input wire sys_clk_p, + input wire sys_clk_n, + // + inout wire [31:0] ddr3_dq, + inout wire [3:0] ddr3_dqs_n, + inout wire [3:0] ddr3_dqs_p, + output wire [3:0] ddr3_dm, + // + output wire [2:0] ddr3_ba, + output wire [15:0] ddr3_addr, + output wire ddr3_ras_n, + output wire ddr3_cas_n, + output wire ddr3_we_n, + // + output wire [0:0] ddr3_cs_n, + output wire [0:0] ddr3_cke, + output wire [0:0] ddr3_odt, + // + output wire [0:0] ddr3_ck_p, + output wire [0:0] ddr3_ck_n, + // + output wire ddr3_reset_n, + + // LEDs + output wire LED_LINK1, + output wire LED_ACT1, + + // PPS, REFCLK + input wire CLK_SYNC_INT, // PPS from GPS + input wire CLK_SYNC_INT_RAW, // PPS_RAW from GPS (Unused) + input wire CLK_SYNC_EXT, // PPS from external connector + input wire CLK_REF_RAW, // FPGA reference clock (GPS or external) + output wire CLK_REF_SEL, // Select for GPS or external reference clock + input wire CLK_MUX_OUT, // RF clock locked status + + // RF LVDS Data Interface + // + // Receive + input wire RX_CLK_P, + input wire RX_CLK_N, + input wire RX_FRAME_P, + input wire RX_FRAME_N, + input wire [5:0] RX_DATA_P, + input wire [5:0] RX_DATA_N, + // + // TraNSMIT + output wire TX_CLK_P, + output wire TX_CLK_N, + output wire TX_FRAME_P, + output wire TX_FRAME_N, + output wire [5:0] TX_DATA_P, + output wire [5:0] TX_DATA_N, + + // Switches + output wire [2:0] FE1_SEL, + output wire [2:0] FE2_SEL, + output wire [1:0] RX1_SEL, + output wire [1:0] RX2_SEL, + output wire [5:0] RX1_BSEL, + output wire [5:0] RX2_BSEL, + output wire [5:0] TX1_BSEL, + output wire [5:0] TX2_BSEL, + + // SPI + input wire XCVR_SPI_MISO, + output wire XCVR_SPI_MOSI, + output wire XCVR_SPI_CLK, + output wire XCVR_SPI_CS_N, + + // AD9361 + output wire XCVR_ENABLE, + output wire XCVR_SYNC, + output wire XCVR_TXNRX, + output wire XCVR_ENA_AGC, + output wire XCVR_RESET_N, + input wire [7:0] XCVR_CTRL_OUT, + + // Amplifiers + output wire TX_HFAMP1_ENA, + output wire TX_HFAMP2_ENA, + output wire TX_LFAMP1_ENA, + output wire TX_LFAMP2_ENA, + + // LEDs + output wire RX1_GRN_ENA, + output wire RX2_GRN_ENA, + output wire TX1_RED_ENA, + output wire TX2_RED_ENA, + output wire TXRX1_GRN_ENA, + output wire TXRX2_GRN_ENA + +); + + `ifdef SFP_1GBE + parameter PROTOCOL = "1GbE"; + parameter MDIO_EN = 1'b1; + parameter MDIO_PHYADDR = 5'd4; + `elsif SFP_10GBE + parameter PROTOCOL = "10GbE"; + parameter MDIO_EN = 1'b1; + parameter MDIO_PHYADDR = 5'd4; + `elsif SFP_AURORA + parameter PROTOCOL = "Aurora"; + parameter MDIO_EN = 1'b0; + parameter MDIO_PHYADDR = 5'd0; + `else + parameter PROTOCOL = "Disabled"; + parameter MDIO_EN = 1'b0; + parameter MDIO_PHYADDR = 5'd0; + `endif + + // Constants + localparam REG_AWIDTH = 14; // log2(0x4000) + localparam REG_DWIDTH = 32; + localparam DB_GPIO_WIDTH = 32; + localparam FP_GPIO_OFFSET = 32; // Offset within ps_gpio_* + localparam FP_GPIO_WIDTH = 8; + + //If bus_clk freq ever changes, update this parameter accordingly. + localparam BUS_CLK_RATE = 32'd200000000; //200 MHz bus_clk rate. + localparam SFP_PORTNUM = 8'b0; // Only one SFP port + localparam NUM_RADIOS = 1; + localparam NUM_CHANNELS_PER_RADIO = 2; + localparam NUM_DBOARDS = 1; + localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO; + localparam [15:0] RFNOC_PROTOVER = {8'd1, 8'd0}; + + // Clocks + wire xgige_clk156; + wire bus_clk; + wire radio_clk; + wire reg_clk; + wire clk40; + wire ddr3_dma_clk; + wire FCLK_CLK0; + wire FCLK_CLK1; + wire FCLK_CLK2; + wire FCLK_CLK3; + + // Resets + wire global_rst; + wire bus_rst; + wire radio_rst; + wire reg_rstn; + wire clk40_rst; + wire clk40_rstn; + wire FCLK_RESET0_N; + + // Regport for SFP + wire m_axi_net_arvalid; + wire m_axi_net_awvalid; + wire m_axi_net_bready; + wire m_axi_net_rready; + wire m_axi_net_wvalid; + wire [11:0] m_axi_net_arid; + wire [11:0] m_axi_net_awid; + wire [11:0] m_axi_net_wid; + wire [31:0] m_axi_net_araddr; + wire [31:0] m_axi_net_awaddr; + wire [31:0] m_axi_net_wdata; + wire [3:0] m_axi_net_wstrb; + wire m_axi_net_arready; + wire m_axi_net_awready; + wire m_axi_net_bvalid; + wire m_axi_net_rlast; + wire m_axi_net_rvalid; + wire m_axi_net_wready; + wire [1:0] m_axi_net_bresp; + wire [1:0] m_axi_net_rresp; + wire [31:0] m_axi_net_rdata; + + // Crossbar + wire m_axi_xbar_arvalid; + wire m_axi_xbar_awvalid; + wire m_axi_xbar_bready; + wire m_axi_xbar_rready; + wire m_axi_xbar_wvalid; + wire [11:0] m_axi_xbar_arid; + wire [11:0] m_axi_xbar_awid; + wire [11:0] m_axi_xbar_wid; + wire [31:0] m_axi_xbar_araddr; + wire [31:0] m_axi_xbar_awaddr; + wire [31:0] m_axi_xbar_wdata; + wire [3:0] m_axi_xbar_wstrb; + wire m_axi_xbar_arready; + wire m_axi_xbar_awready; + wire m_axi_xbar_bvalid; + wire m_axi_xbar_rlast; + wire m_axi_xbar_rvalid; + wire m_axi_xbar_wready; + wire [1:0] m_axi_xbar_bresp; + wire [1:0] m_axi_xbar_rresp; + wire [31:0] m_axi_xbar_rdata; + + // ETH DMA + wire m_axi_eth_dma_arvalid; + wire m_axi_eth_dma_awvalid; + wire m_axi_eth_dma_bready; + wire m_axi_eth_dma_rready; + wire m_axi_eth_dma_wvalid; + wire [11:0] m_axi_eth_dma_arid; + wire [11:0] m_axi_eth_dma_awid; + wire [11:0] m_axi_eth_dma_wid; + wire [31:0] m_axi_eth_dma_araddr; + wire [31:0] m_axi_eth_dma_awaddr; + wire [31:0] m_axi_eth_dma_wdata; + wire [3:0] m_axi_eth_dma_wstrb; + wire m_axi_eth_dma_arready; + wire m_axi_eth_dma_awready; + wire m_axi_eth_dma_bvalid; + wire m_axi_eth_dma_rlast; + wire m_axi_eth_dma_rvalid; + wire m_axi_eth_dma_wready; + wire [1:0] m_axi_eth_dma_bresp; + wire [1:0] m_axi_eth_dma_rresp; + wire [31:0] m_axi_eth_dma_rdata; + + // Processing System + wire [15:0] IRQ_F2P; + + // DMA xport adapter to PS + wire [63:0] m_axis_dma_tdata; + wire [3:0] m_axis_dma_tuser; + wire m_axis_dma_tlast; + wire m_axis_dma_tready; + wire m_axis_dma_tvalid; + + wire [63:0] s_axis_dma_tdata; + wire [3:0] s_axis_dma_tdest; + wire s_axis_dma_tlast; + wire s_axis_dma_tready; + wire s_axis_dma_tvalid; + + // HP0 -- High Performance port 0 + wire [5:0] s_axi_hp0_awid; + wire [31:0] s_axi_hp0_awaddr; + wire [2:0] s_axi_hp0_awprot; + wire s_axi_hp0_awvalid; + wire s_axi_hp0_awready; + wire [63:0] s_axi_hp0_wdata; + wire [7:0] s_axi_hp0_wstrb; + wire s_axi_hp0_wvalid; + wire s_axi_hp0_wready; + wire [1:0] s_axi_hp0_bresp; + wire s_axi_hp0_bvalid; + wire s_axi_hp0_bready; + wire [5:0] s_axi_hp0_arid; + wire [31:0] s_axi_hp0_araddr; + wire [2:0] s_axi_hp0_arprot; + wire s_axi_hp0_arvalid; + wire s_axi_hp0_arready; + wire [63:0] s_axi_hp0_rdata; + wire [1:0] s_axi_hp0_rresp; + wire s_axi_hp0_rvalid; + wire s_axi_hp0_rready; + wire s_axi_hp0_rlast; + wire [3:0] s_axi_hp0_arcache; + wire [7:0] s_axi_hp0_awlen; + wire [2:0] s_axi_hp0_awsize; + wire [1:0] s_axi_hp0_awburst; + wire [3:0] s_axi_hp0_awcache; + wire s_axi_hp0_wlast; + wire [7:0] s_axi_hp0_arlen; + wire [1:0] s_axi_hp0_arburst; + wire [2:0] s_axi_hp0_arsize; + + wire [4:0] s_axi_eth_descriptor_awid; + wire [31:0] s_axi_eth_descriptor_awaddr; + wire [2:0] s_axi_eth_descriptor_awprot; + wire s_axi_eth_descriptor_awvalid; + wire s_axi_eth_descriptor_awready; + wire [31:0] s_axi_eth_descriptor_wdata; + wire [3:0] s_axi_eth_descriptor_wstrb; + wire s_axi_eth_descriptor_wvalid; + wire s_axi_eth_descriptor_wready; + wire [1:0] s_axi_eth_descriptor_bresp; + wire s_axi_eth_descriptor_bvalid; + wire s_axi_eth_descriptor_bready; + wire [4:0] s_axi_eth_descriptor_arid; + wire [31:0] s_axi_eth_descriptor_araddr; + wire [2:0] s_axi_eth_descriptor_arprot; + wire s_axi_eth_descriptor_arvalid; + wire s_axi_eth_descriptor_arready; + wire [31:0] s_axi_eth_descriptor_rdata; + wire [1:0] s_axi_eth_descriptor_rresp; + wire s_axi_eth_descriptor_rvalid; + wire s_axi_eth_descriptor_rready; + wire s_axi_eth_descriptor_rlast; + wire [3:0] s_axi_eth_descriptor_arcache; + wire [7:0] s_axi_eth_descriptor_awlen; + wire [2:0] s_axi_eth_descriptor_awsize; + wire [1:0] s_axi_eth_descriptor_awburst; + wire [3:0] s_axi_eth_descriptor_awcache; + wire s_axi_eth_descriptor_wlast; + wire [7:0] s_axi_eth_descriptor_arlen; + wire [1:0] s_axi_eth_descriptor_arburst; + wire [2:0] s_axi_eth_descriptor_arsize; + + // ARM ethernet dma clock crossing + wire [63:0] arm_eth_tx_tdata; + wire arm_eth_tx_tvalid; + wire arm_eth_tx_tlast; + wire arm_eth_tx_tready; + wire [3:0] arm_eth_tx_tuser; + wire [7:0] arm_eth_tx_tkeep; + + wire [63:0] arm_eth_tx_tdata_b; + wire arm_eth_tx_tvalid_b; + wire arm_eth_tx_tlast_b; + wire arm_eth_tx_tready_b; + wire [3:0] arm_eth_tx_tuser_b; + wire [7:0] arm_eth_tx_tkeep_b; + + wire [63:0] arm_eth_rx_tdata; + wire arm_eth_rx_tvalid; + wire arm_eth_rx_tlast; + wire arm_eth_rx_tready; + wire [3:0] arm_eth_rx_tuser; + wire [7:0] arm_eth_rx_tkeep; + + wire [63:0] arm_eth_rx_tdata_b; + wire arm_eth_rx_tvalid_b; + wire arm_eth_rx_tlast_b; + wire arm_eth_rx_tready_b; + wire [3:0] arm_eth_rx_tuser_b; + wire [7:0] arm_eth_rx_tkeep_b; + + wire arm_eth_rx_irq; + wire arm_eth_tx_irq; + + // Vita to Ethernet + wire [63:0] v2e_tdata; + wire v2e_tlast; + wire v2e_tvalid; + wire v2e_tready; + + // Ethernet to Vita + wire [63:0] e2v_tdata; + wire e2v_tlast; + wire e2v_tvalid; + wire e2v_tready; + + // Misc + wire [31:0] sfp_port_info; + wire sfp_link_up; + wire [15:0] device_id; + wire clocks_locked; + + ///////////////////////////////////////////////////////////////////// + // + // Resets: + // - PL - Global Reset --> Bus Reset + // --> Radio Reset + // - PS - FCLK_RESET0_N --> clk40_rst(n) + // + ////////////////////////////////////////////////////////////////////// + + // Global synchronous reset, on the bus_clk domain. De-asserts after 85 + // bus_clk cycles. Asserted by default. + por_gen por_gen ( + .clk(bus_clk), + .reset_out(global_rst) + ); + + // Synchronous reset for the radio_clk domain + reset_sync radio_reset_gen ( + .clk(radio_clk), + .reset_in(~clocks_locked), + .reset_out(radio_rst) + ); + + // Synchronous reset for the bus_clk domain + reset_sync bus_reset_gen ( + .clk(bus_clk), + .reset_in(~clocks_locked), + .reset_out(bus_rst) + ); + + + // PS-based Resets // + // + // Synchronous reset for the clk40 domain. This is derived from the PS reset 0. + reset_sync clk40_reset_gen ( + .clk(clk40), + .reset_in(~FCLK_RESET0_N), + .reset_out(clk40_rst) + ); + // Invert for various modules. + assign clk40_rstn = ~clk40_rst; + assign reg_rstn = clk40_rstn; + + ///////////////////////////////////////////////////////////////////// + // + // Clocks and PPS + // + ///////////////////////////////////////////////////////////////////// + + wire pps_refclk; + wire [1:0] pps_select; + wire ref_select; + wire refclk_locked_busclk; + + assign clk40 = FCLK_CLK1; // 40 MHz + assign bus_clk = FCLK_CLK3; // 200 MHz + assign reg_clk = clk40; + + e320_clocking e320_clocking_i ( + .global_rst(global_rst), + .ref_clk_from_pin(CLK_REF_RAW), + .ref_clk(), + .clk156(xgige_clk156), + .ddr3_dma_clk(ddr3_dma_clk), + .clocks_locked(clocks_locked), + .ext_pps_from_pin(CLK_SYNC_EXT), + .gps_pps_from_pin(CLK_SYNC_INT), + .pps_select(pps_select), + .pps_refclk(pps_refclk) + ); + + assign CLK_REF_SEL = ref_select; + + synchronizer synchronize_rf_clk_lock ( + .clk(bus_clk), .rst(1'b0), .in(CLK_MUX_OUT), .out(refclk_locked_busclk) + ); + + ///////////////////////////////////////////////////////////////////// + // + // PL DDR3 Memory Interface + // + ///////////////////////////////////////////////////////////////////// + + wire ddr3_axi_clk; // 1/4 DDR external clock rate + wire ddr3_axi_rst; // Synchronized to ddr_sys_clk + wire ddr3_running; // DRAM calibration complete. + wire [11:0] device_temp; + + // Slave Interface Write Address Ports + wire [3:0] ddr3_axi_awid; + wire [31:0] ddr3_axi_awaddr; + wire [7:0] ddr3_axi_awlen; + wire [2:0] ddr3_axi_awsize; + wire [1:0] ddr3_axi_awburst; + wire [0:0] ddr3_axi_awlock; + wire [3:0] ddr3_axi_awcache; + wire [2:0] ddr3_axi_awprot; + wire [3:0] ddr3_axi_awqos; + wire ddr3_axi_awvalid; + wire ddr3_axi_awready; + // Slave Interface Write Data Ports + wire [255:0] ddr3_axi_wdata; + wire [31:0] ddr3_axi_wstrb; + wire ddr3_axi_wlast; + wire ddr3_axi_wvalid; + wire ddr3_axi_wready; + // Slave Interface Write Response Ports + wire ddr3_axi_bready; + wire [3:0] ddr3_axi_bid; + wire [1:0] ddr3_axi_bresp; + wire ddr3_axi_bvalid; + // Slave Interface Read Address Ports + wire [3:0] ddr3_axi_arid; + wire [31:0] ddr3_axi_araddr; + wire [7:0] ddr3_axi_arlen; + wire [2:0] ddr3_axi_arsize; + wire [1:0] ddr3_axi_arburst; + wire [0:0] ddr3_axi_arlock; + wire [3:0] ddr3_axi_arcache; + wire [2:0] ddr3_axi_arprot; + wire [3:0] ddr3_axi_arqos; + wire ddr3_axi_arvalid; + wire ddr3_axi_arready; + // Slave Interface Read Data Ports + wire ddr3_axi_rready; + wire [3:0] ddr3_axi_rid; + wire [255:0] ddr3_axi_rdata; + wire [1:0] ddr3_axi_rresp; + wire ddr3_axi_rlast; + wire ddr3_axi_rvalid; + + reg ddr3_axi_rst_reg_n; + + // Copied this reset circuit from example design. + always @(posedge ddr3_axi_clk) + ddr3_axi_rst_reg_n <= ~ddr3_axi_rst; + + ddr3_32bit u_ddr3_32bit ( + // Memory interface ports + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .init_calib_complete (ddr3_running), + .device_temp_i (device_temp), + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_odt (ddr3_odt), + // Application interface ports + .ui_clk (ddr3_axi_clk), + .ui_clk_sync_rst (ddr3_axi_rst), + .aresetn (ddr3_axi_rst_reg_n), + .app_sr_req (1'b0), + .app_sr_active (), + .app_ref_req (1'b0), + .app_ref_ack (), + .app_zq_req (1'b0), + .app_zq_ack (), + // Slave Interface Write Address Ports + .s_axi_awid (ddr3_axi_awid), + .s_axi_awaddr (ddr3_axi_awaddr[30:0]), + .s_axi_awlen (ddr3_axi_awlen), + .s_axi_awsize (ddr3_axi_awsize), + .s_axi_awburst (ddr3_axi_awburst), + .s_axi_awlock (ddr3_axi_awlock), + .s_axi_awcache (ddr3_axi_awcache), + .s_axi_awprot (ddr3_axi_awprot), + .s_axi_awqos (ddr3_axi_awqos), + .s_axi_awvalid (ddr3_axi_awvalid), + .s_axi_awready (ddr3_axi_awready), + // Slave Interface Write Data Ports + .s_axi_wdata (ddr3_axi_wdata), + .s_axi_wstrb (ddr3_axi_wstrb), + .s_axi_wlast (ddr3_axi_wlast), + .s_axi_wvalid (ddr3_axi_wvalid), + .s_axi_wready (ddr3_axi_wready), + // Slave Interface Write Response Ports + .s_axi_bid (ddr3_axi_bid), + .s_axi_bresp (ddr3_axi_bresp), + .s_axi_bvalid (ddr3_axi_bvalid), + .s_axi_bready (ddr3_axi_bready), + // Slave Interface Read Address Ports + .s_axi_arid (ddr3_axi_arid), + .s_axi_araddr (ddr3_axi_araddr[30:0]), + .s_axi_arlen (ddr3_axi_arlen), + .s_axi_arsize (ddr3_axi_arsize), + .s_axi_arburst (ddr3_axi_arburst), + .s_axi_arlock (ddr3_axi_arlock), + .s_axi_arcache (ddr3_axi_arcache), + .s_axi_arprot (ddr3_axi_arprot), + .s_axi_arqos (ddr3_axi_arqos), + .s_axi_arvalid (ddr3_axi_arvalid), + .s_axi_arready (ddr3_axi_arready), + // Slave Interface Read Data Ports + .s_axi_rid (ddr3_axi_rid), + .s_axi_rdata (ddr3_axi_rdata), + .s_axi_rresp (ddr3_axi_rresp), + .s_axi_rlast (ddr3_axi_rlast), + .s_axi_rvalid (ddr3_axi_rvalid), + .s_axi_rready (ddr3_axi_rready), + // System Clock Ports + .sys_clk_p (sys_clk_p), + .sys_clk_n (sys_clk_n), + .clk_ref_i (bus_clk), + .sys_rst (bus_rst) + ); + + // Temperature monitor module + mig_7series_v4_2_tempmon #( + .TEMP_MON_CONTROL ("INTERNAL"), + .XADC_CLK_PERIOD (5000) // In ps, should match xadc_clk period + ) tempmon_i ( + .clk (bus_clk), + .xadc_clk (bus_clk), + .rst (bus_rst), + .device_temp_i (12'd0), // Not used for "INTERNAL" + .device_temp (device_temp) + ); + + + ///////////////////////////////////////////////////////////////////// + // + // Front-Panel GPIO + // + ///////////////////////////////////////////////////////////////////// + + wire [31:0] fp_gpio_ctrl; + wire [FP_GPIO_WIDTH-1:0] fp_gpio_in; + wire [FP_GPIO_WIDTH-1:0] fp_gpio_out; + wire [FP_GPIO_WIDTH-1:0] fp_gpio_tri; + + // Turn on GPIO buffers + assign GPIO_OE_N = fp_gpio_ctrl[0]; + + // Enable GPIO supply + assign EN_GPIO_VAR_SUPPLY = fp_gpio_ctrl[1]; + + // GPIO Voltage (1.8V, 2.5V, or 3.3V) + // + // 3V3 2V5 | Voltage + // ----------------- + // 0 0 | 1.8 V + // 0 1 | 2.5 V + // 1 0 | 3.3 V + assign EN_GPIO_2V5 = fp_gpio_ctrl[2]; + assign EN_GPIO_3V3 = fp_gpio_ctrl[3]; + + genvar i; + generate + for (i = 0; i < FP_GPIO_WIDTH; i = i+1) begin : gen_gpio_iobuf + assign fp_gpio_in[i] = GPIO_PREBUFF[i]; + assign GPIO_PREBUFF[i] = fp_gpio_tri[i] ? 1'bZ : fp_gpio_out[i]; + assign GPIO_DIR[i] = ~fp_gpio_tri[i]; + end + endgenerate + + + ///////////////////////////////////////////////////////////////////// + // + // GPIO Interface + // - Control Filter Banks + // - LEDs + // + ///////////////////////////////////////////////////////////////////// + + // Flattened Radio GPIO control + wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_out_flat; + wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_ddr_flat; + wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_in_flat; + wire [32*NUM_CHANNELS-1:0] leds_flat; + + // Radio GPIO control + wire [DB_GPIO_WIDTH-1:0] db_gpio_in[0:NUM_CHANNELS-1]; + wire [DB_GPIO_WIDTH-1:0] db_gpio_out[0:NUM_CHANNELS-1]; + wire [DB_GPIO_WIDTH-1:0] db_gpio_ddr[0:NUM_CHANNELS-1]; + wire [DB_GPIO_WIDTH-1:0] db_gpio_pins[0:NUM_CHANNELS-1]; + wire [31:0] leds[0:NUM_CHANNELS-1]; + + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + + assign db_gpio_in_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH] = db_gpio_in[i]; + assign db_gpio_out[i] = db_gpio_out_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH]; + assign db_gpio_ddr[i] = db_gpio_ddr_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH]; + assign leds[i] = leds_flat[32*i +: 32]; + + gpio_atr_io #( + .WIDTH(DB_GPIO_WIDTH) + ) gpio_atr_db_inst ( + .clk(radio_clk), + .gpio_pins(db_gpio_pins[i]), + .gpio_ddr(db_gpio_ddr[i]), + .gpio_out(db_gpio_out[i]), + .gpio_in(db_gpio_in[i]) + ); + end + endgenerate + + // DB_GPIO and LED pin assignments with software mapping + + // Channel 1 + assign {TX_HFAMP1_ENA, // HF TX AMP + TX_LFAMP1_ENA, // LF TX AMP + FE1_SEL[2:0], // TRX Switch + TX1_BSEL[5:3], // TX_SW2 + TX1_BSEL[2:0], // TX_SW1 + RX1_SEL[1:0], // RX_SW3 + RX1_BSEL[5:3], // RX_SW2 + RX1_BSEL[2:0] // RX_SW1 + } = db_gpio_pins[0]; + + assign {RX1_GRN_ENA, //TX/RX led + TX1_RED_ENA, //TX/RX led + TXRX1_GRN_ENA //RX2 led + } = leds[0]; + + // Channel 2 + assign {TX_HFAMP2_ENA, // HF TX AMP + TX_LFAMP2_ENA, // LF TX AMP + FE2_SEL[2:0], // TRX Switch + TX2_BSEL[5:3], // TX_SW2 + TX2_BSEL[2:0], // TX_SW1 + RX2_SEL[1:0], // RX_SW3 + RX2_BSEL[5:3], // RX_SW2 + RX2_BSEL[2:0] // RX_SW1 + } = db_gpio_pins[1]; + + assign {RX2_GRN_ENA, + TX2_RED_ENA, + TXRX2_GRN_ENA + } = leds[1]; + + ///////////////////////////////////////////////////////////////////// + // + // 5V Power Supply (TX Amplifier) + // + ///////////////////////////////////////////////////////////////////// + + assign ENA_PAPWR = 1'b1; + + ///////////////////////////////////////////////////////////////////// + // + // AD9361 Interface + // + ///////////////////////////////////////////////////////////////////// + + wire [NUM_CHANNELS*32-1:0] rx_flat, tx_flat; + + wire [11:0] rx_i0, rx_q0, tx_i0, tx_q0; + wire [11:0] rx_i1, rx_q1, tx_i1, tx_q1; + + wire [NUM_CHANNELS-1:0] rx_stb, tx_stb; + wire [NUM_CHANNELS-1:0] rx_atr, tx_atr; + + wire [REG_DWIDTH-1:0] dboard_ctrl; + wire [REG_DWIDTH-1:0] dboard_status; + wire mimo_busclk, mimo_radioclk; + wire tx_chan_sel_busclk, tx_chan_sel_radioclk; + wire rx_aligned; + + wire tx_pll_lock_busclk, rx_pll_lock_busclk; + + synchronizer synchronizer_tx_pll_lock ( + .clk(bus_clk), .rst(1'b0), .in(XCVR_CTRL_OUT[7]), .out(tx_pll_lock_busclk) + ); + + synchronizer synchronizer_rx_pll_lock ( + .clk(bus_clk), .rst(1'b0), .in(XCVR_CTRL_OUT[6]), .out(rx_pll_lock_busclk) + ); + + assign dboard_status = { + 24'b0, + tx_pll_lock_busclk, // TX PLL Lock + rx_pll_lock_busclk, // RX PLL Lock + 6'b0 + }; + + assign mimo_busclk = dboard_ctrl[0]; + assign tx_chan_sel_busclk = dboard_ctrl[1]; + + synchronizer synchronizer_mimo_radioclk ( + .clk(radio_clk), .rst(1'b0), .in(mimo_busclk), .out(mimo_radioclk) + ); + + synchronizer synchronizer_tx_chan_sel_radioclk ( + .clk(radio_clk), .rst(1'b0), .in(tx_chan_sel_busclk), .out(tx_chan_sel_radioclk) + ); + + assign rx_flat = {rx_i1, 4'b0, rx_q1, 4'b0, + rx_i0, 4'b0, rx_q0, 4'b0}; + + assign tx_q0 = tx_flat[15:4]; + assign tx_i0 = tx_flat[31:20]; + assign tx_q1 = tx_flat[47:36]; + assign tx_i1 = tx_flat[63:52]; + + // Tx and Rx have samples on every clock, so keep stb asserted + assign rx_stb = { 1'b1, 1'b1 }; + assign tx_stb = { 1'b1, 1'b1 }; + + // These delays depend on the internal clock routing delays of the FPGA. + // Valid timing constraints are required to confirm that setup/hold are met + // at both the input and output interfaces. + localparam INPUT_DATA_DELAY = 27; + localparam OUTPUT_DATA_DELAY = 19; + + assign XCVR_ENABLE = 1'b1; + assign XCVR_SYNC = 1'b0; + assign XCVR_TXNRX = 1'b1; + assign XCVR_ENA_AGC = 1'b1; + assign XCVR_RESET_N = ~bus_rst; + + cat_io_lvds_dual_mode #( + .INVERT_FRAME_RX (0), + .INVERT_DATA_RX (6'b00_0000), + .INVERT_FRAME_TX (0), + .INVERT_DATA_TX (6'b00_0000), + .USE_CLOCK_IDELAY (0), + .USE_DATA_IDELAY (1), + .DATA_IDELAY_MODE ("FIXED"), + .CLOCK_IDELAY_MODE ("FIXED"), + .INPUT_CLOCK_DELAY (0), + .INPUT_DATA_DELAY (INPUT_DATA_DELAY), + .USE_CLOCK_ODELAY (1), + .USE_DATA_ODELAY (1), + .DATA_ODELAY_MODE ("FIXED"), + .CLOCK_ODELAY_MODE ("FIXED"), + .OUTPUT_CLOCK_DELAY (0), + .OUTPUT_DATA_DELAY (OUTPUT_DATA_DELAY) + ) cat_io_lvds_dual_mode_i0 ( + .rst (radio_rst), + .clk200 (bus_clk), // 200 MHz clock + + // Data and frame timing + .a_mimo (mimo_busclk), + .a_tx_ch (tx_chan_sel_busclk), + + // Delay control interface (not used) + .ctrl_clk (bus_clk), + // + .ctrl_in_data_delay (5'b00000), + .ctrl_in_clk_delay (5'b00000), + .ctrl_ld_in_data_delay (1'b0), + .ctrl_ld_in_clk_delay (1'b0), + // + .ctrl_out_data_delay (5'b00000), + .ctrl_out_clk_delay (5'b00000), + .ctrl_ld_out_data_delay (1'b0), + .ctrl_ld_out_clk_delay (1'b0), + + // Sample interface + .radio_clk (radio_clk), + .rx_aligned (rx_aligned), + // + .rx_i0 (rx_i0), + .rx_q0 (rx_q0), + .rx_i1 (rx_i1), + .rx_q1 (rx_q1), + // + .tx_i0 (tx_i0), + .tx_q0 (tx_q0), + .tx_i1 (tx_i1), + .tx_q1 (tx_q1), + + // AD9361 interface + .rx_clk_p (RX_CLK_P), + .rx_clk_n (RX_CLK_N), + .rx_frame_p (RX_FRAME_P), + .rx_frame_n (RX_FRAME_N), + .rx_d_p (RX_DATA_P), + .rx_d_n (RX_DATA_N), + // + .tx_clk_p (TX_CLK_P), + .tx_clk_n (TX_CLK_N), + .tx_frame_p (TX_FRAME_P), + .tx_frame_n (TX_FRAME_N), + .tx_d_p (TX_DATA_P), + .tx_d_n (TX_DATA_N) + ); + + ///////////////////////////////////////////////////////////////////// + // + // SFP Connections: + // - 1G + // - 10G + // - Aurora + // + ////////////////////////////////////////////////////////////////////// + + //-------------------------------------------------------------- + // SFP Reference Clocks: + // 1G requires 125 MHz reference clock + //-------------------------------------------------------------- + + wire gige_refclk; + wire gige_refclk_bufg; + + // dont_touch required for good SI on clock + (* dont_touch = "true" *) IBUFDS_GTE2 gige_refclk_ibuf ( + .ODIV2(), + .CEB (1'b0), + .I (CLK_MGT_125M_P), + .IB(CLK_MGT_125M_N), + .O (gige_refclk) + ); + + BUFG bufg_gige_refclk_i ( + .I(gige_refclk), + .O(gige_refclk_bufg) + ); + + //-------------------------------------------------------------- + // SFP Reference Clocks: + // XG requires 156.25 MHz reference clock + //-------------------------------------------------------------- + + wire xgige_refclk; + wire xgige_dclk; + + // dont_touch required for good SI on clock + (* dont_touch = "true" *) IBUFDS_GTE2 ten_gige_refclk_ibuf ( + .ODIV2(), + .CEB (1'b0), + .I (CLK_MGT_156_25M_P), + .IB(CLK_MGT_156_25M_N), + .O (xgige_refclk) + ); + + ten_gige_phy_clk_gen xgige_clk_gen_i ( + .refclk_ibuf(xgige_refclk), + .clk156(xgige_clk156), + .dclk(xgige_dclk) + ); + + //-------------------------------------------------------------- + // SFP Reference Clocks: + // XG requires 156.25 MHz reference clock + //-------------------------------------------------------------- + + wire aurora_refclk; + wire aurora_clk156; + wire aurora_init_clk; + + // Use the 156.25MHz reference clock for Aurora + assign aurora_refclk = xgige_refclk; + assign aurora_clk156 = xgige_clk156; + assign aurora_init_clk = xgige_dclk; + + wire sfp_gt_refclk; + wire sfp_gb_refclk; + wire sfp_misc_clk; + + // Make SFP1_RS1 open drain to avoid a short circuit when it is connected to + // ground by the SFP module (per the SFP+ specification). + wire SFP1_RS1_t; + assign SFP1_RS1 = SFP1_RS1_t ? 1'bZ : 1'b0; + + // Select Reference Clock according to Protocol + generate + if (PROTOCOL == "10GbE") begin + + assign sfp_gt_refclk = xgige_refclk; + assign sfp_gb_refclk = xgige_clk156; + assign sfp_misc_clk = xgige_dclk; + assign SFP1_RS0 = 1'b1; + assign SFP1_RS1_t = 1'b1; + + end else if (PROTOCOL == "1GbE") begin + + assign sfp_gt_refclk = gige_refclk; + assign sfp_gb_refclk = gige_refclk_bufg; + assign sfp_misc_clk = gige_refclk_bufg; + assign SFP1_RS0 = 1'b0; + assign SFP1_RS1_t = 1'b0; + + end else if (PROTOCOL == "Aurora") begin + + assign sfp_gt_refclk = aurora_refclk; + assign sfp_gb_refclk = aurora_clk156; + assign sfp_misc_clk = aurora_init_clk; + assign SFP1_RS0 = 1'b1; + assign SFP1_RS1_t = 1'b1; + + end else begin + + assign sfp_gt_refclk = 1'b0; + assign sfp_gb_refclk = 1'b0; + assign sfp_misc_clk = 1'b0; + assign SFP1_RS0 = 1'b0; + assign SFP1_RS1_t = 1'b0; + + end + endgenerate + + ///////////////////////////////////////////////////////////////////// + // + // SFP Wrapper: All protocols (1G/XG/AA) + eth_switch + // + ///////////////////////////////////////////////////////////////////// + + n3xx_sfp_wrapper #( + .PROTOCOL(PROTOCOL), + .MDIO_EN(MDIO_EN), + .MDIO_PHYADDR(MDIO_PHYADDR), + .DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .AWIDTH(REG_AWIDTH), // Width of the address bus + .PORTNUM(SFP_PORTNUM) + ) sfp_wrapper_i ( + .areset(bus_rst), + .gt_refclk(sfp_gt_refclk), + .gb_refclk(sfp_gb_refclk), + .misc_clk(sfp_misc_clk), + + .bus_rst(bus_rst), + .bus_clk(bus_clk), + .user_clk(), + .sync_clk(), + + // GT_COMMON + .qpllreset(), + .qplllock(1'b0), + .qplloutclk(1'b0), + .qplloutrefclk(1'b0), + .qpllrefclklost(), + + .mmcm_locked(1'b0), + .gt_pll_lock(), + + .txp(SFP1_TX_P), + .txn(SFP1_TX_N), + .rxp(SFP1_RX_P), + .rxn(SFP1_RX_N), + + .sfpp_rxlos(SFP1_RXLOS), + .sfpp_tx_fault(SFP1_TXFAULT), + .sfpp_tx_disable(SFP1_TXDISABLE), + + // Clock and reset + .s_axi_aclk(reg_clk), + .s_axi_aresetn(reg_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(m_axi_net_awaddr[REG_AWIDTH-1:0]), + .s_axi_awvalid(m_axi_net_awvalid), + .s_axi_awready(m_axi_net_awready), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(m_axi_net_wdata), + .s_axi_wstrb(m_axi_net_wstrb), + .s_axi_wvalid(m_axi_net_wvalid), + .s_axi_wready(m_axi_net_wready), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(m_axi_net_bresp), + .s_axi_bvalid(m_axi_net_bvalid), + .s_axi_bready(m_axi_net_bready), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(m_axi_net_araddr[REG_AWIDTH-1:0]), + .s_axi_arvalid(m_axi_net_arvalid), + .s_axi_arready(m_axi_net_arready), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(m_axi_net_rdata), + .s_axi_rresp(m_axi_net_rresp), + .s_axi_rvalid(m_axi_net_rvalid), + .s_axi_rready(m_axi_net_rready), + + // Ethernet to Vita + .e2v_tdata(e2v_tdata), + .e2v_tlast(e2v_tlast), + .e2v_tvalid(e2v_tvalid), + .e2v_tready(e2v_tready), + + // Vita to Ethernet + .v2e_tdata(v2e_tdata), + .v2e_tlast(v2e_tlast), + .v2e_tvalid(v2e_tvalid), + .v2e_tready(v2e_tready), + + // Ethernet to CPU + .e2c_tdata(arm_eth_rx_tdata_b), + .e2c_tkeep(arm_eth_rx_tkeep_b), + .e2c_tlast(arm_eth_rx_tlast_b), + .e2c_tvalid(arm_eth_rx_tvalid_b), + .e2c_tready(arm_eth_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata(arm_eth_tx_tdata_b), + .c2e_tkeep(arm_eth_tx_tkeep_b), + .c2e_tlast(arm_eth_tx_tlast_b), + .c2e_tvalid(arm_eth_tx_tvalid_b), + .c2e_tready(arm_eth_tx_tready_b), + + // Misc + .port_info(sfp_port_info), + .device_id(device_id), + + // LED + .link_up(sfp_link_up), + .activity(LED_ACT1) + ); + + assign ps_gpio_in[60] = ps_gpio_tri[60] ? sfp_link_up : ps_gpio_out[60]; + assign LED_LINK1 = sfp_link_up; + + ///////////////////////////////////////////////////////////////////// + // + // Ethernet DMA (SFP to ARM) + // + ////////////////////////////////////////////////////////////////////// + + assign IRQ_F2P[0] = arm_eth_rx_irq; + assign IRQ_F2P[1] = arm_eth_tx_irq; + + assign {s_axi_hp0_awid, s_axi_hp0_arid} = 12'd0; + assign {s_axi_eth_descriptor_awid, s_axi_eth_descriptor_arid} = 10'd0; + + axi_eth_dma inst_axi_eth_dma ( + .s_axi_lite_aclk(clk40), + .m_axi_sg_aclk(clk40), + .m_axi_mm2s_aclk(clk40), + .m_axi_s2mm_aclk(clk40), + .axi_resetn(clk40_rstn), + + .s_axi_lite_awaddr(m_axi_eth_dma_awaddr), //FIXME: Synthesis Warning: port width(10) doesn't match 32 + .s_axi_lite_awvalid(m_axi_eth_dma_awvalid), + .s_axi_lite_awready(m_axi_eth_dma_awready), + + .s_axi_lite_wdata(m_axi_eth_dma_wdata), + .s_axi_lite_wvalid(m_axi_eth_dma_wvalid), + .s_axi_lite_wready(m_axi_eth_dma_wready), + + .s_axi_lite_bresp(m_axi_eth_dma_bresp), + .s_axi_lite_bvalid(m_axi_eth_dma_bvalid), + .s_axi_lite_bready(m_axi_eth_dma_bready), + + .s_axi_lite_araddr(m_axi_eth_dma_araddr), //FIXME: Synthesis Warning: port width(10) doesn't match 32 + .s_axi_lite_arvalid(m_axi_eth_dma_arvalid), + .s_axi_lite_arready(m_axi_eth_dma_arready), + + .s_axi_lite_rdata(m_axi_eth_dma_rdata), + .s_axi_lite_rresp(m_axi_eth_dma_rresp), + .s_axi_lite_rvalid(m_axi_eth_dma_rvalid), + .s_axi_lite_rready(m_axi_eth_dma_rready), + + .m_axi_sg_awaddr(s_axi_eth_descriptor_awaddr), + .m_axi_sg_awlen(s_axi_eth_descriptor_awlen), + .m_axi_sg_awsize(s_axi_eth_descriptor_awsize), + .m_axi_sg_awburst(s_axi_eth_descriptor_awburst), + .m_axi_sg_awprot(s_axi_eth_descriptor_awprot), + .m_axi_sg_awcache(s_axi_eth_descriptor_awcache), + .m_axi_sg_awvalid(s_axi_eth_descriptor_awvalid), + .m_axi_sg_awready(s_axi_eth_descriptor_awready), + .m_axi_sg_wdata(s_axi_eth_descriptor_wdata), + .m_axi_sg_wstrb(s_axi_eth_descriptor_wstrb), + .m_axi_sg_wlast(s_axi_eth_descriptor_wlast), + .m_axi_sg_wvalid(s_axi_eth_descriptor_wvalid), + .m_axi_sg_wready(s_axi_eth_descriptor_wready), + .m_axi_sg_bresp(s_axi_eth_descriptor_bresp), + .m_axi_sg_bvalid(s_axi_eth_descriptor_bvalid), + .m_axi_sg_bready(s_axi_eth_descriptor_bready), + .m_axi_sg_araddr(s_axi_eth_descriptor_araddr), + .m_axi_sg_arlen(s_axi_eth_descriptor_arlen), + .m_axi_sg_arsize(s_axi_eth_descriptor_arsize), + .m_axi_sg_arburst(s_axi_eth_descriptor_arburst), + .m_axi_sg_arprot(s_axi_eth_descriptor_arprot), + .m_axi_sg_arcache(s_axi_eth_descriptor_arcache), + .m_axi_sg_arvalid(s_axi_eth_descriptor_arvalid), + .m_axi_sg_arready(s_axi_eth_descriptor_arready), + .m_axi_sg_rdata(s_axi_eth_descriptor_rdata), + .m_axi_sg_rresp(s_axi_eth_descriptor_rresp), + .m_axi_sg_rlast(s_axi_eth_descriptor_rlast), + .m_axi_sg_rvalid(s_axi_eth_descriptor_rvalid), + .m_axi_sg_rready(s_axi_eth_descriptor_rready), + + .m_axi_mm2s_araddr(s_axi_hp0_araddr), + .m_axi_mm2s_arlen(s_axi_hp0_arlen), + .m_axi_mm2s_arsize(s_axi_hp0_arsize), + .m_axi_mm2s_arburst(s_axi_hp0_arburst), + .m_axi_mm2s_arprot(s_axi_hp0_arprot), + .m_axi_mm2s_arcache(s_axi_hp0_arcache), + .m_axi_mm2s_arvalid(s_axi_hp0_arvalid), + .m_axi_mm2s_arready(s_axi_hp0_arready), + .m_axi_mm2s_rdata(s_axi_hp0_rdata), + .m_axi_mm2s_rresp(s_axi_hp0_rresp), + .m_axi_mm2s_rlast(s_axi_hp0_rlast), + .m_axi_mm2s_rvalid(s_axi_hp0_rvalid), + .m_axi_mm2s_rready(s_axi_hp0_rready), + + .mm2s_prmry_reset_out_n(), + .m_axis_mm2s_tdata(arm_eth_tx_tdata), + .m_axis_mm2s_tkeep(arm_eth_tx_tkeep), + .m_axis_mm2s_tvalid(arm_eth_tx_tvalid), + .m_axis_mm2s_tready(arm_eth_tx_tready), + .m_axis_mm2s_tlast(arm_eth_tx_tlast), + + .m_axi_s2mm_awaddr(s_axi_hp0_awaddr), + .m_axi_s2mm_awlen(s_axi_hp0_awlen), + .m_axi_s2mm_awsize(s_axi_hp0_awsize), + .m_axi_s2mm_awburst(s_axi_hp0_awburst), + .m_axi_s2mm_awprot(s_axi_hp0_awprot), + .m_axi_s2mm_awcache(s_axi_hp0_awcache), + .m_axi_s2mm_awvalid(s_axi_hp0_awvalid), + .m_axi_s2mm_awready(s_axi_hp0_awready), + .m_axi_s2mm_wdata(s_axi_hp0_wdata), + .m_axi_s2mm_wstrb(s_axi_hp0_wstrb), + .m_axi_s2mm_wlast(s_axi_hp0_wlast), + .m_axi_s2mm_wvalid(s_axi_hp0_wvalid), + .m_axi_s2mm_wready(s_axi_hp0_wready), + .m_axi_s2mm_bresp(s_axi_hp0_bresp), + .m_axi_s2mm_bvalid(s_axi_hp0_bvalid), + .m_axi_s2mm_bready(s_axi_hp0_bready), + + .s2mm_prmry_reset_out_n(), + .s_axis_s2mm_tdata(arm_eth_rx_tdata), + .s_axis_s2mm_tkeep(arm_eth_rx_tkeep), + .s_axis_s2mm_tvalid(arm_eth_rx_tvalid), + .s_axis_s2mm_tready(arm_eth_rx_tready), + .s_axis_s2mm_tlast(arm_eth_rx_tlast), + + .mm2s_introut(arm_eth_tx_irq), + .s2mm_introut(arm_eth_rx_irq), + .axi_dma_tstvec() + ); + + // Clock crossing fifo from dma(clk40) to sfp(bus_clk) + axi_fifo_2clk #(.WIDTH(1+8+64), .SIZE(5)) eth_tx_fifo_2clk_i ( + .reset(clk40_rst), + .i_aclk(clk40), + .i_tdata({arm_eth_tx_tlast, arm_eth_tx_tkeep, arm_eth_tx_tdata}), + .i_tvalid(arm_eth_tx_tvalid), + .i_tready(arm_eth_tx_tready), + .o_aclk(bus_clk), + .o_tdata({arm_eth_tx_tlast_b, arm_eth_tx_tkeep_b, arm_eth_tx_tdata_b}), + .o_tvalid(arm_eth_tx_tvalid_b), + .o_tready(arm_eth_tx_tready_b) + ); + + // Clock crossing fifo from sfp(bus_clk) to dma(clk40) + axi_fifo_2clk #(.WIDTH(1+8+64), .SIZE(5)) eth_rx_fifo_2clk_i ( + .reset(bus_rst), + .i_aclk(bus_clk), + .i_tdata({arm_eth_rx_tlast_b, arm_eth_rx_tkeep_b, arm_eth_rx_tdata_b}), + .i_tvalid(arm_eth_rx_tvalid_b), + .i_tready(arm_eth_rx_tready_b), + .o_aclk(clk40), + .o_tdata({arm_eth_rx_tlast, arm_eth_rx_tkeep, arm_eth_rx_tdata}), + .o_tvalid(arm_eth_rx_tvalid), + .o_tready(arm_eth_rx_tready) + ); + + ///////////////////////////////////////////////////////////////////// + // + // PS Connections + // + ////////////////////////////////////////////////////////////////////// + + wire [63:0] ps_gpio_in; + wire [63:0] ps_gpio_out; + wire [63:0] ps_gpio_tri; + + e320_ps_bd e320_ps_bd_i ( + // DDR Interface + .DDR_VRN(PS_DDR3_VRN), + .DDR_VRP(PS_DDR3_VRP), + .DDR_addr(PS_DDR3_ADDR), + .DDR_ba(PS_DDR3_BA), + .DDR_cas_n(PS_DDR3_CAS_N), + .DDR_ck_n(DDR_MODCLK_N), + .DDR_ck_p(DDR_MODCLK_P), + .DDR_cke(PS_DDR3_CKE), + .DDR_cs_n(PS_DDR3_CS_N), + .DDR_dm(PS_DDR3_DM), + .DDR_dq(PS_DDR3_DQ), + .DDR_dqs_n(PS_DDR3_DQS_N), + .DDR_dqs_p(PS_DDR3_DQS_P), + .DDR_odt(PS_DDR3_ODT), + .DDR_ras_n(PS_DDR3_RAS_N), + .DDR_reset_n(PS_DDR3_RESET_N), + .DDR_we_n(PS_DDR3_WE_N), + + // Clocks + .FCLK_CLK0(FCLK_CLK0), + .FCLK_CLK1(FCLK_CLK1), + .FCLK_CLK2(FCLK_CLK2), + .FCLK_CLK3(FCLK_CLK3), + + // Resets + .FCLK_RESET0_N(FCLK_RESET0_N), + + // GPIO + .GPIO_0_tri_i(ps_gpio_in), + .GPIO_0_tri_o(ps_gpio_out), + .GPIO_0_tri_t(ps_gpio_tri), + + // Interrupts + .IRQ_F2P(IRQ_F2P), + + // MIO + .MIO(PS_MIO), + + .PS_CLK(PS_CLK), + .PS_PORB(PS_POR_B), + .PS_SRSTB(PS_SRST_B), + + // SPI + .SPI0_MISO_I(XCVR_SPI_MISO), + .SPI0_MISO_O(), + .SPI0_MISO_T(), + .SPI0_MOSI_I(1'b0), + .SPI0_MOSI_O(XCVR_SPI_MOSI), + .SPI0_MOSI_T(), + .SPI0_SCLK_I(1'b0), + .SPI0_SCLK_O(XCVR_SPI_CLK), + .SPI0_SCLK_T(), + .SPI0_SS1_O(), + .SPI0_SS2_O(), + .SPI0_SS_I(1'b1), + .SPI0_SS_O(XCVR_SPI_CS_N), + .SPI0_SS_T(), + + .SPI1_MISO_I(1'b0), + .SPI1_MISO_O(), + .SPI1_MISO_T(), + .SPI1_MOSI_I(1'b0), + .SPI1_MOSI_O(CLK_PLL_SDATA), + .SPI1_MOSI_T(), + .SPI1_SCLK_I(1'b0), + .SPI1_SCLK_O(CLK_PLL_SCLK), + .SPI1_SCLK_T(), + .SPI1_SS1_O(), + .SPI1_SS2_O(), + .SPI1_SS_I(1'b1), + .SPI1_SS_O(CLK_PLL_SLE), + .SPI1_SS_T(), + + // Eth DMA Descriptor + .s_axi_eth_descriptor_araddr(s_axi_eth_descriptor_araddr), + .s_axi_eth_descriptor_arburst(s_axi_eth_descriptor_arburst), + .s_axi_eth_descriptor_arcache(s_axi_eth_descriptor_arcache), + .s_axi_eth_descriptor_arid(s_axi_eth_descriptor_arid), + .s_axi_eth_descriptor_arlen(s_axi_eth_descriptor_arlen), + .s_axi_eth_descriptor_arlock(1'b0), + .s_axi_eth_descriptor_arprot(s_axi_eth_descriptor_arprot), + .s_axi_eth_descriptor_arqos(4'b0), + .s_axi_eth_descriptor_arready(s_axi_eth_descriptor_arready), + .s_axi_eth_descriptor_arsize(s_axi_eth_descriptor_arsize), + .s_axi_eth_descriptor_arvalid(s_axi_eth_descriptor_arvalid), + .s_axi_eth_descriptor_awaddr(s_axi_eth_descriptor_awaddr), + .s_axi_eth_descriptor_awburst(s_axi_eth_descriptor_awburst), + .s_axi_eth_descriptor_awcache(s_axi_eth_descriptor_awcache), + .s_axi_eth_descriptor_awid(s_axi_eth_descriptor_awid), + .s_axi_eth_descriptor_awlen(s_axi_eth_descriptor_awlen), + .s_axi_eth_descriptor_awlock(1'b0), + .s_axi_eth_descriptor_awprot(s_axi_eth_descriptor_awprot), + .s_axi_eth_descriptor_awqos(4'b0), + .s_axi_eth_descriptor_awready(s_axi_eth_descriptor_awready), + .s_axi_eth_descriptor_awsize(s_axi_eth_descriptor_awsize), + .s_axi_eth_descriptor_awvalid(s_axi_eth_descriptor_awvalid), + .s_axi_eth_descriptor_bid(), + .s_axi_eth_descriptor_bready(s_axi_eth_descriptor_bready), + .s_axi_eth_descriptor_bresp(s_axi_eth_descriptor_bresp), + .s_axi_eth_descriptor_bvalid(s_axi_eth_descriptor_bvalid), + .s_axi_eth_descriptor_rdata(s_axi_eth_descriptor_rdata), + .s_axi_eth_descriptor_rid(), + .s_axi_eth_descriptor_rlast(s_axi_eth_descriptor_rlast), + .s_axi_eth_descriptor_rready(s_axi_eth_descriptor_rready), + .s_axi_eth_descriptor_rresp(s_axi_eth_descriptor_rresp), + .s_axi_eth_descriptor_rvalid(s_axi_eth_descriptor_rvalid), + .s_axi_eth_descriptor_wdata(s_axi_eth_descriptor_wdata), + .s_axi_eth_descriptor_wlast(s_axi_eth_descriptor_wlast), + .s_axi_eth_descriptor_wready(s_axi_eth_descriptor_wready), + .s_axi_eth_descriptor_wstrb(s_axi_eth_descriptor_wstrb), + .s_axi_eth_descriptor_wvalid(s_axi_eth_descriptor_wvalid), + + // HP0 - Eth DMA + .S_AXI_HP0_ACLK(clk40), + .S_AXI_HP0_ARESETN(clk40_rstn), + .S_AXI_HP0_araddr(s_axi_hp0_araddr), + .S_AXI_HP0_arburst(s_axi_hp0_arburst), + .S_AXI_HP0_arcache(s_axi_hp0_arcache), + .S_AXI_HP0_arid(s_axi_hp0_arid), + .S_AXI_HP0_arlen(s_axi_hp0_arlen), + .S_AXI_HP0_arlock(1'b0), + .S_AXI_HP0_arprot(s_axi_hp0_arprot), + .S_AXI_HP0_arqos(4'b0), + .S_AXI_HP0_arready(s_axi_hp0_arready), + .S_AXI_HP0_arsize(s_axi_hp0_arsize), + .S_AXI_HP0_arvalid(s_axi_hp0_arvalid), + .S_AXI_HP0_awaddr(s_axi_hp0_awaddr), + .S_AXI_HP0_awburst(s_axi_hp0_awburst), + .S_AXI_HP0_awcache(s_axi_hp0_awcache), + .S_AXI_HP0_awid(s_axi_hp0_awid), + .S_AXI_HP0_awlen(s_axi_hp0_awlen), + .S_AXI_HP0_awlock(1'b0), + .S_AXI_HP0_awprot(s_axi_hp0_awprot), + .S_AXI_HP0_awqos(4'b0), + .S_AXI_HP0_awready(s_axi_hp0_awready), + .S_AXI_HP0_awsize(s_axi_hp0_awsize), + .S_AXI_HP0_awvalid(s_axi_hp0_awvalid), + .S_AXI_HP0_bid(), + .S_AXI_HP0_bready(s_axi_hp0_bready), + .S_AXI_HP0_bresp(s_axi_hp0_bresp), + .S_AXI_HP0_bvalid(s_axi_hp0_bvalid), + .S_AXI_HP0_rdata(s_axi_hp0_rdata), + .S_AXI_HP0_rid(), + .S_AXI_HP0_rlast(s_axi_hp0_rlast), + .S_AXI_HP0_rready(s_axi_hp0_rready), + .S_AXI_HP0_rresp(s_axi_hp0_rresp), + .S_AXI_HP0_rvalid(s_axi_hp0_rvalid), + .S_AXI_HP0_wdata(s_axi_hp0_wdata), + .S_AXI_HP0_wlast(s_axi_hp0_wlast), + .S_AXI_HP0_wready(s_axi_hp0_wready), + .S_AXI_HP0_wstrb(s_axi_hp0_wstrb), + .S_AXI_HP0_wvalid(s_axi_hp0_wvalid), + .m_axi_eth_dma_araddr(m_axi_eth_dma_araddr), + .m_axi_eth_dma_arprot(), + .m_axi_eth_dma_arready(m_axi_eth_dma_arready), + .m_axi_eth_dma_arvalid(m_axi_eth_dma_arvalid), + .m_axi_eth_dma_awaddr(m_axi_eth_dma_awaddr), + .m_axi_eth_dma_awprot(), + .m_axi_eth_dma_awready(m_axi_eth_dma_awready), + .m_axi_eth_dma_awvalid(m_axi_eth_dma_awvalid), + .m_axi_eth_dma_bready(m_axi_eth_dma_bready), + .m_axi_eth_dma_bresp(m_axi_eth_dma_bresp), + .m_axi_eth_dma_bvalid(m_axi_eth_dma_bvalid), + .m_axi_eth_dma_rdata(m_axi_eth_dma_rdata), + .m_axi_eth_dma_rready(m_axi_eth_dma_rready), + .m_axi_eth_dma_rresp(m_axi_eth_dma_rresp), + .m_axi_eth_dma_rvalid(m_axi_eth_dma_rvalid), + .m_axi_eth_dma_wdata(m_axi_eth_dma_wdata), + .m_axi_eth_dma_wready(m_axi_eth_dma_wready), + .m_axi_eth_dma_wstrb(m_axi_eth_dma_wstrb), + .m_axi_eth_dma_wvalid(m_axi_eth_dma_wvalid), + + // MGT IO Regport + .m_axi_net_araddr(m_axi_net_araddr), + .m_axi_net_arprot(), + .m_axi_net_arready(m_axi_net_arready), + .m_axi_net_arvalid(m_axi_net_arvalid), + .m_axi_net_awaddr(m_axi_net_awaddr), + .m_axi_net_awprot(), + .m_axi_net_awready(m_axi_net_awready), + .m_axi_net_awvalid(m_axi_net_awvalid), + .m_axi_net_bready(m_axi_net_bready), + .m_axi_net_bresp(m_axi_net_bresp), + .m_axi_net_bvalid(m_axi_net_bvalid), + .m_axi_net_rdata(m_axi_net_rdata), + .m_axi_net_rready(m_axi_net_rready), + .m_axi_net_rresp(m_axi_net_rresp), + .m_axi_net_rvalid(m_axi_net_rvalid), + .m_axi_net_wdata(m_axi_net_wdata), + .m_axi_net_wready(m_axi_net_wready), + .m_axi_net_wstrb(m_axi_net_wstrb), + .m_axi_net_wvalid(m_axi_net_wvalid), + + // XBAR Regport + .m_axi_xbar_araddr(m_axi_xbar_araddr), + .m_axi_xbar_arprot(), + .m_axi_xbar_arready(m_axi_xbar_arready), + .m_axi_xbar_arvalid(m_axi_xbar_arvalid), + .m_axi_xbar_awaddr(m_axi_xbar_awaddr), + .m_axi_xbar_awprot(), + .m_axi_xbar_awready(m_axi_xbar_awready), + .m_axi_xbar_awvalid(m_axi_xbar_awvalid), + .m_axi_xbar_bready(m_axi_xbar_bready), + .m_axi_xbar_bresp(m_axi_xbar_bresp), + .m_axi_xbar_bvalid(m_axi_xbar_bvalid), + .m_axi_xbar_rdata(m_axi_xbar_rdata), + .m_axi_xbar_rready(m_axi_xbar_rready), + .m_axi_xbar_rresp(m_axi_xbar_rresp), + .m_axi_xbar_rvalid(m_axi_xbar_rvalid), + .m_axi_xbar_wdata(m_axi_xbar_wdata), + .m_axi_xbar_wready(m_axi_xbar_wready), + .m_axi_xbar_wstrb(m_axi_xbar_wstrb), + .m_axi_xbar_wvalid(m_axi_xbar_wvalid), + + // USB + .USBIND_0_port_indctl(), + .USBIND_0_vbus_pwrfault(), + .USBIND_0_vbus_pwrselect(), + + .bus_clk(bus_clk), + .bus_rstn(~bus_rst), + .clk40(clk40), + .clk40_rstn(clk40_rstn), + .S_AXI_GP0_ACLK(clk40), + .S_AXI_GP0_ARESETN(clk40_rstn), + + // DMA + .s_axis_dma_tdata(s_axis_dma_tdata), + .s_axis_dma_tdest(s_axis_dma_tdest), + .s_axis_dma_tlast(s_axis_dma_tlast), + .s_axis_dma_tready(s_axis_dma_tready), + .s_axis_dma_tvalid(s_axis_dma_tvalid), + .m_axis_dma_tdata(m_axis_dma_tdata), + .m_axis_dma_tuser(m_axis_dma_tuser), + .m_axis_dma_tlast(m_axis_dma_tlast), + .m_axis_dma_tready(m_axis_dma_tready), + .m_axis_dma_tvalid(m_axis_dma_tvalid) + ); + + ///////////////////////////////////////////////////////////////////// + // + // GPSDO Control and Status + // + ///////////////////////////////////////////////////////////////////// + + wire [31:0] gps_ctrl; + wire [31:0] gps_status; + + assign CLK_GPS_PWR_EN = gps_ctrl[0]; + assign GPS_RST_N = gps_ctrl[1]; + assign GPS_INITSURV_N = gps_ctrl[2]; + assign gps_status[0] = GPS_LOCK; + assign gps_status[1] = GPS_ALARM; + assign gps_status[2] = GPS_PHASELOCK; + assign gps_status[3] = GPS_SURVEY; + assign gps_status[4] = GPS_WARMUP; + assign gps_status[31:5] = 'd0; + + ///////////////////////////////////////////////////////////////////// + // + // E320 Core: + // - xbar + // - Radio + // - DMA + // - DRAM + // - CEs + // + ////////////////////////////////////////////////////////////////////// + + wire [31:0] build_datestamp; + + USR_ACCESSE2 usr_access_i ( + .DATA(build_datestamp), .CFGCLK(), .DATAVALID() + ); + + e320_core #( + .REG_AWIDTH(REG_AWIDTH), + .BUS_CLK_RATE(BUS_CLK_RATE), + .NUM_RADIOS(NUM_RADIOS), + .NUM_CHANNELS(NUM_CHANNELS), + .NUM_DBOARDS(NUM_DBOARDS), + .FP_GPIO_WIDTH(FP_GPIO_WIDTH), + .DB_GPIO_WIDTH(DB_GPIO_WIDTH) + ) e320_core_i ( + + //Clocks and resets + .radio_clk(radio_clk), + .radio_rst(radio_rst), + .bus_clk(bus_clk), + .bus_rst(bus_rst), + .ddr3_dma_clk(ddr3_dma_clk), + .clk40(clk40), + + // Clocking and PPS Controls/Indicators + .pps_refclk(pps_refclk), + .refclk_locked(refclk_locked_busclk), + .pps_select(pps_select), + .ref_select(ref_select), + + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(m_axi_xbar_awaddr), + .s_axi_awvalid(m_axi_xbar_awvalid), + .s_axi_awready(m_axi_xbar_awready), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(m_axi_xbar_wdata), + .s_axi_wstrb(m_axi_xbar_wstrb), + .s_axi_wvalid(m_axi_xbar_wvalid), + .s_axi_wready(m_axi_xbar_wready), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(m_axi_xbar_bresp), + .s_axi_bvalid(m_axi_xbar_bvalid), + .s_axi_bready(m_axi_xbar_bready), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(m_axi_xbar_araddr), + .s_axi_arvalid(m_axi_xbar_arvalid), + .s_axi_arready(m_axi_xbar_arready), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(m_axi_xbar_rdata), + .s_axi_rresp(m_axi_xbar_rresp), + .s_axi_rvalid(m_axi_xbar_rvalid), + .s_axi_rready(m_axi_xbar_rready), + + // DRAM signals + .ddr3_axi_clk (ddr3_axi_clk), + .ddr3_axi_rst (ddr3_axi_rst), + .ddr3_running (ddr3_running), + // Slave Interface Write Address Ports + .ddr3_axi_awid (ddr3_axi_awid), + .ddr3_axi_awaddr (ddr3_axi_awaddr), + .ddr3_axi_awlen (ddr3_axi_awlen), + .ddr3_axi_awsize (ddr3_axi_awsize), + .ddr3_axi_awburst (ddr3_axi_awburst), + .ddr3_axi_awlock (ddr3_axi_awlock), + .ddr3_axi_awcache (ddr3_axi_awcache), + .ddr3_axi_awprot (ddr3_axi_awprot), + .ddr3_axi_awqos (ddr3_axi_awqos), + .ddr3_axi_awvalid (ddr3_axi_awvalid), + .ddr3_axi_awready (ddr3_axi_awready), + // Slave Interface Write Data Ports + .ddr3_axi_wdata (ddr3_axi_wdata), + .ddr3_axi_wstrb (ddr3_axi_wstrb), + .ddr3_axi_wlast (ddr3_axi_wlast), + .ddr3_axi_wvalid (ddr3_axi_wvalid), + .ddr3_axi_wready (ddr3_axi_wready), + // Slave Interface Write Response Ports + .ddr3_axi_bid (ddr3_axi_bid), + .ddr3_axi_bresp (ddr3_axi_bresp), + .ddr3_axi_bvalid (ddr3_axi_bvalid), + .ddr3_axi_bready (ddr3_axi_bready), + // Slave Interface Read Address Ports + .ddr3_axi_arid (ddr3_axi_arid), + .ddr3_axi_araddr (ddr3_axi_araddr), + .ddr3_axi_arlen (ddr3_axi_arlen), + .ddr3_axi_arsize (ddr3_axi_arsize), + .ddr3_axi_arburst (ddr3_axi_arburst), + .ddr3_axi_arlock (ddr3_axi_arlock), + .ddr3_axi_arcache (ddr3_axi_arcache), + .ddr3_axi_arprot (ddr3_axi_arprot), + .ddr3_axi_arqos (ddr3_axi_arqos), + .ddr3_axi_arvalid (ddr3_axi_arvalid), + .ddr3_axi_arready (ddr3_axi_arready), + // Slave Interface Read Data Ports + .ddr3_axi_rid (ddr3_axi_rid), + .ddr3_axi_rdata (ddr3_axi_rdata), + .ddr3_axi_rresp (ddr3_axi_rresp), + .ddr3_axi_rlast (ddr3_axi_rlast), + .ddr3_axi_rvalid (ddr3_axi_rvalid), + .ddr3_axi_rready (ddr3_axi_rready), + + + // Radio ATR + .rx_atr(rx_atr), + .tx_atr(tx_atr), + + // Front-Panel GPIO + .fp_gpio_in(fp_gpio_in), + .fp_gpio_tri(fp_gpio_tri), + .fp_gpio_out(fp_gpio_out), + + // PS GPIO Connection + .ps_gpio_tri(ps_gpio_tri[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1: FP_GPIO_OFFSET]), + .ps_gpio_out(ps_gpio_out[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1: FP_GPIO_OFFSET]), + .ps_gpio_in(ps_gpio_in[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1: FP_GPIO_OFFSET]), + + // DB GPIO + .db_gpio_out_flat(db_gpio_out_flat), + .db_gpio_ddr_flat(db_gpio_ddr_flat), + .db_gpio_in_flat(db_gpio_in_flat), + .db_gpio_fab_flat(32'b0), // FIXME: Incorrect width + + // TX/RX LEDs + .leds_flat(leds_flat), + + // Radio Strobes + .rx_stb(rx_stb), + .tx_stb(tx_stb), + + // Radio Data + .rx(rx_flat), + .tx(tx_flat), + + // DMA to PS + .m_dma_tdata(s_axis_dma_tdata), + .m_dma_tdest(s_axis_dma_tdest), + .m_dma_tlast(s_axis_dma_tlast), + .m_dma_tready(s_axis_dma_tready), + .m_dma_tvalid(s_axis_dma_tvalid), + + .s_dma_tdata(m_axis_dma_tdata), + .s_dma_tuser(m_axis_dma_tuser), + .s_dma_tlast(m_axis_dma_tlast), + .s_dma_tready(m_axis_dma_tready), + .s_dma_tvalid(m_axis_dma_tvalid), + + // VITA to Ethernet + .v2e_tdata(v2e_tdata), + .v2e_tvalid(v2e_tvalid), + .v2e_tlast(v2e_tlast), + .v2e_tready(v2e_tready), + + // Ethernet to VITA + .e2v_tdata(e2v_tdata), + .e2v_tlast(e2v_tlast), + .e2v_tvalid(e2v_tvalid), + .e2v_tready(e2v_tready), + + .build_datestamp(build_datestamp), + .sfp_ports_info(sfp_port_info), + .gps_status(gps_status), + .gps_ctrl(gps_ctrl), + .dboard_status(dboard_status), + .xadc_readback({20'h0, device_temp}), + .fp_gpio_ctrl(fp_gpio_ctrl), + .dboard_ctrl(dboard_ctrl), + .device_id(device_id) + ); + +endmodule // e320 +`default_nettype wire diff --git a/fpga/usrp3/top/e320/e320_10ge.xdc b/fpga/usrp3/top/e320/e320_10ge.xdc new file mode 100644 index 000000000..ad84a1b7f --- /dev/null +++ b/fpga/usrp3/top/e320/e320_10ge.xdc @@ -0,0 +1,16 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0-or-later +# + + +# No need for any asynchronous clock groups between bus_clk and the recovered clocks, +# because bus_clk already has a blanket asynchronous constraint from the top level XDC. + +# Remove analysis between the xge_clk and the recovered clocks from the MGT PHYs, +# since they cannot be related to one another with any known phase or period. +set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ sfp_wrapper_*/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/RXOUTCLK}] -group [get_clocks xge_clk] +set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ sfp_wrapper_*/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/TXOUTCLK}] -group [get_clocks xge_clk] + +set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *PRE}] +set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *CLR}] diff --git a/fpga/usrp3/top/e320/e320_10ge_port0.xdc b/fpga/usrp3/top/e320/e320_10ge_port0.xdc new file mode 100644 index 000000000..3cb98091b --- /dev/null +++ b/fpga/usrp3/top/e320/e320_10ge_port0.xdc @@ -0,0 +1,7 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + +set_property LOC GTXE2_CHANNEL_X0Y12 [get_cells -hierarchical -filter {NAME =~ "*sfp_wrapper_0/mgt_io_i/ten_gige_phy_i/*gtxe2_i*" && PRIMITIVE_TYPE == IO.gt.GTXE2_CHANNEL}] +set_property LOC GTXE2_COMMON_X0Y12 [get_cells -hierarchical -filter {NAME =~ "*gtxe2_common_0_i*" && PRIMITIVE_TYPE == IO.gt.GTXE2_COMMON}] diff --git a/fpga/usrp3/top/e320/e320_1ge.xdc b/fpga/usrp3/top/e320/e320_1ge.xdc new file mode 100644 index 000000000..7d5f51641 --- /dev/null +++ b/fpga/usrp3/top/e320/e320_1ge.xdc @@ -0,0 +1,15 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + + +# No need for any asynchronous clock groups between clk100 and the recovered clocks, +# because clk100 already has a blanket asynchronous constraint from the top level XDC. +set_clock_groups -asynchronous -group [get_clocks clk100] -group [get_clocks ge_clk] +set_clock_groups -asynchronous -group [get_clocks clk100] -group [get_clocks -of_objects [get_pins sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*/core_clocking_i/mmcm_*/CLKOUT0]] +set_clock_groups -asynchronous -group [get_clocks clk100] -group [get_clocks -of_objects [get_pins sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*/core_clocking_i/mmcm_*/CLKOUT1]] + +set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*reset_sync*/PRE}] +set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*/pma_reset_pipe_reg*/PRE}] +set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*/pma_reset_pipe*[0]/D}] diff --git a/fpga/usrp3/top/e320/e320_aurora.xdc b/fpga/usrp3/top/e320/e320_aurora.xdc new file mode 100644 index 000000000..3f6860de3 --- /dev/null +++ b/fpga/usrp3/top/e320/e320_aurora.xdc @@ -0,0 +1,13 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + + +create_generated_clock -name aurora_init_clk [get_pins -hierarchical -filter {NAME =~ "*aurora_clk_gen_i/dclk_divide_by_2_buf/O"}] + +set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks aurora_init_clk] + +set_false_path -to [get_pins -hierarchical -filter {NAME =~ "sfp_wrapper_*/mgt_io_i/aurora_phy*/aurora_64b66b_pcs_pma*/*/gt_reset_sync/stg1_*_cdc_to_reg/D"}] + +set_false_path -to [get_pins -hierarchical -filter {NAME =~ "*npio*/aurora_phy*/aurora_64b66b_pcs_pma*/*/gt_reset_sync/stg1_*_cdc_to_reg/D"}] diff --git a/fpga/usrp3/top/e320/e320_clocking.v b/fpga/usrp3/top/e320/e320_clocking.v new file mode 100644 index 000000000..fff99180e --- /dev/null +++ b/fpga/usrp3/top/e320/e320_clocking.v @@ -0,0 +1,220 @@ +///////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: e320_clocking.v +// +// Purpose: +// +// TODO: First, instantiate clock input buffers on all clocks to provide termination +// for the PCB traces. +// +// Second, PPS inputs from the back panel (called external) and the GPSDO are captured by +// the Reference Clock. Selection is performed amongst these and the internally-generated +// options. +// +////////////////////////////////////////////////////////////////////// + +module e320_clocking ( + input global_rst, + + // Reference Clk + input ref_clk_from_pin, + output ref_clk, + + // Input clocks + input clk156, // 156.25 MHz + + // Output clocks + output ddr3_dma_clk, + output reg clocks_locked = 1'b0, + + // PPS Capture & Selection + input ext_pps_from_pin, + input gps_pps_from_pin, + input [1:0] pps_select, + output reg pps_refclk +); + + //TODO: Code is same as n3xx, try reusing it. + + // Clock Buffering and Generation : /////////////////////////////////////////////////// + // + // Manually instantiate input buffers on all clocks, and a global buffer on the + // Reference Clock for use in the rest of the design. All other clocks must have + // global buffers other places, since the declarations here are for SI purposes. + // + /////////////////////////////////////////////////////////////////////////////////////// + + wire ref_clk_buf; + + // FPGA Reference Clock Buffering + // + // Only require an IBUF and BUFG here, since an MMCM is (thankfully) not needed + // to meet timing with the PPS signal. + IBUFG ref_clk_ibuf ( + .O(ref_clk_buf), + .I(ref_clk_from_pin) + ); + + BUFG ref_clk_bufg ( + .I(ref_clk_buf), + .O(ref_clk) + ); + + wire pps_ext_refclk; + wire pps_gps_refclk; + wire [1:0] pps_select_refclk; + + // Capture the external PPSs with a FF before sending them to the mux. To be safe, + // we double-synchronize the external signals. If we meet timing (which we should) + // then this is a two-cycle delay. If we don't meet timing, then it's 1-2 cycles + // and our system timing is thrown off--but at least our downstream logic doesn't + // go metastable! + synchronizer #( + .FALSE_PATH_TO_IN(0) + ) ext_pps_dsync ( + .clk(ref_clk), .rst(1'b0), .in(ext_pps_from_pin), .out(pps_ext_refclk) + ); + // Same deal with the GPSDO PPS input. Double-sync, then use it. + synchronizer #( + .FALSE_PATH_TO_IN(0) + ) gps_pps_dsync ( + .clk(ref_clk), .rst(1'b0), .in(gps_pps_from_pin), .out(pps_gps_refclk) + ); + + // Synchronize the select bits over to the reference clock as well. Note that this is + // a vector, so we could have some non-one-hot values creep through when changing. + // See the note below as to why this is safe. + synchronizer #( + .FALSE_PATH_TO_IN(1), + .WIDTH(2) + ) pps_select_dsync ( + .clk(ref_clk), .rst(1'b0), .in(pps_select), .out(pps_select_refclk) + ); + + // Bit locations for the pps_select vector. + localparam BIT_PPS_SEL_INT = 0; + localparam BIT_PPS_SEL_EXT = 1; + + // PPS MUX - selects internal/gpsdo or external PPS. + always @(posedge ref_clk) begin + + // Encoding is one-hot on these bits. It is possible when the vector is being double- + // synchronized to the reference clock domain that there could be multiple bits + // asserted simultaneously. This is not problematic because the order of operations + // in the following selection mux should take over and only one PPS should win. + // This could result in glitches, but that is expected during ANY PPS switchover + // since the switch is performed asynchronously to the PPS signal. + if (pps_select_refclk[BIT_PPS_SEL_INT]) begin + pps_refclk <= pps_gps_refclk; + end else if (pps_select_refclk[BIT_PPS_SEL_EXT]) begin + pps_refclk <= pps_ext_refclk; + end else begin + pps_refclk <= pps_gps_refclk; + end + end + + //--------------------------------------------------------------------------- + // Clock Generation + //--------------------------------------------------------------------------- + + MMCME2_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_MULT_F (6.000), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (3.125), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (6.400)) + mmcm_adv_inst ( + .CLKFBOUT (clkfbout), + .CLKFBOUTB (), + .CLKOUT0 (ddr3_dma_clk_raw), + .CLKOUT0B (), + .CLKOUT1 (), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + // Input clock control + .CLKFBIN (clkfbout), + .CLKIN1 (clk156), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (locked_raw), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (global_rst)); + + BUFG clk300_bufg + (.O (ddr3_dma_clk), + .I (ddr3_dma_clk_raw)); + + + //--------------------------------------------------------------------------- + // Lock Signal + //--------------------------------------------------------------------------- + // + // We assume that the LOCKED signal from the MMCM is not necessarily a clean + // asynchronous signal, so we want to make sure that the MMCM is really + // locked before we assert our clocks_locked output. + // + //--------------------------------------------------------------------------- + + reg [9:0] locked_count = ~0; + + synchronizer lock_sync_i ( + .clk(clk156), .rst(1'b0), .in(locked_raw), .out(locked_sync) + ); + + // Filter the locked signal + always @(posedge clk156 or posedge global_rst) + begin + if (global_rst) begin + locked_count <= ~0; + clocks_locked <= 0; + end else begin + if (~locked_sync) begin + locked_count <= ~0; + clocks_locked <= 1'b0; + end else begin + if (locked_count == 0) begin + clocks_locked <= 1'b1; + end else begin + clocks_locked <= 1'b0; + locked_count <= locked_count - 1; + end + end + end + end + +endmodule diff --git a/fpga/usrp3/top/e320/e320_core.v b/fpga/usrp3/top/e320/e320_core.v new file mode 100644 index 000000000..f8fccecc0 --- /dev/null +++ b/fpga/usrp3/top/e320/e320_core.v @@ -0,0 +1,1103 @@ +///////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0 +// +// Module: e320_core +// Description: +// - Motherboard Registers +// - DRAM Interconnect +// - Radio Front End control +// - Timekeeper +// - RFNoC Image Core +// +///////////////////////////////////////////////////////////////////// + +`default_nettype none +module e320_core #( + parameter REG_DWIDTH = 32, // Width of the AXI4-Lite data bus (must be 32 or 64) + parameter REG_AWIDTH = 32, // Width of the address bus + parameter BUS_CLK_RATE = 200000000, // bus_clk rate + parameter NUM_RADIOS = 1, + parameter NUM_CHANNELS = 2, + parameter NUM_DBOARDS = 1, + parameter NUM_CHANNELS_PER_DBOARD = 2, + parameter FP_GPIO_WIDTH = 8, // Front panel GPIO width + parameter DB_GPIO_WIDTH = 16, // Daughterboard GPIO width + parameter CHDR_WIDTH = 16'd64 , + parameter RFNOC_PROTOVER = {8'd1, 8'd0} +)( + // Clocks and resets + input wire radio_clk, + input wire radio_rst, + input wire bus_clk, + input wire bus_rst, + input wire ddr3_dma_clk, + input wire clk40, + + // Motherboard Registers: AXI lite interface + input wire s_axi_aclk, + input wire s_axi_aresetn, + input wire [REG_AWIDTH-1:0] s_axi_awaddr, + input wire s_axi_awvalid, + output wire s_axi_awready, + + input wire [REG_DWIDTH-1:0] s_axi_wdata, + input wire [REG_DWIDTH/8-1:0] s_axi_wstrb, + input wire s_axi_wvalid, + output wire s_axi_wready, + + output wire [1:0] s_axi_bresp, + output wire s_axi_bvalid, + input wire s_axi_bready, + + input wire [REG_AWIDTH-1:0] s_axi_araddr, + input wire s_axi_arvalid, + output wire s_axi_arready, + + output wire [REG_DWIDTH-1:0] s_axi_rdata, + output wire [1:0] s_axi_rresp, + output wire s_axi_rvalid, + input wire s_axi_rready, + + // PPS and Clock Control + input wire pps_refclk, + input wire refclk_locked, + output reg [1:0] pps_select, + output reg ref_select, + + // PS GPIO source + input wire [FP_GPIO_WIDTH-1:0] ps_gpio_out, + input wire [FP_GPIO_WIDTH-1:0] ps_gpio_tri, + output wire [FP_GPIO_WIDTH-1:0] ps_gpio_in, + + // Front Panel GPIO + input wire [FP_GPIO_WIDTH-1:0] fp_gpio_in, + output wire [FP_GPIO_WIDTH-1:0] fp_gpio_tri, + output wire [FP_GPIO_WIDTH-1:0] fp_gpio_out, + + // Radio GPIO control + output wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_out_flat, + output wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_ddr_flat, + input wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_in_flat, + input wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_fab_flat, + + // TX/RX LEDs + output wire [32*NUM_CHANNELS-1:0] leds_flat, + + // Radio ATR + output wire [NUM_CHANNELS-1:0] rx_atr, + output wire [NUM_CHANNELS-1:0] tx_atr, + + // Radio Data + input wire [NUM_CHANNELS-1:0] rx_stb, + input wire [NUM_CHANNELS-1:0] tx_stb, + input wire [32*NUM_CHANNELS-1:0] rx, + output wire [32*NUM_CHANNELS-1:0] tx, + + // AXI4 DDR3 Interface + input wire ddr3_axi_clk, + input wire ddr3_axi_rst, + input wire ddr3_running, + // Write Address Ports + output wire [3:0] ddr3_axi_awid, + output wire [31:0] ddr3_axi_awaddr, + output wire [7:0] ddr3_axi_awlen, + output wire [2:0] ddr3_axi_awsize, + output wire [1:0] ddr3_axi_awburst, + output wire [0:0] ddr3_axi_awlock, + output wire [3:0] ddr3_axi_awcache, + output wire [2:0] ddr3_axi_awprot, + output wire [3:0] ddr3_axi_awqos, + output wire ddr3_axi_awvalid, + input wire ddr3_axi_awready, + // Write Data Ports + output wire [255:0] ddr3_axi_wdata, + output wire [31:0] ddr3_axi_wstrb, + output wire ddr3_axi_wlast, + output wire ddr3_axi_wvalid, + input wire ddr3_axi_wready, + // Write Response Ports + output wire ddr3_axi_bready, + input wire [3:0] ddr3_axi_bid, + input wire [1:0] ddr3_axi_bresp, + input wire ddr3_axi_bvalid, + // Read Address Ports + output wire [3:0] ddr3_axi_arid, + output wire [31:0] ddr3_axi_araddr, + output wire [7:0] ddr3_axi_arlen, + output wire [2:0] ddr3_axi_arsize, + output wire [1:0] ddr3_axi_arburst, + output wire [0:0] ddr3_axi_arlock, + output wire [3:0] ddr3_axi_arcache, + output wire [2:0] ddr3_axi_arprot, + output wire [3:0] ddr3_axi_arqos, + output wire ddr3_axi_arvalid, + input wire ddr3_axi_arready, + // Read Data Ports + output wire ddr3_axi_rready, + input wire [3:0] ddr3_axi_rid, + input wire [255:0] ddr3_axi_rdata, + input wire [1:0] ddr3_axi_rresp, + input wire ddr3_axi_rlast, + input wire ddr3_axi_rvalid, + + + + // DMA xport adapter to PS + input wire [63:0] s_dma_tdata, + input wire [3:0] s_dma_tuser, + input wire s_dma_tlast, + output wire s_dma_tready, + input wire s_dma_tvalid, + + output wire [63:0] m_dma_tdata, + output wire [3:0] m_dma_tdest, + output wire m_dma_tlast, + input wire m_dma_tready, + output wire m_dma_tvalid, + + // e2v (Ethernet to Vita) and v2e (Vita to Ethernet) + output wire [63:0] v2e_tdata, + output wire v2e_tvalid, + output wire v2e_tlast, + input wire v2e_tready, + + input wire [63:0] e2v_tdata, + input wire e2v_tlast, + input wire e2v_tvalid, + output wire e2v_tready, + + // Misc + input wire [31:0] build_datestamp, + input wire [31:0] sfp_ports_info, + input wire [31:0] gps_status, + output reg [31:0] gps_ctrl, + input wire [31:0] dboard_status, + input wire [31:0] xadc_readback, + output reg [31:0] fp_gpio_ctrl, + output reg [31:0] dboard_ctrl, + output reg [15:0] device_id +); + + ///////////////////////////////////////////////////////////////////////////////// + // + // FPGA Compatibility Number + // Rules for modifying compat number: + // - Major is updated when the FPGA is changed and requires a software + // change as a result. + // - Minor is updated when a new feature is added to the FPGA that does not + // break software compatibility. + // + ///////////////////////////////////////////////////////////////////////////////// + + localparam [15:0] COMPAT_MAJOR = 16'd5; + localparam [15:0] COMPAT_MINOR = 16'd0; + + ///////////////////////////////////////////////////////////////////////////////// + + ///////////////////////////////////////////////////////////////////////////////// + // + // Motherboard Registers + // + ///////////////////////////////////////////////////////////////////////////////// + + // Register base + localparam REG_BASE_MISC = 14'h0; + localparam REG_BASE_TIMEKEEPER = 14'h1000; + + // Misc Registers + localparam REG_COMPAT_NUM = REG_BASE_MISC + 14'h00; + localparam REG_DATESTAMP = REG_BASE_MISC + 14'h04; + localparam REG_GIT_HASH = REG_BASE_MISC + 14'h08; + localparam REG_SCRATCH = REG_BASE_MISC + 14'h0C; + localparam REG_DEVICE_ID = REG_BASE_MISC + 14'h10; + localparam REG_RFNOC_INFO = REG_BASE_MISC + 14'h14; + localparam REG_CLOCK_CTRL = REG_BASE_MISC + 14'h18; + localparam REG_XADC_READBACK = REG_BASE_MISC + 14'h1C; + localparam REG_BUS_CLK_RATE = REG_BASE_MISC + 14'h20; + localparam REG_BUS_CLK_COUNT = REG_BASE_MISC + 14'h24; + localparam REG_SFP_PORT_INFO = REG_BASE_MISC + 14'h28; + localparam REG_FP_GPIO_CTRL = REG_BASE_MISC + 14'h2C; + localparam REG_FP_GPIO_MASTER = REG_BASE_MISC + 14'h30; + localparam REG_FP_GPIO_RADIO_SRC = REG_BASE_MISC + 14'h34; + localparam REG_GPS_CTRL = REG_BASE_MISC + 14'h38; + localparam REG_GPS_STATUS = REG_BASE_MISC + 14'h3C; + localparam REG_DBOARD_CTRL = REG_BASE_MISC + 14'h40; + localparam REG_DBOARD_STATUS = REG_BASE_MISC + 14'h44; + localparam REG_NUM_TIMEKEEPERS = REG_BASE_MISC + 14'h48; + + localparam NUM_TIMEKEEPERS = 16'd1; + + wire m_ctrlport_req_wr; + wire m_ctrlport_req_rd; + wire [19:0] m_ctrlport_req_addr; + wire [31:0] m_ctrlport_req_data; + wire m_ctrlport_req_has_time; + wire [63:0] m_ctrlport_req_time; + wire m_ctrlport_resp_ack; + wire [31:0] m_ctrlport_resp_data; + + reg [31:0] fp_gpio_master_reg = 32'h0; + reg [31:0] fp_gpio_src_reg = 32'h0; + + wire reg_wr_req; + wire [REG_AWIDTH-1:0] reg_wr_addr; + wire [REG_DWIDTH-1:0] reg_wr_data; + wire reg_rd_req; + wire [REG_AWIDTH-1:0] reg_rd_addr; + wire reg_rd_resp; + wire [REG_DWIDTH-1:0] reg_rd_data; + + reg reg_rd_resp_glob; + reg [REG_DWIDTH-1:0] reg_rd_data_glob; + wire reg_rd_resp_tk; + wire [REG_DWIDTH-1:0] reg_rd_data_tk; + + reg [31:0] scratch_reg = 32'h0; + reg [31:0] bus_counter = 32'h0; + + always @(posedge bus_clk) begin + if (bus_rst) + bus_counter <= 32'd0; + else + bus_counter <= bus_counter + 32'd1; + end + + // Regport Master to convert AXI4-Lite to regport + axil_regport_master #( + .DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .AWIDTH (REG_AWIDTH), // Width of the address bus + .WRBASE (0), // Write address base + .RDBASE (0), // Read address base + .TIMEOUT (10) // log2(timeout). Read will timeout after (2^TIMEOUT - 1) cycles + ) core_regport_master_i ( + // Clock and reset + .s_axi_aclk (s_axi_aclk), + .s_axi_aresetn (s_axi_aresetn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp (s_axi_bresp), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bready (s_axi_bready), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr (s_axi_araddr), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (s_axi_rdata), + .s_axi_rresp (s_axi_rresp), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rready (s_axi_rready), + // Register port: Write port (domain: reg_clk) + .reg_clk (bus_clk), + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + .reg_wr_keep (/*unused*/), + // Register port: Read port (domain: reg_clk) + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_resp (reg_rd_resp), + .reg_rd_data (reg_rd_data) + ); + + //-------------------------------------------------------------------- + // Global Registers + // ------------------------------------------------------------------- + + // Write Registers + always @ (posedge bus_clk) begin + if (bus_rst) begin + scratch_reg <= 32'h0; + pps_select <= 2'b01; // Default to internal + ref_select <= 1'b0; // Default to internal + fp_gpio_ctrl <= 32'h9; // Default to OFF - 4'b1001 + gps_ctrl <= 32'h3; // Default to gps_en, out of reset + dboard_ctrl <= 32'h1; // Default to mimo + device_id <= 16'h0; + end else if (reg_wr_req) begin + case (reg_wr_addr) + REG_DEVICE_ID: begin + device_id <= reg_wr_data[15:0]; + end + REG_FP_GPIO_MASTER: begin + fp_gpio_master_reg <= reg_wr_data; + end + REG_FP_GPIO_RADIO_SRC: begin + fp_gpio_src_reg <= reg_wr_data; + end + REG_SCRATCH: begin + scratch_reg <= reg_wr_data; + end + REG_CLOCK_CTRL: begin + pps_select <= reg_wr_data[1:0]; + ref_select <= reg_wr_data[2]; + end + REG_FP_GPIO_CTRL: begin + fp_gpio_ctrl <= reg_wr_data; + end + REG_GPS_CTRL: begin + gps_ctrl <= reg_wr_data; + end + REG_DBOARD_CTRL: begin + dboard_ctrl <= reg_wr_data; + end + endcase + end + end + + // Read Registers + always @ (posedge bus_clk) begin + if (bus_rst) begin + reg_rd_resp_glob <= 1'b0; + end + else begin + + if (reg_rd_req) begin + reg_rd_resp_glob <= 1'b1; + + case (reg_rd_addr) + REG_DEVICE_ID: + reg_rd_data_glob <= device_id; + + REG_RFNOC_INFO: + reg_rd_data_glob <= {CHDR_WIDTH[15:0], RFNOC_PROTOVER[15:0]}; + + REG_COMPAT_NUM: + reg_rd_data_glob <= {COMPAT_MAJOR[15:0], COMPAT_MINOR[15:0]}; + + REG_FP_GPIO_CTRL: + reg_rd_data_glob <= fp_gpio_ctrl; + + REG_FP_GPIO_MASTER: + reg_rd_data_glob <= fp_gpio_master_reg; + + REG_FP_GPIO_RADIO_SRC: + reg_rd_data_glob <= fp_gpio_src_reg; + + REG_DATESTAMP: + reg_rd_data_glob <= build_datestamp; + + REG_GIT_HASH: + `ifndef GIT_HASH + `define GIT_HASH 32'h0BADC0DE + `endif + reg_rd_data_glob <= `GIT_HASH; + + REG_SCRATCH: + reg_rd_data_glob <= scratch_reg; + + REG_CLOCK_CTRL: begin + reg_rd_data_glob <= 32'b0; + reg_rd_data_glob[1:0] <= pps_select; + reg_rd_data_glob[2] <= ref_select; + reg_rd_data_glob[3] <= refclk_locked; + end + + REG_XADC_READBACK: + reg_rd_data_glob <= xadc_readback; + + REG_BUS_CLK_RATE: + reg_rd_data_glob <= BUS_CLK_RATE; + + REG_BUS_CLK_COUNT: + reg_rd_data_glob <= bus_counter; + + REG_SFP_PORT_INFO: + reg_rd_data_glob <= sfp_ports_info; + + REG_GPS_CTRL: + reg_rd_data_glob <= gps_ctrl; + + REG_GPS_STATUS: + reg_rd_data_glob <= gps_status; + + REG_DBOARD_CTRL: + reg_rd_data_glob <= dboard_ctrl; + + REG_DBOARD_STATUS: + reg_rd_data_glob <= dboard_status; + + REG_NUM_TIMEKEEPERS: + reg_rd_data_glob <= NUM_TIMEKEEPERS; + + default: + reg_rd_resp_glob <= 1'b0; + endcase + end + else if (reg_rd_resp_glob) begin + reg_rd_resp_glob <= 1'b0; + end + end + end + + wire pps_radioclk; + + // Synchronize the PPS signal to the radio clock domain + synchronizer pps_radio_sync ( + .clk(radio_clk), .rst(1'b0), .in(pps_refclk), .out(pps_radioclk) + ); + + + ///////////////////////////////////////////////////////////////////////////// + // + // DRAM + // + ///////////////////////////////////////////////////////////////////////////// + + localparam NUM_DRAM_FIFOS = 2; + + wire ddr3_dma_rst; + + synchronizer #( + .INITIAL_VAL(1'b1) + ) ddr3_dma_rst_sync_i ( + .clk(ddr3_dma_clk), .rst(1'b0), .in(ddr3_axi_rst), .out(ddr3_dma_rst) + ); + + // AXI4 MM buses + wire [0:0] dram_axi_awid [0:NUM_DRAM_FIFOS-1]; + wire [31:0] dram_axi_awaddr [0:NUM_DRAM_FIFOS-1]; + wire [7:0] dram_axi_awlen [0:NUM_DRAM_FIFOS-1]; + wire [2:0] dram_axi_awsize [0:NUM_DRAM_FIFOS-1]; + wire [1:0] dram_axi_awburst [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_awlock [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_awcache [0:NUM_DRAM_FIFOS-1]; + wire [2:0] dram_axi_awprot [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_awqos [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_awregion [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_awuser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_awvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_awready [0:NUM_DRAM_FIFOS-1]; + wire [63:0] dram_axi_wdata [0:NUM_DRAM_FIFOS-1]; + wire [7:0] dram_axi_wstrb [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_wlast [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_wuser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_wvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_wready [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_bid [0:NUM_DRAM_FIFOS-1]; + wire [1:0] dram_axi_bresp [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_buser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_bvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_bready [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_arid [0:NUM_DRAM_FIFOS-1]; + wire [31:0] dram_axi_araddr [0:NUM_DRAM_FIFOS-1]; + wire [7:0] dram_axi_arlen [0:NUM_DRAM_FIFOS-1]; + wire [2:0] dram_axi_arsize [0:NUM_DRAM_FIFOS-1]; + wire [1:0] dram_axi_arburst [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_arlock [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_arcache [0:NUM_DRAM_FIFOS-1]; + wire [2:0] dram_axi_arprot [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_arqos [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_arregion [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_aruser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_arvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_arready [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_rid [0:NUM_DRAM_FIFOS-1]; + wire [63:0] dram_axi_rdata [0:NUM_DRAM_FIFOS-1]; + wire [1:0] dram_axi_rresp [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_rlast [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_ruser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_rvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_rready [0:NUM_DRAM_FIFOS-1]; + + axi_intercon_4x64_256_bd_wrapper axi_intercon_2x64_256_bd_i ( + .S00_AXI_ACLK (ddr3_dma_clk ), + .S00_AXI_ARESETN (~ddr3_dma_rst ), + .S00_AXI_AWID (dram_axi_awid [0]), + .S00_AXI_AWADDR (dram_axi_awaddr [0]), + .S00_AXI_AWLEN (dram_axi_awlen [0]), + .S00_AXI_AWSIZE (dram_axi_awsize [0]), + .S00_AXI_AWBURST (dram_axi_awburst [0]), + .S00_AXI_AWLOCK (dram_axi_awlock [0]), + .S00_AXI_AWCACHE (dram_axi_awcache [0]), + .S00_AXI_AWPROT (dram_axi_awprot [0]), + .S00_AXI_AWQOS (dram_axi_awqos [0]), + .S00_AXI_AWREGION (dram_axi_awregion[0]), + .S00_AXI_AWVALID (dram_axi_awvalid [0]), + .S00_AXI_AWREADY (dram_axi_awready [0]), + .S00_AXI_WDATA (dram_axi_wdata [0]), + .S00_AXI_WSTRB (dram_axi_wstrb [0]), + .S00_AXI_WLAST (dram_axi_wlast [0]), + .S00_AXI_WVALID (dram_axi_wvalid [0]), + .S00_AXI_WREADY (dram_axi_wready [0]), + .S00_AXI_BID (dram_axi_bid [0]), + .S00_AXI_BRESP (dram_axi_bresp [0]), + .S00_AXI_BVALID (dram_axi_bvalid [0]), + .S00_AXI_BREADY (dram_axi_bready [0]), + .S00_AXI_ARID (dram_axi_arid [0]), + .S00_AXI_ARADDR (dram_axi_araddr [0]), + .S00_AXI_ARLEN (dram_axi_arlen [0]), + .S00_AXI_ARSIZE (dram_axi_arsize [0]), + .S00_AXI_ARBURST (dram_axi_arburst [0]), + .S00_AXI_ARLOCK (dram_axi_arlock [0]), + .S00_AXI_ARCACHE (dram_axi_arcache [0]), + .S00_AXI_ARPROT (dram_axi_arprot [0]), + .S00_AXI_ARQOS (dram_axi_arqos [0]), + .S00_AXI_ARREGION (dram_axi_arregion[0]), + .S00_AXI_ARVALID (dram_axi_arvalid [0]), + .S00_AXI_ARREADY (dram_axi_arready [0]), + .S00_AXI_RID (dram_axi_rid [0]), + .S00_AXI_RDATA (dram_axi_rdata [0]), + .S00_AXI_RRESP (dram_axi_rresp [0]), + .S00_AXI_RLAST (dram_axi_rlast [0]), + .S00_AXI_RVALID (dram_axi_rvalid [0]), + .S00_AXI_RREADY (dram_axi_rready [0]), + // + .S01_AXI_ACLK (ddr3_dma_clk ), + .S01_AXI_ARESETN (~ddr3_dma_rst ), + .S01_AXI_AWID (dram_axi_awid [1]), + .S01_AXI_AWADDR (dram_axi_awaddr [1]), + .S01_AXI_AWLEN (dram_axi_awlen [1]), + .S01_AXI_AWSIZE (dram_axi_awsize [1]), + .S01_AXI_AWBURST (dram_axi_awburst [1]), + .S01_AXI_AWLOCK (dram_axi_awlock [1]), + .S01_AXI_AWCACHE (dram_axi_awcache [1]), + .S01_AXI_AWPROT (dram_axi_awprot [1]), + .S01_AXI_AWQOS (dram_axi_awqos [1]), + .S01_AXI_AWREGION (dram_axi_awregion[1]), + .S01_AXI_AWVALID (dram_axi_awvalid [1]), + .S01_AXI_AWREADY (dram_axi_awready [1]), + .S01_AXI_WDATA (dram_axi_wdata [1]), + .S01_AXI_WSTRB (dram_axi_wstrb [1]), + .S01_AXI_WLAST (dram_axi_wlast [1]), + .S01_AXI_WVALID (dram_axi_wvalid [1]), + .S01_AXI_WREADY (dram_axi_wready [1]), + .S01_AXI_BID (dram_axi_bid [1]), + .S01_AXI_BRESP (dram_axi_bresp [1]), + .S01_AXI_BVALID (dram_axi_bvalid [1]), + .S01_AXI_BREADY (dram_axi_bready [1]), + .S01_AXI_ARID (dram_axi_arid [1]), + .S01_AXI_ARADDR (dram_axi_araddr [1]), + .S01_AXI_ARLEN (dram_axi_arlen [1]), + .S01_AXI_ARSIZE (dram_axi_arsize [1]), + .S01_AXI_ARBURST (dram_axi_arburst [1]), + .S01_AXI_ARLOCK (dram_axi_arlock [1]), + .S01_AXI_ARCACHE (dram_axi_arcache [1]), + .S01_AXI_ARPROT (dram_axi_arprot [1]), + .S01_AXI_ARQOS (dram_axi_arqos [1]), + .S01_AXI_ARREGION (dram_axi_arregion[1]), + .S01_AXI_ARVALID (dram_axi_arvalid [1]), + .S01_AXI_ARREADY (dram_axi_arready [1]), + .S01_AXI_RID (dram_axi_rid [1]), + .S01_AXI_RDATA (dram_axi_rdata [1]), + .S01_AXI_RRESP (dram_axi_rresp [1]), + .S01_AXI_RLAST (dram_axi_rlast [1]), + .S01_AXI_RVALID (dram_axi_rvalid [1]), + .S01_AXI_RREADY (dram_axi_rready [1]), + // + .S02_AXI_ACLK (ddr3_dma_clk ), + .S02_AXI_ARESETN (~ddr3_dma_rst ), + .S02_AXI_AWID (dram_axi_awid [2]), + .S02_AXI_AWADDR (dram_axi_awaddr [2]), + .S02_AXI_AWLEN (dram_axi_awlen [2]), + .S02_AXI_AWSIZE (dram_axi_awsize [2]), + .S02_AXI_AWBURST (dram_axi_awburst [2]), + .S02_AXI_AWLOCK (dram_axi_awlock [2]), + .S02_AXI_AWCACHE (dram_axi_awcache [2]), + .S02_AXI_AWPROT (dram_axi_awprot [2]), + .S02_AXI_AWQOS (dram_axi_awqos [2]), + .S02_AXI_AWREGION (dram_axi_awregion[2]), + .S02_AXI_AWVALID (dram_axi_awvalid [2]), + .S02_AXI_AWREADY (dram_axi_awready [2]), + .S02_AXI_WDATA (dram_axi_wdata [2]), + .S02_AXI_WSTRB (dram_axi_wstrb [2]), + .S02_AXI_WLAST (dram_axi_wlast [2]), + .S02_AXI_WVALID (dram_axi_wvalid [2]), + .S02_AXI_WREADY (dram_axi_wready [2]), + .S02_AXI_BID (dram_axi_bid [2]), + .S02_AXI_BRESP (dram_axi_bresp [2]), + .S02_AXI_BVALID (dram_axi_bvalid [2]), + .S02_AXI_BREADY (dram_axi_bready [2]), + .S02_AXI_ARID (dram_axi_arid [2]), + .S02_AXI_ARADDR (dram_axi_araddr [2]), + .S02_AXI_ARLEN (dram_axi_arlen [2]), + .S02_AXI_ARSIZE (dram_axi_arsize [2]), + .S02_AXI_ARBURST (dram_axi_arburst [2]), + .S02_AXI_ARLOCK (dram_axi_arlock [2]), + .S02_AXI_ARCACHE (dram_axi_arcache [2]), + .S02_AXI_ARPROT (dram_axi_arprot [2]), + .S02_AXI_ARQOS (dram_axi_arqos [2]), + .S02_AXI_ARREGION (dram_axi_arregion[2]), + .S02_AXI_ARVALID (dram_axi_arvalid [2]), + .S02_AXI_ARREADY (dram_axi_arready [2]), + .S02_AXI_RID (dram_axi_rid [2]), + .S02_AXI_RDATA (dram_axi_rdata [2]), + .S02_AXI_RRESP (dram_axi_rresp [2]), + .S02_AXI_RLAST (dram_axi_rlast [2]), + .S02_AXI_RVALID (dram_axi_rvalid [2]), + .S02_AXI_RREADY (dram_axi_rready [2]), + // + .S03_AXI_ACLK (ddr3_dma_clk ), + .S03_AXI_ARESETN (~ddr3_dma_rst ), + .S03_AXI_AWID (dram_axi_awid [3]), + .S03_AXI_AWADDR (dram_axi_awaddr [3]), + .S03_AXI_AWLEN (dram_axi_awlen [3]), + .S03_AXI_AWSIZE (dram_axi_awsize [3]), + .S03_AXI_AWBURST (dram_axi_awburst [3]), + .S03_AXI_AWLOCK (dram_axi_awlock [3]), + .S03_AXI_AWCACHE (dram_axi_awcache [3]), + .S03_AXI_AWPROT (dram_axi_awprot [3]), + .S03_AXI_AWQOS (dram_axi_awqos [3]), + .S03_AXI_AWREGION (dram_axi_awregion[3]), + .S03_AXI_AWVALID (dram_axi_awvalid [3]), + .S03_AXI_AWREADY (dram_axi_awready [3]), + .S03_AXI_WDATA (dram_axi_wdata [3]), + .S03_AXI_WSTRB (dram_axi_wstrb [3]), + .S03_AXI_WLAST (dram_axi_wlast [3]), + .S03_AXI_WVALID (dram_axi_wvalid [3]), + .S03_AXI_WREADY (dram_axi_wready [3]), + .S03_AXI_BID (dram_axi_bid [3]), + .S03_AXI_BRESP (dram_axi_bresp [3]), + .S03_AXI_BVALID (dram_axi_bvalid [3]), + .S03_AXI_BREADY (dram_axi_bready [3]), + .S03_AXI_ARID (dram_axi_arid [3]), + .S03_AXI_ARADDR (dram_axi_araddr [3]), + .S03_AXI_ARLEN (dram_axi_arlen [3]), + .S03_AXI_ARSIZE (dram_axi_arsize [3]), + .S03_AXI_ARBURST (dram_axi_arburst [3]), + .S03_AXI_ARLOCK (dram_axi_arlock [3]), + .S03_AXI_ARCACHE (dram_axi_arcache [3]), + .S03_AXI_ARPROT (dram_axi_arprot [3]), + .S03_AXI_ARQOS (dram_axi_arqos [3]), + .S03_AXI_ARREGION (dram_axi_arregion[3]), + .S03_AXI_ARVALID (dram_axi_arvalid [3]), + .S03_AXI_ARREADY (dram_axi_arready [3]), + .S03_AXI_RID (dram_axi_rid [3]), + .S03_AXI_RDATA (dram_axi_rdata [3]), + .S03_AXI_RRESP (dram_axi_rresp [3]), + .S03_AXI_RLAST (dram_axi_rlast [3]), + .S03_AXI_RVALID (dram_axi_rvalid [3]), + .S03_AXI_RREADY (dram_axi_rready [3]), + // + .M00_AXI_ACLK (ddr3_axi_clk ), + .M00_AXI_ARESETN (~ddr3_axi_rst ), + .M00_AXI_AWID (ddr3_axi_awid ), + .M00_AXI_AWADDR (ddr3_axi_awaddr ), + .M00_AXI_AWLEN (ddr3_axi_awlen ), + .M00_AXI_AWSIZE (ddr3_axi_awsize ), + .M00_AXI_AWBURST (ddr3_axi_awburst ), + .M00_AXI_AWLOCK (ddr3_axi_awlock ), + .M00_AXI_AWCACHE (ddr3_axi_awcache ), + .M00_AXI_AWPROT (ddr3_axi_awprot ), + .M00_AXI_AWQOS (ddr3_axi_awqos ), + .M00_AXI_AWREGION ( ), + .M00_AXI_AWVALID (ddr3_axi_awvalid ), + .M00_AXI_AWREADY (ddr3_axi_awready ), + .M00_AXI_WDATA (ddr3_axi_wdata ), + .M00_AXI_WSTRB (ddr3_axi_wstrb ), + .M00_AXI_WLAST (ddr3_axi_wlast ), + .M00_AXI_WVALID (ddr3_axi_wvalid ), + .M00_AXI_WREADY (ddr3_axi_wready ), + .M00_AXI_BID (ddr3_axi_bid ), + .M00_AXI_BRESP (ddr3_axi_bresp ), + .M00_AXI_BVALID (ddr3_axi_bvalid ), + .M00_AXI_BREADY (ddr3_axi_bready ), + .M00_AXI_ARID (ddr3_axi_arid ), + .M00_AXI_ARADDR (ddr3_axi_araddr ), + .M00_AXI_ARLEN (ddr3_axi_arlen ), + .M00_AXI_ARSIZE (ddr3_axi_arsize ), + .M00_AXI_ARBURST (ddr3_axi_arburst ), + .M00_AXI_ARLOCK (ddr3_axi_arlock ), + .M00_AXI_ARCACHE (ddr3_axi_arcache ), + .M00_AXI_ARPROT (ddr3_axi_arprot ), + .M00_AXI_ARQOS (ddr3_axi_arqos ), + .M00_AXI_ARREGION ( ), + .M00_AXI_ARVALID (ddr3_axi_arvalid ), + .M00_AXI_ARREADY (ddr3_axi_arready ), + .M00_AXI_RID (ddr3_axi_rid ), + .M00_AXI_RDATA (ddr3_axi_rdata ), + .M00_AXI_RRESP (ddr3_axi_rresp ), + .M00_AXI_RLAST (ddr3_axi_rlast ), + .M00_AXI_RVALID (ddr3_axi_rvalid ), + .M00_AXI_RREADY (ddr3_axi_rready ) + ); + + + ///////////////////////////////////////////////////////////////////////////// + // + // DMA Transport Adapter + // + ///////////////////////////////////////////////////////////////////////////// + wire [63:0] dmao_tdata; + wire dmao_tlast; + wire dmao_tvalid; + wire dmao_tready; + + wire [63:0] dmai_tdata; + wire dmai_tlast; + wire dmai_tvalid; + wire dmai_tready; + + liberio_chdr64_adapter #( + .DMA_ID_WIDTH (4) + ) dma_xport_adapter ( + .clk (bus_clk), + .rst (bus_rst), + .device_id (device_id), + // From DMA engine to core + .s_dma_tdata (s_dma_tdata), + .s_dma_tuser (s_dma_tuser), + .s_dma_tlast (s_dma_tlast), + .s_dma_tvalid (s_dma_tvalid), + .s_dma_tready (s_dma_tready), + // From core to DMA engine + .m_dma_tdata (m_dma_tdata), + .m_dma_tuser (m_dma_tdest), + .m_dma_tlast (m_dma_tlast), + .m_dma_tvalid (m_dma_tvalid), + .m_dma_tready (m_dma_tready), + // CHDR buses + .s_chdr_tdata (dmao_tdata), + .s_chdr_tlast (dmao_tlast), + .s_chdr_tvalid (dmao_tvalid), + .s_chdr_tready (dmao_tready), + .m_chdr_tdata (dmai_tdata), + .m_chdr_tlast (dmai_tlast), + .m_chdr_tvalid (dmai_tvalid), + .m_chdr_tready (dmai_tready) + ); + + ///////////////////////////////////////////////////////////////////////////// + // + // Radio Daughter board and Front End Control + // + ///////////////////////////////////////////////////////////////////////////// + + // Radio Daughter board GPIO + wire [DB_GPIO_WIDTH-1:0] db_gpio_in[0:NUM_CHANNELS-1]; + wire [DB_GPIO_WIDTH-1:0] db_gpio_out[0:NUM_CHANNELS-1]; + wire [DB_GPIO_WIDTH-1:0] db_gpio_ddr[0:NUM_CHANNELS-1]; + wire [DB_GPIO_WIDTH-1:0] db_gpio_fab[0:NUM_CHANNELS-1]; + wire [31:0] radio_gpio_out[0:NUM_CHANNELS-1]; + wire [31:0] radio_gpio_ddr[0:NUM_CHANNELS-1]; + wire [31:0] radio_gpio_in[0:NUM_CHANNELS-1]; + wire [31:0] leds[0:NUM_CHANNELS-1]; + + // Daughter board I/O + wire rx_running[0:NUM_CHANNELS-1], tx_running[0:NUM_CHANNELS-1]; + wire [31:0] rx_int[0:NUM_CHANNELS-1], rx_data[0:NUM_CHANNELS-1], tx_int[0:NUM_CHANNELS-1], tx_data[0:NUM_CHANNELS-1]; + //wire rx_stb[0:NUM_CHANNELS-1], tx_stb[0:NUM_CHANNELS-1]; + wire db_fe_set_stb[0:NUM_CHANNELS-1]; + wire [7:0] db_fe_set_addr[0:NUM_CHANNELS-1]; + wire [31:0] db_fe_set_data[0:NUM_CHANNELS-1]; + wire db_fe_rb_stb[0:NUM_CHANNELS-1]; + wire [7:0] db_fe_rb_addr[0:NUM_CHANNELS-1]; + wire [63:0] db_fe_rb_data[0:NUM_CHANNELS-1]; + + wire [NUM_RADIOS-1:0] sync_out; + + genvar i; + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + assign rx_atr[i] = rx_running[i]; + assign tx_atr[i] = tx_running[i]; + end + endgenerate + + + //------------------------------------ + // Daughterboard Control + // ----------------------------------- + + localparam [7:0] SR_DB_BASE = 8'd160; + localparam [7:0] RB_DB_BASE = 8'd16; + + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: gen_db_control + db_control #( + .USE_SPI_CLK(0), + .SR_BASE(SR_DB_BASE), + .RB_BASE(RB_DB_BASE) + ) db_control_i ( + .clk(radio_clk), .reset(radio_rst), + .set_stb(db_fe_set_stb[i]), .set_addr(db_fe_set_addr[i]), .set_data(db_fe_set_data[i]), + .rb_stb(db_fe_rb_stb[i]), .rb_addr(db_fe_rb_addr[i]), .rb_data(db_fe_rb_data[i]), + .run_rx(rx_running[i]), .run_tx(tx_running[i]), + .misc_ins(32'h0), .misc_outs(), + .fp_gpio_in(radio_gpio_in[i]), .fp_gpio_out(radio_gpio_out[i]), .fp_gpio_ddr(radio_gpio_ddr[i]), .fp_gpio_fab(32'h0), + .db_gpio_in(db_gpio_in[i]), .db_gpio_out(db_gpio_out[i]), .db_gpio_ddr(db_gpio_ddr[i]), .db_gpio_fab(), + .leds(leds[i]), + .spi_clk(1'b0), .spi_rst(1'b0), .sen(), .sclk(), .mosi(), .miso(1'b0) + ); + end + endgenerate + + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: gen_gpio_control + // Radio Data + assign rx_data[i] = rx[32*i+31:32*i]; + assign tx[32*i+31:32*i] = tx_data[i]; + // GPIO + assign db_gpio_out_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH] = db_gpio_out[i]; + assign db_gpio_ddr_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH] = db_gpio_ddr[i]; + assign db_gpio_in[i] = db_gpio_in_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH]; + assign db_gpio_fab[i] = db_gpio_fab_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH]; + // LEDs + assign leds_flat[32*i+31:32*i] = leds[i]; + end + endgenerate + + ///////////////////////////////////////////////////////////////////////////// + // + // Front-panel GPIO + // + ///////////////////////////////////////////////////////////////////////////// + + wire [FP_GPIO_WIDTH-1:0] radio_gpio_in_sync; + wire [FP_GPIO_WIDTH-1:0] radio_gpio_src_out; + reg [FP_GPIO_WIDTH-1:0] radio_gpio_src_out_reg; + wire [FP_GPIO_WIDTH-1:0] radio_gpio_src_ddr; + reg [FP_GPIO_WIDTH-1:0] radio_gpio_src_ddr_reg = ~0; + + // Double-synchronize the inputs to the PS + synchronizer #( + .INITIAL_VAL(1'b0), .WIDTH(FP_GPIO_WIDTH) + ) ps_gpio_in_sync_i ( + .clk(bus_clk), .rst(1'b0), .in(fp_gpio_in), .out(ps_gpio_in) + ); + + // Double-synchronize the inputs to the radio + synchronizer #( + .INITIAL_VAL(1'b0), .WIDTH(FP_GPIO_WIDTH) + ) radio_gpio_in_sync_i ( + .clk(radio_clk), .rst(1'b0), .in(fp_gpio_in), .out(radio_gpio_in_sync) + ); + + // Map the double-synchronized inputs to all radio channels + generate + for (i=0; i<NUM_CHANNELS; i=i+1) begin: gen_fp_gpio_in_sync + assign radio_gpio_in[i][FP_GPIO_WIDTH-1:0] = radio_gpio_in_sync; + end + endgenerate + + // For each of the FP GPIO bits, implement four control muxes + generate + for (i=0; i<FP_GPIO_WIDTH; i=i+1) begin: gpio_muxing_gen + + // 1) Select which radio drives the output + assign radio_gpio_src_out[i] = radio_gpio_out[fp_gpio_src_reg[2*i+1:2*i]][i]; + always @ (posedge radio_clk) begin + if (radio_rst) begin + radio_gpio_src_out_reg <= 0; + end else begin + radio_gpio_src_out_reg <= radio_gpio_src_out; + end + end + + // 2) Select which radio drives the direction + assign radio_gpio_src_ddr[i] = radio_gpio_ddr[fp_gpio_src_reg[2*i+1:2*i]][i]; + always @ (posedge radio_clk) begin + if (radio_rst) begin + radio_gpio_src_ddr_reg <= ~0; + end else begin + radio_gpio_src_ddr_reg <= radio_gpio_src_ddr; + end + end + + // 3) Select if the radio or the ps drives the output + // + // The following implements a 2:1 mux in a LUT explicitly to avoid + // glitches that can be introduced by unexpected Vivado synthesis. + // + (* dont_touch = "TRUE" *) LUT3 #( + .INIT(8'hCA) // Specify LUT Contents. O = ~I2&I0 | I2&I1 + ) mux_out_i ( + .O(fp_gpio_out[i]), // LUT general output. Mux output + .I0(radio_gpio_src_out_reg[i]), // LUT input. Input 1 + .I1(ps_gpio_out[i]), // LUT input. Input 2 + .I2(fp_gpio_master_reg[i]) // LUT input. Select bit + ); + + // 4) Select if the radio or the PS drives the direction + // + (* dont_touch = "TRUE" *) LUT3 #( + .INIT(8'hC5) // Specify LUT Contents. O = ~I2&I0 | I2&~I1 + ) mux_ddr_i ( + .O(fp_gpio_tri[i]), // LUT general output. Mux output + .I0(radio_gpio_src_ddr_reg[i]), // LUT input. Input 1 + .I1(ps_gpio_tri[i]), // LUT input. Input 2 + .I2(fp_gpio_master_reg[i]) // LUT input. Select bit + ); + + end + endgenerate + + // Regport Mux for response + regport_resp_mux #( + .WIDTH (32), + .NUM_SLAVES (2) + ) reg_resp_mux_i ( + .clk(bus_clk), .reset(bus_rst), + .sla_rd_resp({reg_rd_resp_tk, reg_rd_resp_glob}), + .sla_rd_data({reg_rd_data_tk, reg_rd_data_glob}), + .mst_rd_resp(reg_rd_resp), .mst_rd_data(reg_rd_data) + ); + + // Timekeeper + wire [63:0] radio_time; + + timekeeper #( + .BASE_ADDR (REG_BASE_TIMEKEEPER), + .TIME_INCREMENT (1'b1) + ) timekeeper_i ( + .tb_clk (radio_clk), + .tb_rst (radio_rst), + .s_ctrlport_clk (bus_clk), + .s_ctrlport_req_wr (reg_wr_req), + .s_ctrlport_req_rd (reg_rd_req), + .s_ctrlport_req_addr (reg_wr_req ? reg_wr_addr: reg_rd_addr), + .s_ctrlport_req_data (reg_wr_data), + .s_ctrlport_resp_ack (reg_rd_resp_tk), + .s_ctrlport_resp_data (reg_rd_data_tk), + .sample_rx_stb (rx_stb[0]), + .pps (pps_radioclk), + .tb_timestamp (radio_time), + .tb_timestamp_last_pps (), + .tb_period_ns_q32 () + ); + + + ///////////////////////////////////////////////////////////////////////////// + // + // RFNoC Image Core + // + ///////////////////////////////////////////////////////////////////////////// + + // Unused memory AXI ports + for (i = 0; i < NUM_DRAM_FIFOS; i = i+1) begin : gen_unused_ram_signals + assign dram_axi_buser[i] = 4'b0; + assign dram_axi_ruser[i] = 4'b0; + end + + rfnoc_image_core #( + .PROTOVER(RFNOC_PROTOVER) + ) rfnoc_sandbox_i ( + .chdr_aclk (bus_clk ), + .ctrl_aclk (clk40 ), + .core_arst (bus_rst ), + .device_id (device_id ), + .radio_clk (radio_clk ), + .dram_clk (ddr3_dma_clk), + .m_ctrlport_req_wr (m_ctrlport_req_wr ), + .m_ctrlport_req_rd (m_ctrlport_req_rd ), + .m_ctrlport_req_addr (m_ctrlport_req_addr ), + .m_ctrlport_req_data (m_ctrlport_req_data ), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (m_ctrlport_req_has_time), + .m_ctrlport_req_time (m_ctrlport_req_time ), + .m_ctrlport_resp_ack (m_ctrlport_resp_ack ), + .m_ctrlport_resp_status (2'b0), + .m_ctrlport_resp_data (m_ctrlport_resp_data ), + .axi_rst (ddr3_dma_rst), + .m_axi_awid ({dram_axi_awid [1], dram_axi_awid [0]}), + .m_axi_awaddr ({dram_axi_awaddr [1], dram_axi_awaddr [0]}), + .m_axi_awlen ({dram_axi_awlen [1], dram_axi_awlen [0]}), + .m_axi_awsize ({dram_axi_awsize [1], dram_axi_awsize [0]}), + .m_axi_awburst ({dram_axi_awburst [1], dram_axi_awburst [0]}), + .m_axi_awlock ({dram_axi_awlock [1], dram_axi_awlock [0]}), + .m_axi_awcache ({dram_axi_awcache [1], dram_axi_awcache [0]}), + .m_axi_awprot ({dram_axi_awprot [1], dram_axi_awprot [0]}), + .m_axi_awqos ({dram_axi_awqos [1], dram_axi_awqos [0]}), + .m_axi_awregion ({dram_axi_awregion[1], dram_axi_awregion[0]}), + .m_axi_awuser ({dram_axi_awuser [1], dram_axi_awuser [0]}), + .m_axi_awvalid ({dram_axi_awvalid [1], dram_axi_awvalid [0]}), + .m_axi_awready ({dram_axi_awready [1], dram_axi_awready [0]}), + .m_axi_wdata ({dram_axi_wdata [1], dram_axi_wdata [0]}), + .m_axi_wstrb ({dram_axi_wstrb [1], dram_axi_wstrb [0]}), + .m_axi_wlast ({dram_axi_wlast [1], dram_axi_wlast [0]}), + .m_axi_wuser ({dram_axi_wuser [1], dram_axi_wuser [0]}), + .m_axi_wvalid ({dram_axi_wvalid [1], dram_axi_wvalid [0]}), + .m_axi_wready ({dram_axi_wready [1], dram_axi_wready [0]}), + .m_axi_bid ({dram_axi_bid [1], dram_axi_bid [0]}), + .m_axi_bresp ({dram_axi_bresp [1], dram_axi_bresp [0]}), + .m_axi_buser ({dram_axi_buser [1], dram_axi_buser [0]}), + .m_axi_bvalid ({dram_axi_bvalid [1], dram_axi_bvalid [0]}), + .m_axi_bready ({dram_axi_bready [1], dram_axi_bready [0]}), + .m_axi_arid ({dram_axi_arid [1], dram_axi_arid [0]}), + .m_axi_araddr ({dram_axi_araddr [1], dram_axi_araddr [0]}), + .m_axi_arlen ({dram_axi_arlen [1], dram_axi_arlen [0]}), + .m_axi_arsize ({dram_axi_arsize [1], dram_axi_arsize [0]}), + .m_axi_arburst ({dram_axi_arburst [1], dram_axi_arburst [0]}), + .m_axi_arlock ({dram_axi_arlock [1], dram_axi_arlock [0]}), + .m_axi_arcache ({dram_axi_arcache [1], dram_axi_arcache [0]}), + .m_axi_arprot ({dram_axi_arprot [1], dram_axi_arprot [0]}), + .m_axi_arqos ({dram_axi_arqos [1], dram_axi_arqos [0]}), + .m_axi_arregion ({dram_axi_arregion[1], dram_axi_arregion[0]}), + .m_axi_aruser ({dram_axi_aruser [1], dram_axi_aruser [0]}), + .m_axi_arvalid ({dram_axi_arvalid [1], dram_axi_arvalid [0]}), + .m_axi_arready ({dram_axi_arready [1], dram_axi_arready [0]}), + .m_axi_rid ({dram_axi_rid [1], dram_axi_rid [0]}), + .m_axi_rdata ({dram_axi_rdata [1], dram_axi_rdata [0]}), + .m_axi_rresp ({dram_axi_rresp [1], dram_axi_rresp [0]}), + .m_axi_rlast ({dram_axi_rlast [1], dram_axi_rlast [0]}), + .m_axi_ruser ({dram_axi_ruser [1], dram_axi_ruser [0]}), + .m_axi_rvalid ({dram_axi_rvalid [1], dram_axi_rvalid [0]}), + .m_axi_rready ({dram_axi_rready [1], dram_axi_rready [0]}), + .radio_time (radio_time ), + .radio_rx_stb ({rx_stb[1], rx_stb[0] }), + .radio_rx_data ({rx_data[1], rx_data[0] }), + .radio_rx_running ({rx_running[1], rx_running[0]}), + .radio_tx_stb ({tx_stb[1], tx_stb[0] }), + .radio_tx_data ({tx_data[1], tx_data[0] }), + .radio_tx_running ({tx_running[1], tx_running[0]}), + .s_eth_tdata (e2v_tdata ), + .s_eth_tlast (e2v_tlast ), + .s_eth_tvalid (e2v_tvalid), + .s_eth_tready (e2v_tready), + .m_eth_tdata (v2e_tdata ), + .m_eth_tlast (v2e_tlast ), + .m_eth_tvalid (v2e_tvalid), + .m_eth_tready (v2e_tready), + .s_dma_tdata (dmai_tdata), + .s_dma_tlast (dmai_tlast), + .s_dma_tvalid (dmai_tvalid), + .s_dma_tready (dmai_tready), + .m_dma_tdata (dmao_tdata), + .m_dma_tlast (dmao_tlast), + .m_dma_tvalid (dmao_tvalid), + .m_dma_tready (dmao_tready) + ); + + //--------------------------------------------------------------------------- + // Convert Control Port to Settings Bus + //--------------------------------------------------------------------------- + + ctrlport_to_settings_bus # ( + .NUM_PORTS (2), + .USE_TIME (1) + ) ctrlport_to_settings_bus_i ( + .ctrlport_clk (radio_clk), + .ctrlport_rst (radio_rst), + .s_ctrlport_req_wr (m_ctrlport_req_wr), + .s_ctrlport_req_rd (m_ctrlport_req_rd), + .s_ctrlport_req_addr (m_ctrlport_req_addr), + .s_ctrlport_req_data (m_ctrlport_req_data), + .s_ctrlport_req_has_time (m_ctrlport_req_has_time), + .s_ctrlport_req_time (m_ctrlport_req_time), + .s_ctrlport_resp_ack (m_ctrlport_resp_ack), + .s_ctrlport_resp_data (m_ctrlport_resp_data), + .set_data ({db_fe_set_data[1], db_fe_set_data[0]}), + .set_addr ({db_fe_set_addr[1], db_fe_set_addr[0]}), + .set_stb ({db_fe_set_stb[1], db_fe_set_stb[0] }), + .set_time (), + .set_has_time (), + .rb_stb ({db_fe_rb_stb[1], db_fe_rb_stb[0] }), + .rb_addr ({db_fe_rb_addr[1], db_fe_rb_addr[0] }), + .rb_data ({db_fe_rb_data[1], db_fe_rb_data[0] }), + .timestamp (radio_time) + ); + +endmodule //e320_core +`default_nettype wire + diff --git a/fpga/usrp3/top/e320/e320_dram.xdc b/fpga/usrp3/top/e320/e320_dram.xdc new file mode 100644 index 000000000..b8282ed63 --- /dev/null +++ b/fpga/usrp3/top/e320/e320_dram.xdc @@ -0,0 +1,27 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + +# Declare the 133 MHz DRAM subsystem clock. +create_generated_clock -name ddr3_ext_refclk -period 7.5 [get_ports sys_clk_p] + +# Rename IODELAY reference clock outputs from the MMCM inside MIG. +# These are based off the 200 MHz bus_clk. +create_generated_clock -name ddr3_iodelay_refclk \ + [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKOUT1}] +create_generated_clock -name ddr3_iodelay_refclk_fb \ + [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKFBOUT}] + +# Rename the UI clock appropriately. This clocks the slave AXI4 ports of the MIG as well +# as the AXI logic/interconnects in the remainder of the FPGA design. Should be 200 MHz. +create_generated_clock -name ddr3_ui_clk \ + [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT}] + +# Another UI clock at 300 MHz... not quite at 2x due to timing. +create_generated_clock -name ddr3_ui_clk_2x \ + [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0}] + +# Phase shifting clock for the MIG. Drives a few resets. +create_generated_clock -name ddr3_ps_clk \ + [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT5}] diff --git a/fpga/usrp3/top/e320/e320_rfnoc_image_core.v b/fpga/usrp3/top/e320/e320_rfnoc_image_core.v new file mode 100644 index 000000000..0811c9cc7 --- /dev/null +++ b/fpga/usrp3/top/e320/e320_rfnoc_image_core.v @@ -0,0 +1,994 @@ +// +// Copyright 2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +// Module: rfnoc_image_core (for e320) +// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) +// Re-running that tool will overwrite this file! +// File generated on: 2019-11-08T15:58:14.818480 +// Source: ./e320/e320_rfnoc_image_core.yml +// Source SHA256: a2a7b213b5764ef6cb83fed9d744a415bf8a7f18a955fbe1f867590f5d8c5142 + +module rfnoc_image_core #( + parameter [15:0] PROTOVER = {8'd1, 8'd0} +)( + // Clocks + input wire chdr_aclk, + input wire ctrl_aclk, + input wire core_arst, + input wire radio_clk, + input wire dram_clk, + // Basic + input wire [15:0] device_id, +//// IO ports ////////////////////////////////// +// ctrl_port + output wire [ 1-1:0] m_ctrlport_req_wr, + output wire [ 1-1:0] m_ctrlport_req_rd, + output wire [ 20-1:0] m_ctrlport_req_addr, + output wire [ 32-1:0] m_ctrlport_req_data, + output wire [ 4-1:0] m_ctrlport_req_byte_en, + output wire [ 1-1:0] m_ctrlport_req_has_time, + output wire [ 64-1:0] m_ctrlport_req_time, + input wire [ 1-1:0] m_ctrlport_resp_ack, + input wire [ 2-1:0] m_ctrlport_resp_status, + input wire [ 32-1:0] m_ctrlport_resp_data, +// time_keeper + input wire [ 64-1:0] radio_time, +// x300_radio + input wire [ 64-1:0] radio_rx_data, + input wire [ 2-1:0] radio_rx_stb, + output wire [ 2-1:0] radio_rx_running, + output wire [ 64-1:0] radio_tx_data, + input wire [ 2-1:0] radio_tx_stb, + output wire [ 2-1:0] radio_tx_running, +// dram + input wire [ 1-1:0] axi_rst, + output wire [ 2-1:0] m_axi_awid, + output wire [ 64-1:0] m_axi_awaddr, + output wire [ 16-1:0] m_axi_awlen, + output wire [ 6-1:0] m_axi_awsize, + output wire [ 4-1:0] m_axi_awburst, + output wire [ 2-1:0] m_axi_awlock, + output wire [ 8-1:0] m_axi_awcache, + output wire [ 6-1:0] m_axi_awprot, + output wire [ 8-1:0] m_axi_awqos, + output wire [ 8-1:0] m_axi_awregion, + output wire [ 2-1:0] m_axi_awuser, + output wire [ 2-1:0] m_axi_awvalid, + input wire [ 2-1:0] m_axi_awready, + output wire [128-1:0] m_axi_wdata, + output wire [ 16-1:0] m_axi_wstrb, + output wire [ 2-1:0] m_axi_wlast, + output wire [ 2-1:0] m_axi_wuser, + output wire [ 2-1:0] m_axi_wvalid, + input wire [ 2-1:0] m_axi_wready, + input wire [ 2-1:0] m_axi_bid, + input wire [ 4-1:0] m_axi_bresp, + input wire [ 2-1:0] m_axi_buser, + input wire [ 2-1:0] m_axi_bvalid, + output wire [ 2-1:0] m_axi_bready, + output wire [ 2-1:0] m_axi_arid, + output wire [ 64-1:0] m_axi_araddr, + output wire [ 16-1:0] m_axi_arlen, + output wire [ 6-1:0] m_axi_arsize, + output wire [ 4-1:0] m_axi_arburst, + output wire [ 2-1:0] m_axi_arlock, + output wire [ 8-1:0] m_axi_arcache, + output wire [ 6-1:0] m_axi_arprot, + output wire [ 8-1:0] m_axi_arqos, + output wire [ 8-1:0] m_axi_arregion, + output wire [ 2-1:0] m_axi_aruser, + output wire [ 2-1:0] m_axi_arvalid, + input wire [ 2-1:0] m_axi_arready, + input wire [ 2-1:0] m_axi_rid, + input wire [128-1:0] m_axi_rdata, + input wire [ 4-1:0] m_axi_rresp, + input wire [ 2-1:0] m_axi_rlast, + input wire [ 2-1:0] m_axi_ruser, + input wire [ 2-1:0] m_axi_rvalid, + output wire [ 2-1:0] m_axi_rready, + // Transport 0 (eth 10G) + input wire [64-1:0] s_eth_tdata, + input wire s_eth_tlast, + input wire s_eth_tvalid, + output wire s_eth_tready, + output wire [64-1:0] m_eth_tdata, + output wire m_eth_tlast, + output wire m_eth_tvalid, + input wire m_eth_tready, + // Transport 1 (dma dma) + input wire [64-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [64-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready +); + + localparam CHDR_W = 64; + localparam MTU = 10; + localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; + + wire rfnoc_chdr_clk, rfnoc_chdr_rst; + wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; + + // ---------------------------------------------------- + // CHDR Crossbar + // ---------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; + wire xb_to_ep0_tlast ; + wire xb_to_ep0_tvalid; + wire xb_to_ep0_tready; + wire [CHDR_W-1:0] ep0_to_xb_tdata ; + wire ep0_to_xb_tlast ; + wire ep0_to_xb_tvalid; + wire ep0_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep1_tdata ; + wire xb_to_ep1_tlast ; + wire xb_to_ep1_tvalid; + wire xb_to_ep1_tready; + wire [CHDR_W-1:0] ep1_to_xb_tdata ; + wire ep1_to_xb_tlast ; + wire ep1_to_xb_tvalid; + wire ep1_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep2_tdata ; + wire xb_to_ep2_tlast ; + wire xb_to_ep2_tvalid; + wire xb_to_ep2_tready; + wire [CHDR_W-1:0] ep2_to_xb_tdata ; + wire ep2_to_xb_tlast ; + wire ep2_to_xb_tvalid; + wire ep2_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep3_tdata ; + wire xb_to_ep3_tlast ; + wire xb_to_ep3_tvalid; + wire xb_to_ep3_tready; + wire [CHDR_W-1:0] ep3_to_xb_tdata ; + wire ep3_to_xb_tlast ; + wire ep3_to_xb_tvalid; + wire ep3_to_xb_tready; + + chdr_crossbar_nxn #( + .CHDR_W (CHDR_W), + .NPORTS (6), + .DEFAULT_PORT (0), + .MTU (MTU), + .ROUTE_TBL_SIZE (6), + .MUX_ALLOC ("ROUND-ROBIN"), + .OPTIMIZE ("AREA"), + .NPORTS_MGMT (2), + .EXT_RTCFG_PORT (0), + .PROTOVER (PROTOVER) + ) chdr_xb_i ( + .clk (rfnoc_chdr_clk), + .reset (rfnoc_chdr_rst), + .device_id (device_id), + .s_axis_tdata ({ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth_tdata}), + .s_axis_tlast ({ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth_tlast}), + .s_axis_tvalid ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth_tvalid}), + .s_axis_tready ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth_tready}), + .m_axis_tdata ({xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth_tdata}), + .m_axis_tlast ({xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth_tlast}), + .m_axis_tvalid ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth_tvalid}), + .m_axis_tready ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth_tready}), + .ext_rtcfg_stb (1'h0), + .ext_rtcfg_addr (16'h0), + .ext_rtcfg_data (32'h0), + .ext_rtcfg_ack () + ); + + // ---------------------------------------------------- + // Stream Endpoints + // ---------------------------------------------------- + + wire [CHDR_W-1:0] m_ep0_out0_tdata; + wire m_ep0_out0_tlast; + wire m_ep0_out0_tvalid; + wire m_ep0_out0_tready; + wire [CHDR_W-1:0] s_ep0_in0_tdata; + wire s_ep0_in0_tlast; + wire s_ep0_in0_tvalid; + wire s_ep0_in0_tready; + wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; + wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; + wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (1), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (0), + .CTRL_XBAR_PORT (1), + .INGRESS_BUFF_SIZE (15), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep0_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep0_tdata ), + .s_axis_chdr_tlast (xb_to_ep0_tlast ), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), + .s_axis_chdr_tready (xb_to_ep0_tready ), + .m_axis_chdr_tdata (ep0_to_xb_tdata ), + .m_axis_chdr_tlast (ep0_to_xb_tlast ), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), + .m_axis_chdr_tready (ep0_to_xb_tready ), + .s_axis_data_tdata ({s_ep0_in0_tdata}), + .s_axis_data_tlast ({s_ep0_in0_tlast}), + .s_axis_data_tvalid ({s_ep0_in0_tvalid}), + .s_axis_data_tready ({s_ep0_in0_tready}), + .m_axis_data_tdata ({m_ep0_out0_tdata}), + .m_axis_data_tlast ({m_ep0_out0_tlast}), + .m_axis_data_tvalid ({m_ep0_out0_tvalid}), + .m_axis_data_tready ({m_ep0_out0_tready}), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep0_ctrl_tready), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep0_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep1_out0_tdata; + wire m_ep1_out0_tlast; + wire m_ep1_out0_tvalid; + wire m_ep1_out0_tready; + wire [CHDR_W-1:0] s_ep1_in0_tdata; + wire s_ep1_in0_tlast; + wire s_ep1_in0_tvalid; + wire s_ep1_in0_tready; + wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; + wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; + wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (1), + .CTRL_XBAR_PORT (2), + .INGRESS_BUFF_SIZE (15), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep1_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep1_tdata ), + .s_axis_chdr_tlast (xb_to_ep1_tlast ), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), + .s_axis_chdr_tready (xb_to_ep1_tready ), + .m_axis_chdr_tdata (ep1_to_xb_tdata ), + .m_axis_chdr_tlast (ep1_to_xb_tlast ), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), + .m_axis_chdr_tready (ep1_to_xb_tready ), + .s_axis_data_tdata ({s_ep1_in0_tdata}), + .s_axis_data_tlast ({s_ep1_in0_tlast}), + .s_axis_data_tvalid ({s_ep1_in0_tvalid}), + .s_axis_data_tready ({s_ep1_in0_tready}), + .m_axis_data_tdata ({m_ep1_out0_tdata}), + .m_axis_data_tlast ({m_ep1_out0_tlast}), + .m_axis_data_tvalid ({m_ep1_out0_tvalid}), + .m_axis_data_tready ({m_ep1_out0_tready}), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep1_ctrl_tready), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep1_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep2_out0_tdata; + wire m_ep2_out0_tlast; + wire m_ep2_out0_tvalid; + wire m_ep2_out0_tready; + wire [CHDR_W-1:0] s_ep2_in0_tdata; + wire s_ep2_in0_tlast; + wire s_ep2_in0_tvalid; + wire s_ep2_in0_tready; + wire [31:0] m_ep2_ctrl_tdata , s_ep2_ctrl_tdata ; + wire m_ep2_ctrl_tlast , s_ep2_ctrl_tlast ; + wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; + wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (2), + .CTRL_XBAR_PORT (3), + .INGRESS_BUFF_SIZE (13), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep2_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep2_tdata ), + .s_axis_chdr_tlast (xb_to_ep2_tlast ), + .s_axis_chdr_tvalid (xb_to_ep2_tvalid ), + .s_axis_chdr_tready (xb_to_ep2_tready ), + .m_axis_chdr_tdata (ep2_to_xb_tdata ), + .m_axis_chdr_tlast (ep2_to_xb_tlast ), + .m_axis_chdr_tvalid (ep2_to_xb_tvalid ), + .m_axis_chdr_tready (ep2_to_xb_tready ), + .s_axis_data_tdata ({s_ep2_in0_tdata}), + .s_axis_data_tlast ({s_ep2_in0_tlast}), + .s_axis_data_tvalid ({s_ep2_in0_tvalid}), + .s_axis_data_tready ({s_ep2_in0_tready}), + .m_axis_data_tdata ({m_ep2_out0_tdata}), + .m_axis_data_tlast ({m_ep2_out0_tlast}), + .m_axis_data_tvalid ({m_ep2_out0_tvalid}), + .m_axis_data_tready ({m_ep2_out0_tready}), + .s_axis_ctrl_tdata (s_ep2_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep2_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep2_ctrl_tready), + .m_axis_ctrl_tdata (m_ep2_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep2_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep2_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep3_out0_tdata; + wire m_ep3_out0_tlast; + wire m_ep3_out0_tvalid; + wire m_ep3_out0_tready; + wire [CHDR_W-1:0] s_ep3_in0_tdata; + wire s_ep3_in0_tlast; + wire s_ep3_in0_tvalid; + wire s_ep3_in0_tready; + wire [31:0] m_ep3_ctrl_tdata , s_ep3_ctrl_tdata ; + wire m_ep3_ctrl_tlast , s_ep3_ctrl_tlast ; + wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; + wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (3), + .CTRL_XBAR_PORT (4), + .INGRESS_BUFF_SIZE (13), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep3_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep3_tdata ), + .s_axis_chdr_tlast (xb_to_ep3_tlast ), + .s_axis_chdr_tvalid (xb_to_ep3_tvalid ), + .s_axis_chdr_tready (xb_to_ep3_tready ), + .m_axis_chdr_tdata (ep3_to_xb_tdata ), + .m_axis_chdr_tlast (ep3_to_xb_tlast ), + .m_axis_chdr_tvalid (ep3_to_xb_tvalid ), + .m_axis_chdr_tready (ep3_to_xb_tready ), + .s_axis_data_tdata ({s_ep3_in0_tdata}), + .s_axis_data_tlast ({s_ep3_in0_tlast}), + .s_axis_data_tvalid ({s_ep3_in0_tvalid}), + .s_axis_data_tready ({s_ep3_in0_tready}), + .m_axis_data_tdata ({m_ep3_out0_tdata}), + .m_axis_data_tlast ({m_ep3_out0_tlast}), + .m_axis_data_tvalid ({m_ep3_out0_tvalid}), + .m_axis_data_tready ({m_ep3_out0_tready}), + .s_axis_ctrl_tdata (s_ep3_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep3_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep3_ctrl_tready), + .m_axis_ctrl_tdata (m_ep3_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep3_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep3_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + + + // ---------------------------------------------------- + // Control Crossbar + // ---------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; + wire m_core_ctrl_tlast , s_core_ctrl_tlast ; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_duc0_ctrl_tdata , s_duc0_ctrl_tdata ; + wire m_duc0_ctrl_tlast , s_duc0_ctrl_tlast ; + wire m_duc0_ctrl_tvalid, s_duc0_ctrl_tvalid; + wire m_duc0_ctrl_tready, s_duc0_ctrl_tready; + wire [31:0] m_ddc0_ctrl_tdata , s_ddc0_ctrl_tdata ; + wire m_ddc0_ctrl_tlast , s_ddc0_ctrl_tlast ; + wire m_ddc0_ctrl_tvalid, s_ddc0_ctrl_tvalid; + wire m_ddc0_ctrl_tready, s_ddc0_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; + wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_fifo0_ctrl_tdata , s_fifo0_ctrl_tdata ; + wire m_fifo0_ctrl_tlast , s_fifo0_ctrl_tlast ; + wire m_fifo0_ctrl_tvalid, s_fifo0_ctrl_tvalid; + wire m_fifo0_ctrl_tready, s_fifo0_ctrl_tready; + + axis_ctrl_crossbar_nxn #( + .WIDTH (32), + .NPORTS (6), + .TOPOLOGY ("TORUS"), + .INGRESS_BUFF_SIZE(5), + .ROUTER_BUFF_SIZE (5), + .ROUTING_ALLOC ("WORMHOLE"), + .SWITCH_ALLOC ("PRIO") + ) ctrl_xb_i ( + .clk (rfnoc_ctrl_clk), + .reset (rfnoc_ctrl_rst), + .s_axis_tdata ({m_fifo0_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), + .s_axis_tvalid ({m_fifo0_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), + .s_axis_tlast ({m_fifo0_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), + .s_axis_tready ({m_fifo0_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), + .m_axis_tdata ({s_fifo0_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), + .m_axis_tvalid ({s_fifo0_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), + .m_axis_tlast ({s_fifo0_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), + .m_axis_tready ({s_fifo0_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), + .deadlock_detected() + ); + + // ---------------------------------------------------- + // RFNoC Core Kernel + // ---------------------------------------------------- + wire [(512*4)-1:0] rfnoc_core_config, rfnoc_core_status; + + rfnoc_core_kernel #( + .PROTOVER (PROTOVER), + .DEVICE_TYPE (16'hE320), + .DEVICE_FAMILY ("7SERIES"), + .SAFE_START_CLKS (0), + .NUM_BLOCKS (4), + .NUM_STREAM_ENDPOINTS(4), + .NUM_ENDPOINTS_CTRL (1), + .NUM_TRANSPORTS (2), + .NUM_EDGES (12), + .CHDR_XBAR_PRESENT (1), + .EDGE_TBL_FILE (EDGE_TBL_FILE) + ) core_kernel_i ( + .chdr_aclk (chdr_aclk), + .chdr_aclk_locked (1'b1), + .ctrl_aclk (ctrl_aclk), + .ctrl_aclk_locked (1'b1), + .core_arst (core_arst), + .core_chdr_clk (rfnoc_chdr_clk), + .core_chdr_rst (rfnoc_chdr_rst), + .core_ctrl_clk (rfnoc_ctrl_clk), + .core_ctrl_rst (rfnoc_ctrl_rst), + .s_axis_ctrl_tdata (s_core_ctrl_tdata ), + .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), + .s_axis_ctrl_tready (s_core_ctrl_tready), + .m_axis_ctrl_tdata (m_core_ctrl_tdata ), + .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), + .m_axis_ctrl_tready (m_core_ctrl_tready), + .device_id (device_id), + .rfnoc_core_config (rfnoc_core_config), + .rfnoc_core_status (rfnoc_core_status) + ); + + // ---------------------------------------------------- + // Blocks + // ---------------------------------------------------- + + // ---------------------------------------------------- + // duc0 + // ---------------------------------------------------- + wire duc0_ce_clk; + wire [CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ; + wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ; + wire s_duc0_in_1_tvalid, s_duc0_in_0_tvalid; + wire s_duc0_in_1_tready, s_duc0_in_0_tready; + wire [CHDR_W-1:0] m_duc0_out_1_tdata , m_duc0_out_0_tdata ; + wire m_duc0_out_1_tlast , m_duc0_out_0_tlast ; + wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid; + wire m_duc0_out_1_tready, m_duc0_out_0_tready; + + + rfnoc_block_duc #( + .THIS_PORTID(2), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .NUM_HB(3), + .CIC_MAX_INTERP(255), + .MTU(MTU) + ) b_duc0_0 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(duc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + + + .s_rfnoc_chdr_tdata ({s_duc0_in_1_tdata , s_duc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc0_in_1_tlast , s_duc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_duc0_in_1_tvalid, s_duc0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_duc0_in_1_tready, s_duc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc0_out_1_tdata , m_duc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc0_out_1_tlast , m_duc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_duc0_out_1_tvalid, m_duc0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_duc0_out_1_tready, m_duc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_duc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_duc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_duc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_duc0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // ddc0 + // ---------------------------------------------------- + wire ddc0_ce_clk; + wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; + wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; + wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid; + wire s_ddc0_in_1_tready, s_ddc0_in_0_tready; + wire [CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ; + wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ; + wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; + wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; + + + rfnoc_block_ddc #( + .THIS_PORTID(3), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .NUM_HB(3), + .CIC_MAX_DECIM(255), + .MTU(MTU) + ) b_ddc0_1 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(ddc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + + + .s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_ddc0_in_1_tready, s_ddc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc0_out_1_tdata , m_ddc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc0_out_1_tlast , m_ddc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_ddc0_out_1_tready, m_ddc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_ddc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_ddc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_ddc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_ddc0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // radio0 + // ---------------------------------------------------- + wire radio0_radio_clk; + wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; + wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; + wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; + wire s_radio0_in_1_tready, s_radio0_in_0_tready; + wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; + wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; + wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; + wire m_radio0_out_1_tready, m_radio0_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio0_m_ctrlport_req_wr; + wire [ 1-1:0] radio0_m_ctrlport_req_rd; + wire [ 20-1:0] radio0_m_ctrlport_req_addr; + wire [ 32-1:0] radio0_m_ctrlport_req_data; + wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio0_m_ctrlport_req_has_time; + wire [ 64-1:0] radio0_m_ctrlport_req_time; + wire [ 1-1:0] radio0_m_ctrlport_resp_ack; + wire [ 2-1:0] radio0_m_ctrlport_resp_status; + wire [ 32-1:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio0_radio_time; + // x300_radio + wire [ 64-1:0] radio0_radio_rx_data; + wire [ 2-1:0] radio0_radio_rx_stb; + wire [ 2-1:0] radio0_radio_rx_running; + wire [ 64-1:0] radio0_radio_tx_data; + wire [ 2-1:0] radio0_radio_tx_stb; + wire [ 2-1:0] radio0_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(4), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .MTU(MTU) + ) b_radio0_2 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), + .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), + + .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), + .radio_time(radio0_radio_time), + .radio_rx_data(radio0_radio_rx_data), + .radio_rx_stb(radio0_radio_rx_stb), + .radio_rx_running(radio0_radio_rx_running), + .radio_tx_data(radio0_radio_tx_data), + .radio_tx_stb(radio0_radio_tx_stb), + .radio_tx_running(radio0_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // fifo0 + // ---------------------------------------------------- + wire fifo0_mem_clk; + wire [CHDR_W-1:0] s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ; + wire s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ; + wire s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid; + wire s_fifo0_in_1_tready, s_fifo0_in_0_tready; + wire [CHDR_W-1:0] m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ; + wire m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ; + wire m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid; + wire m_fifo0_out_1_tready, m_fifo0_out_0_tready; + + // axi_ram + wire [ 1-1:0] fifo0_axi_rst; + wire [ 2-1:0] fifo0_m_axi_awid; + wire [ 64-1:0] fifo0_m_axi_awaddr; + wire [ 16-1:0] fifo0_m_axi_awlen; + wire [ 6-1:0] fifo0_m_axi_awsize; + wire [ 4-1:0] fifo0_m_axi_awburst; + wire [ 2-1:0] fifo0_m_axi_awlock; + wire [ 8-1:0] fifo0_m_axi_awcache; + wire [ 6-1:0] fifo0_m_axi_awprot; + wire [ 8-1:0] fifo0_m_axi_awqos; + wire [ 8-1:0] fifo0_m_axi_awregion; + wire [ 2-1:0] fifo0_m_axi_awuser; + wire [ 2-1:0] fifo0_m_axi_awvalid; + wire [ 2-1:0] fifo0_m_axi_awready; + wire [128-1:0] fifo0_m_axi_wdata; + wire [ 16-1:0] fifo0_m_axi_wstrb; + wire [ 2-1:0] fifo0_m_axi_wlast; + wire [ 2-1:0] fifo0_m_axi_wuser; + wire [ 2-1:0] fifo0_m_axi_wvalid; + wire [ 2-1:0] fifo0_m_axi_wready; + wire [ 2-1:0] fifo0_m_axi_bid; + wire [ 4-1:0] fifo0_m_axi_bresp; + wire [ 2-1:0] fifo0_m_axi_buser; + wire [ 2-1:0] fifo0_m_axi_bvalid; + wire [ 2-1:0] fifo0_m_axi_bready; + wire [ 2-1:0] fifo0_m_axi_arid; + wire [ 64-1:0] fifo0_m_axi_araddr; + wire [ 16-1:0] fifo0_m_axi_arlen; + wire [ 6-1:0] fifo0_m_axi_arsize; + wire [ 4-1:0] fifo0_m_axi_arburst; + wire [ 2-1:0] fifo0_m_axi_arlock; + wire [ 8-1:0] fifo0_m_axi_arcache; + wire [ 6-1:0] fifo0_m_axi_arprot; + wire [ 8-1:0] fifo0_m_axi_arqos; + wire [ 8-1:0] fifo0_m_axi_arregion; + wire [ 2-1:0] fifo0_m_axi_aruser; + wire [ 2-1:0] fifo0_m_axi_arvalid; + wire [ 2-1:0] fifo0_m_axi_arready; + wire [ 2-1:0] fifo0_m_axi_rid; + wire [128-1:0] fifo0_m_axi_rdata; + wire [ 4-1:0] fifo0_m_axi_rresp; + wire [ 2-1:0] fifo0_m_axi_rlast; + wire [ 2-1:0] fifo0_m_axi_ruser; + wire [ 2-1:0] fifo0_m_axi_rvalid; + wire [ 2-1:0] fifo0_m_axi_rready; + + rfnoc_block_axi_ram_fifo #( + .THIS_PORTID(5), + .CHDR_W(CHDR_W), + .MEM_ADDR_W(31), + .MEM_DATA_W(64), + .MEM_CLK_RATE(300e6), + .FIFO_ADDR_BASE({31'h02000000, 31'h00000000}), + .FIFO_ADDR_MASK({31'h01FFFFFF, 31'h01FFFFFF}), + .NUM_PORTS(2), + .MTU(MTU) + ) b_fifo0_3 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .mem_clk(fifo0_mem_clk), + .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), + .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), + + .axi_rst(fifo0_axi_rst), + .m_axi_awid(fifo0_m_axi_awid), + .m_axi_awaddr(fifo0_m_axi_awaddr), + .m_axi_awlen(fifo0_m_axi_awlen), + .m_axi_awsize(fifo0_m_axi_awsize), + .m_axi_awburst(fifo0_m_axi_awburst), + .m_axi_awlock(fifo0_m_axi_awlock), + .m_axi_awcache(fifo0_m_axi_awcache), + .m_axi_awprot(fifo0_m_axi_awprot), + .m_axi_awqos(fifo0_m_axi_awqos), + .m_axi_awregion(fifo0_m_axi_awregion), + .m_axi_awuser(fifo0_m_axi_awuser), + .m_axi_awvalid(fifo0_m_axi_awvalid), + .m_axi_awready(fifo0_m_axi_awready), + .m_axi_wdata(fifo0_m_axi_wdata), + .m_axi_wstrb(fifo0_m_axi_wstrb), + .m_axi_wlast(fifo0_m_axi_wlast), + .m_axi_wuser(fifo0_m_axi_wuser), + .m_axi_wvalid(fifo0_m_axi_wvalid), + .m_axi_wready(fifo0_m_axi_wready), + .m_axi_bid(fifo0_m_axi_bid), + .m_axi_bresp(fifo0_m_axi_bresp), + .m_axi_buser(fifo0_m_axi_buser), + .m_axi_bvalid(fifo0_m_axi_bvalid), + .m_axi_bready(fifo0_m_axi_bready), + .m_axi_arid(fifo0_m_axi_arid), + .m_axi_araddr(fifo0_m_axi_araddr), + .m_axi_arlen(fifo0_m_axi_arlen), + .m_axi_arsize(fifo0_m_axi_arsize), + .m_axi_arburst(fifo0_m_axi_arburst), + .m_axi_arlock(fifo0_m_axi_arlock), + .m_axi_arcache(fifo0_m_axi_arcache), + .m_axi_arprot(fifo0_m_axi_arprot), + .m_axi_arqos(fifo0_m_axi_arqos), + .m_axi_arregion(fifo0_m_axi_arregion), + .m_axi_aruser(fifo0_m_axi_aruser), + .m_axi_arvalid(fifo0_m_axi_arvalid), + .m_axi_arready(fifo0_m_axi_arready), + .m_axi_rid(fifo0_m_axi_rid), + .m_axi_rdata(fifo0_m_axi_rdata), + .m_axi_rresp(fifo0_m_axi_rresp), + .m_axi_rlast(fifo0_m_axi_rlast), + .m_axi_ruser(fifo0_m_axi_ruser), + .m_axi_rvalid(fifo0_m_axi_rvalid), + .m_axi_rready(fifo0_m_axi_rready), + + .s_rfnoc_chdr_tdata ({s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_fifo0_in_1_tready, s_fifo0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_fifo0_out_1_tdata , m_fifo0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_fifo0_out_1_tready, m_fifo0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_fifo0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_fifo0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_fifo0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_fifo0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // Static Router + // ---------------------------------------------------- + assign s_duc0_in_0_tdata = m_ep0_out0_tdata ; + assign s_duc0_in_0_tlast = m_ep0_out0_tlast ; + assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; + assign m_ep0_out0_tready = s_duc0_in_0_tready; + + assign s_radio0_in_0_tdata = m_duc0_out_0_tdata ; + assign s_radio0_in_0_tlast = m_duc0_out_0_tlast ; + assign s_radio0_in_0_tvalid = m_duc0_out_0_tvalid; + assign m_duc0_out_0_tready = s_radio0_in_0_tready; + + assign s_ddc0_in_0_tdata = m_radio0_out_0_tdata ; + assign s_ddc0_in_0_tlast = m_radio0_out_0_tlast ; + assign s_ddc0_in_0_tvalid = m_radio0_out_0_tvalid; + assign m_radio0_out_0_tready = s_ddc0_in_0_tready; + + assign s_ep0_in0_tdata = m_ddc0_out_0_tdata ; + assign s_ep0_in0_tlast = m_ddc0_out_0_tlast ; + assign s_ep0_in0_tvalid = m_ddc0_out_0_tvalid; + assign m_ddc0_out_0_tready = s_ep0_in0_tready; + + assign s_duc0_in_1_tdata = m_ep1_out0_tdata ; + assign s_duc0_in_1_tlast = m_ep1_out0_tlast ; + assign s_duc0_in_1_tvalid = m_ep1_out0_tvalid; + assign m_ep1_out0_tready = s_duc0_in_1_tready; + + assign s_radio0_in_1_tdata = m_duc0_out_1_tdata ; + assign s_radio0_in_1_tlast = m_duc0_out_1_tlast ; + assign s_radio0_in_1_tvalid = m_duc0_out_1_tvalid; + assign m_duc0_out_1_tready = s_radio0_in_1_tready; + + assign s_ddc0_in_1_tdata = m_radio0_out_1_tdata ; + assign s_ddc0_in_1_tlast = m_radio0_out_1_tlast ; + assign s_ddc0_in_1_tvalid = m_radio0_out_1_tvalid; + assign m_radio0_out_1_tready = s_ddc0_in_1_tready; + + assign s_ep1_in0_tdata = m_ddc0_out_1_tdata ; + assign s_ep1_in0_tlast = m_ddc0_out_1_tlast ; + assign s_ep1_in0_tvalid = m_ddc0_out_1_tvalid; + assign m_ddc0_out_1_tready = s_ep1_in0_tready; + + assign s_fifo0_in_0_tdata = m_ep2_out0_tdata ; + assign s_fifo0_in_0_tlast = m_ep2_out0_tlast ; + assign s_fifo0_in_0_tvalid = m_ep2_out0_tvalid; + assign m_ep2_out0_tready = s_fifo0_in_0_tready; + + assign s_ep2_in0_tdata = m_fifo0_out_0_tdata ; + assign s_ep2_in0_tlast = m_fifo0_out_0_tlast ; + assign s_ep2_in0_tvalid = m_fifo0_out_0_tvalid; + assign m_fifo0_out_0_tready = s_ep2_in0_tready; + + assign s_fifo0_in_1_tdata = m_ep3_out0_tdata ; + assign s_fifo0_in_1_tlast = m_ep3_out0_tlast ; + assign s_fifo0_in_1_tvalid = m_ep3_out0_tvalid; + assign m_ep3_out0_tready = s_fifo0_in_1_tready; + + assign s_ep3_in0_tdata = m_fifo0_out_1_tdata ; + assign s_ep3_in0_tlast = m_fifo0_out_1_tlast ; + assign s_ep3_in0_tvalid = m_fifo0_out_1_tvalid; + assign m_fifo0_out_1_tready = s_ep3_in0_tready; + + + // ---------------------------------------------------- + // Unused Ports + // ---------------------------------------------------- + + // ---------------------------------------------------- + // Clock Domains + // ---------------------------------------------------- + assign radio0_radio_clk = radio_clk; + assign duc0_ce_clk = rfnoc_chdr_clk; + assign ddc0_ce_clk = rfnoc_chdr_clk; + assign fifo0_mem_clk = dram_clk; + + + // ---------------------------------------------------- + // IO Port Connection + // ---------------------------------------------------- + // Master/Slave Connections: + assign m_ctrlport_req_wr = radio0_m_ctrlport_req_wr; + assign m_ctrlport_req_rd = radio0_m_ctrlport_req_rd; + assign m_ctrlport_req_addr = radio0_m_ctrlport_req_addr; + assign m_ctrlport_req_data = radio0_m_ctrlport_req_data; + assign m_ctrlport_req_byte_en = radio0_m_ctrlport_req_byte_en; + assign m_ctrlport_req_has_time = radio0_m_ctrlport_req_has_time; + assign m_ctrlport_req_time = radio0_m_ctrlport_req_time; + assign radio0_m_ctrlport_resp_ack = m_ctrlport_resp_ack; + assign radio0_m_ctrlport_resp_status = m_ctrlport_resp_status; + assign radio0_m_ctrlport_resp_data = m_ctrlport_resp_data; + + assign radio0_radio_rx_data = radio_rx_data; + assign radio0_radio_rx_stb = radio_rx_stb; + assign radio_rx_running = radio0_radio_rx_running; + assign radio_tx_data = radio0_radio_tx_data; + assign radio0_radio_tx_stb = radio_tx_stb; + assign radio_tx_running = radio0_radio_tx_running; + + assign fifo0_axi_rst = axi_rst; + assign m_axi_awid = fifo0_m_axi_awid; + assign m_axi_awaddr = fifo0_m_axi_awaddr; + assign m_axi_awlen = fifo0_m_axi_awlen; + assign m_axi_awsize = fifo0_m_axi_awsize; + assign m_axi_awburst = fifo0_m_axi_awburst; + assign m_axi_awlock = fifo0_m_axi_awlock; + assign m_axi_awcache = fifo0_m_axi_awcache; + assign m_axi_awprot = fifo0_m_axi_awprot; + assign m_axi_awqos = fifo0_m_axi_awqos; + assign m_axi_awregion = fifo0_m_axi_awregion; + assign m_axi_awuser = fifo0_m_axi_awuser; + assign m_axi_awvalid = fifo0_m_axi_awvalid; + assign fifo0_m_axi_awready = m_axi_awready; + assign m_axi_wdata = fifo0_m_axi_wdata; + assign m_axi_wstrb = fifo0_m_axi_wstrb; + assign m_axi_wlast = fifo0_m_axi_wlast; + assign m_axi_wuser = fifo0_m_axi_wuser; + assign m_axi_wvalid = fifo0_m_axi_wvalid; + assign fifo0_m_axi_wready = m_axi_wready; + assign fifo0_m_axi_bid = m_axi_bid; + assign fifo0_m_axi_bresp = m_axi_bresp; + assign fifo0_m_axi_buser = m_axi_buser; + assign fifo0_m_axi_bvalid = m_axi_bvalid; + assign m_axi_bready = fifo0_m_axi_bready; + assign m_axi_arid = fifo0_m_axi_arid; + assign m_axi_araddr = fifo0_m_axi_araddr; + assign m_axi_arlen = fifo0_m_axi_arlen; + assign m_axi_arsize = fifo0_m_axi_arsize; + assign m_axi_arburst = fifo0_m_axi_arburst; + assign m_axi_arlock = fifo0_m_axi_arlock; + assign m_axi_arcache = fifo0_m_axi_arcache; + assign m_axi_arprot = fifo0_m_axi_arprot; + assign m_axi_arqos = fifo0_m_axi_arqos; + assign m_axi_arregion = fifo0_m_axi_arregion; + assign m_axi_aruser = fifo0_m_axi_aruser; + assign m_axi_arvalid = fifo0_m_axi_arvalid; + assign fifo0_m_axi_arready = m_axi_arready; + assign fifo0_m_axi_rid = m_axi_rid; + assign fifo0_m_axi_rdata = m_axi_rdata; + assign fifo0_m_axi_rresp = m_axi_rresp; + assign fifo0_m_axi_rlast = m_axi_rlast; + assign fifo0_m_axi_ruser = m_axi_ruser; + assign fifo0_m_axi_rvalid = m_axi_rvalid; + assign m_axi_rready = fifo0_m_axi_rready; + + // Broadcaster/Listener Connections: + assign radio0_radio_time = radio_time; + +endmodule diff --git a/fpga/usrp3/top/e320/e320_rfnoc_image_core.yml b/fpga/usrp3/top/e320/e320_rfnoc_image_core.yml new file mode 100644 index 000000000..626bba4a7 --- /dev/null +++ b/fpga/usrp3/top/e320/e320_rfnoc_image_core.yml @@ -0,0 +1,101 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers +license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +version: 1.0 # File version +rfnoc_version: 1.0 # RFNoC protocol version +chdr_width: 64 # Bit width of the CHDR bus for this image +device: 'e320' +default_target: 'E320_HG' + + + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + ep1: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + ep2: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 8192 # Ingress buffer size for data + ep3: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 8192 # Ingress buffer size for data + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + duc0: # NoC block name + block_desc: 'duc.yml' # Block device descriptor file + parameters: + NUM_PORTS: 2 + ddc0: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 2 + radio0: + block_desc: 'radio_2x64.yml' + fifo0: + block_desc: 'axi_ram_fifo_2x64.yml' + parameters: + # These parameters correspond to the memory interface on the E320 + MEM_ADDR_W: 31 + MEM_DATA_W: 64 + MEM_CLK_RATE: "300e6" + # Create two non-overlapping 32 MB buffers by default + FIFO_ADDR_BASE: "{31'h02000000, 31'h00000000}" + FIFO_ADDR_MASK: "{31'h01FFFFFF, 31'h01FFFFFF}" + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + # ep0 to radio0(0) - RF0 TX + - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 } + - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 } + # radio0(0) to ep0 - RF0 RX + - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 } + - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 } + # ep1 to radio0(1) - RF1 TX + - { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 } + - { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 } + # radio0(1) to ep1 - RF1 RX + - { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 } + - { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 } + # ep2 to fifo0(0) + - { srcblk: ep2, srcport: out0, dstblk: fifo0, dstport: in_0 } + - { srcblk: fifo0, srcport: out_0, dstblk: ep2, dstport: in0 } + # ep3 to fifo0(1) + - { srcblk: ep3, srcport: out0, dstblk: fifo0, dstport: in_1 } + - { srcblk: fifo0, srcport: out_1, dstblk: ep3, dstport: in0 } + # BSP Connections + - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrl_port } + - { srcblk: _device_, srcport: x300_radio, dstblk: radio0, dstport: x300_radio } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } + - { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram } + +# A list of all clock domain connections in design +# ------------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc0, dstport: ce } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc0, dstport: ce } + - { srcblk: _device_, srcport: dram, dstblk: fifo0, dstport: mem } diff --git a/fpga/usrp3/top/e320/e320_static_router.hex b/fpga/usrp3/top/e320/e320_static_router.hex new file mode 100644 index 000000000..6217eaf68 --- /dev/null +++ b/fpga/usrp3/top/e320/e320_static_router.hex @@ -0,0 +1,13 @@ +0000000C +00400140 +014001c0 +01c00180 +01800040 +00800141 +014101c1 +01c10181 +01810080 +00c00200 +020000c0 +01000201 +02010100 diff --git a/fpga/usrp3/top/e320/ip/Makefile.inc b/fpga/usrp3/top/e320/ip/Makefile.inc new file mode 100644 index 000000000..eb4d83cf3 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/Makefile.inc @@ -0,0 +1,81 @@ +# +# Copyright 2014 Ettus Research +# + +#include $(IP_DIR)/axi4_dualport_sram/Makefile.inc +include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc +include $(IP_DIR)/axi64_8k_2clk_fifo/Makefile.inc +include $(IP_DIR)/axi_intercon_4x64_256_bd/Makefile.inc +include $(IP_DIR)/ddr3_32bit/Makefile.inc +include $(IP_DIR)/fifo_4k_2clk/Makefile.inc +include $(IP_DIR)/fifo_short_2clk/Makefile.inc +#include $(IP_DIR)/input_sample_fifo/Makefile.inc +include $(IP_DIR)/one_gig_eth_pcs_pma/Makefile.inc +#include $(IP_DIR)/misc_clock_gen/Makefile.inc +include $(IP_DIR)/ten_gig_eth_pcs_pma/Makefile.inc +include $(IP_DIR)/aurora_64b66b_pcs_pma/Makefile.inc +#include $(IP_DIR)/axi3_to_axi4lite_protocol_converter/Makefile.inc +#include $(IP_DIR)/axis_fifo_to_axi4lite/Makefile.inc +include $(IP_DIR)/axi_eth_dma/Makefile.inc +#include $(IP_DIR)/axi4_to_axi3_protocol_converter_32/Makefile.inc +#include $(IP_DIR)/axi4_to_axi3_protocol_converter_64/Makefile.inc +include $(IP_DIR)/e320_ps_bd/Makefile.inc + +BD_SRCS = \ +$(IP_AXI_INTERCON_4X64_256_BD_SRCS) \ +$(IP_E320_PS_BD_SRCS) + +IP_XCI_SRCS = \ +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +$(IP_AXI64_4K_2CLK_FIFO_SRCS) \ +$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) \ +$(IP_AURORA_64B66B_PCS_PMA_SRCS) \ +$(IP_AXI64_8K_2CLK_FIFO_SRCS) \ +$(IP_AXI_ETH_DMA_SRCS) \ +$(IP_FIFO_4K_2CLK_SRCS) \ +#$(IP_AXI4_BRAM_SRCS) \ +#$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_SRCS) \ +#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_SRCS) \ +#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_SRCS) \ +#$(IP_AXIS_FIFO_TO_AXI4LITE_SRCS) \ +#$(IP_MISC_CLOCK_GEN_SRCS) \ + +IP_DRAM_XCI_SRCS = \ +$(IP_DDR3_32BIT_SRCS) + +## Currently unused +## $(IP_INPUT_SAMPLE_FIFO_SRCS) \ + +IP_CODEGEN_SRCS = \ +$(TEN_GIGE_PHY_SRCS) \ +$(ONE_GIGE_PHY_SRCS) + +IP_SYNTH_OUTPUTS = \ +$(IP_TEN_GIG_ETH_PCS_PMA_OUTS) \ +$(IP_FIFO_SHORT_2CLK_OUTS) \ +$(IP_AXI64_4K_2CLK_FIFO_OUTS) \ +$(IP_ONE_GIG_ETH_PCS_PMA_OUTS) \ +$(IP_AXI64_8K_2CLK_FIFO_OUTS) \ +$(IP_AURORA_64B66B_PCS_PMA_OUTS) \ +$(IP_AXI_ETH_DMA_OUTS) \ +$(IP_FIFO_4K_2CLK_OUTS) \ +#$(IP_AXI4_BRAM_OUTS) \ +#$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_OUTS) \ +#$(IP_AXI_INTERCONNECT_OUTS) \ +#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_OUTS) \ +#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_OUTS) \ +#$(IP_AXIS_FIFO_TO_AXI4LITE_OUTS) \ + +BD_OUTPUTS = \ +$(IP_AXI_INTERCON_4X64_256_BD_OUTS) \ +$(IP_E320_PS_BD_OUTS) + +# Currently unused +# $(IP_INPUT_SAMPLE_FIFO_OUTS) \ +# $(IP_AXI_INTERCON_4X64_128_OUTS) \ + +ip: $(IP_SYNTH_OUTPUTS) $(IP_CODEGEN_SRCS) $(BD_OUTPUTS) + +.PHONY: ip + diff --git a/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/Makefile.inc b/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/Makefile.inc new file mode 100644 index 000000000..f7dffb541 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/Makefile.inc @@ -0,0 +1,30 @@ +# +# Copyright 2018 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +AURORA_PHY_SRCS = \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_phy_x1.v \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_axis_mac.v \ +$(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS) + +IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma_ex/, \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_clock_module.v \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_gt_common_wrapper.v \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_support_reset_logic.v \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_support.v \ +imports/aurora_64b66b_pcs_pma_cdc_sync_exdes.v \ +imports/aurora_64b66b_pcs_pma_example_axi_to_ll.v \ +imports/aurora_64b66b_pcs_pma_example_ll_to_axi.v \ +) + +IP_AURORA_64B66B_PCS_PMA_SRCS = $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci + +IP_AURORA_64B66B_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/, \ +aurora_64b66b_pcs_pma.xci.out \ +) + +$(IP_AURORA_64B66B_PCS_PMA_SRCS) $(IP_AURORA_64B66B_PCS_PMA_OUTS) $(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS): $(IP_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci + $(call BUILD_VIVADO_IP,aurora_64b66b_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) + diff --git a/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci b/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci new file mode 100644 index 000000000..87c64d2d1 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci @@ -0,0 +1,1774 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>aurora_64b66b_pcs_pma</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="aurora_64b66b" spirit:version="12.0"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.HAS_BRESP">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.HAS_RRESP">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.HAS_WSTRB">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DIFF_REFCLK1.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DIFF_REFCLK1.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DIFF_REFCLK2.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DIFF_REFCLK2.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DIFF_REFCLK3.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DIFF_REFCLK3.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DIFF_REFCLK4.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DIFF_REFCLK4.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DIFF_REFCLK5.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DIFF_REFCLK5.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD10_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD10_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD10_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD10_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD10_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD10_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD10_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD10_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD10_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD10_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD10_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD10_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD11_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD11_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD11_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD11_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD11_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD11_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD11_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD11_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD11_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD11_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD11_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD11_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD12_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD12_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD12_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD12_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD12_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD12_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD12_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD12_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD12_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD12_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD12_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD12_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD1_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD1_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD1_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD1_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD1_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD1_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD1_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD1_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD1_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD1_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD1_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD1_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD2_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD2_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD2_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD2_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD2_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD2_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD2_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD2_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD2_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD2_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD2_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD2_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD3_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD3_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD3_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD3_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD3_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD3_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD3_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD3_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD3_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD3_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD3_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD3_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD4_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD4_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD4_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD4_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD4_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD4_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD4_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD4_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD4_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD4_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD4_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD4_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD5_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD5_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD5_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD5_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD5_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD5_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD5_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD5_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD5_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD5_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD5_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD5_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD6_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD6_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD6_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD6_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD6_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD6_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD6_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD6_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD6_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD6_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD6_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD6_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD7_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD7_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD7_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD7_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD7_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD7_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD7_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD7_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD7_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD7_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD7_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD7_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD8_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD8_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD8_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD8_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD8_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD8_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD8_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD8_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD8_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD8_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD8_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD8_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD9_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD9_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD9_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD9_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD9_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD9_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD9_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD9_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD9_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD9_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD9_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLCLK_QUAD9_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD10_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD10_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD10_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD10_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD10_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD10_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD10_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD10_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD10_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD10_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD10_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD10_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD11_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD11_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD11_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD11_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD11_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD11_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD11_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD11_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD11_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD11_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD11_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD11_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD12_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD12_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD12_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD12_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD12_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD12_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD12_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD12_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD12_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD12_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD12_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD12_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD1_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD1_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD1_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD1_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD1_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD1_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD1_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD1_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD1_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD1_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD1_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD1_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD2_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD2_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD2_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD2_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD2_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD2_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD2_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD2_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD2_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD2_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD2_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD2_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD3_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD3_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD3_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD3_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD3_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD3_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD3_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD3_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD3_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD3_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD3_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD3_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD4_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD4_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD4_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD4_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD4_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD4_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD4_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD4_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD4_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD4_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD4_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD4_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD5_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD5_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD5_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD5_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD5_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD5_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD5_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD5_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD5_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD5_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD5_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD5_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD6_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD6_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD6_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD6_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD6_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD6_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD6_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD6_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD6_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD6_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD6_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD6_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD7_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD7_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD7_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD7_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD7_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD7_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD7_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD7_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD7_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD7_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD7_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD7_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD8_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD8_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD8_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD8_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD8_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD8_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD8_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD8_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD8_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD8_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD8_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD8_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD9_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD9_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD9_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD9_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD9_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD9_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD9_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD9_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD9_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD9_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD9_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_QPLLREFCLK_QUAD9_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK3_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK3_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK3_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK3_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK3_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK4_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK4_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK4_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK4_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK4_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK5_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK5_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK5_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK5_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK5_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RXUSRCLK_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RXUSRCLK_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RXUSRCLK_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RXUSRCLK_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RXUSRCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RXUSRCLK_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_DIFF_CLK.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_DIFF_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LINK_RESET_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK1_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK1_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK1_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK1_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK1_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK1_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK2_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK2_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK2_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK2_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK2_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK2_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK3_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK3_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK3_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK3_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK3_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK3_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK4_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK4_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK4_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK4_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK4_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK4_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK5_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK5_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK5_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK5_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK5_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK5_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET2FC.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET2FG.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET_PB.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE0.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE0.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE0.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE0.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE0.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE1.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE1.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE1.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE1.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE1.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE10.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE10.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE10.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE10.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE10.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE11.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE11.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE11.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE11.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE11.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE12.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE12.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE12.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE12.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE12.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE13.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE13.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE13.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE13.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE13.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE14.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE14.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE14.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE14.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE14.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE15.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE15.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE15.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE15.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE15.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE2.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE2.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE2.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE2.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE2.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE3.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE3.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE3.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE3.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE3.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE4.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE4.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE4.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE4.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE4.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE5.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE5.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE5.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE5.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE5.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE6.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE6.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE6.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE6.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE6.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE7.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE7.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE7.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE7.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE7.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE8.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE8.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE8.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE8.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE8.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE9.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE9.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE9.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE9.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE9.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_RESET_PB.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SYS_RESET_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_RESET_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE0.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE0.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE0.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE0.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE0.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE1.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE1.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE1.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE1.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE1.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE10.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE10.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE10.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE10.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE10.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE11.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE11.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE11.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE11.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE11.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE12.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE12.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE12.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE12.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE12.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE13.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE13.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE13.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE13.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE13.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE14.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE14.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE14.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE14.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE14.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE15.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE15.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE15.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE15.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE15.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE2.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE2.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE2.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE2.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE2.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE3.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE3.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE3.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE3.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE3.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE4.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE4.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE4.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE4.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE4.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE5.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE5.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE5.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE5.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE5.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE6.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE6.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE6.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE6.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE6.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE7.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE7.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE7.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE7.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE7.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE8.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE8.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE8.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE8.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE8.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE9.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE9.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE9.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE9.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE9.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_RESET_PB.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_SYS_RESET_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_1.FREQ_HZ">156.25</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_1.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_2.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.TDATA_NUM_BYTES">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.HAS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.TDATA_NUM_BYTES">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOCCPORT_ENABLE">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REFCLK2_LOC_N">BL7</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REFCLK2_LOC_P">BL8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REFCLK2_SOURCE">none</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REFCLK3_LOC_N">BL7</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REFCLK3_LOC_P">BL8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REFCLK3_SOURCE">none</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REFCLK4_LOC_N">BL7</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REFCLK4_LOC_P">BL8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REFCLK4_SOURCE">none</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REFCLK5_LOC_N">BL7</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REFCLK5_LOC_P">BL8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REFCLK5_SOURCE">none</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REFCLK_LOC_N">BL7</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REFCLK_LOC_P">BL8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REFCLK_SOURCE">none</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_START_LANE">X0Y0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_START_QUAD">X0Y0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_active_transceiverquads">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PLL_TYPE">QPLL</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RX_MASTER_CHANNEL">none</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SINGLEEND_GTREFCLK">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SINGLEEND_INITCLK">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TX_MASTER_CHANNEL">none</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USDRPADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_aurora_lanes">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_column_used">left</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_cpll_fbdiv">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_cpll_fbdiv_45">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_cpll_refclk_div">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_example_simulation">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_clock_1">GTXQ0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_clock_2">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_clock_3">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_clock_4">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_clock_5">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_1">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_10">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_11">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_12">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_13">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_14">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_15">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_16">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_17">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_18">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_19">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_2">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_20">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_21">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_22">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_23">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_24">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_25">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_26">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_27">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_28">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_29">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_3">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_30">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_31">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_32">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_33">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_34">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_35">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_36">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_37">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_38">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_39">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_4">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_40">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_41">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_42">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_43">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_44">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_45">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_46">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_47">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_48">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_5">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_6">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_7">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_8">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_9">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_type">gtx</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gtwiz_out">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_init_clk">78.125</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_lane_width">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_line_rate">10312.5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_nfc">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_nfc_mode">IMM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_no_gts_quad1">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_no_gts_quad2">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_no_gts_quad3">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_no_gts_quad4">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_no_gts_quad5">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_qpll">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_qpll_fbdiv_ratio">66</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_qpll_refclk_div">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_refclk_frequency">156250.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_remwidht">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_rxoutdiv">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_simplex">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_simplex_mode">TX</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_stream">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_txoutdiv">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_ucolumn_used">right</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_ufc">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_use_byteswap">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_use_chipscope">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_user_interface">axi4_stream</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_user_k">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xdevice">xc7z045</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xpackage">ffg900</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xspeedgrade">-3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.cc_refclk_frequency">156.250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.channel_enable">X0Y0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.component_name">aurora_64b66b_pcs_pma</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.crc_mode">NONE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.dataflow_config">Duplex</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.dmonitoroutval">7</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.drp_freq">78.125</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.drp_mode">AXI4_LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.flow_mode">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtquadcnt">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ins_loss_nyq">20</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.interface_mode">Streaming</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.is_7series">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.is_8series">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.is_board">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.is_versal">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.rx_coupling">AC</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.rx_eq_mode">AUTO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.rx_ppm_offset">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.rx_termination">PROGRAMMABLE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.rx_termination_prog_value">800</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.supportlevel">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.transceivercontrol">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE">X0Y0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AURORA_LANES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_COLUMN_USED">left</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DOCCPORT_ENABLE">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXAMPLE_SIMULATION">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GTWIZ_OUT">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_CLOCK_1">GTXQ0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_CLOCK_2">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_CLOCK_3">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_CLOCK_4">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_CLOCK_5">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_1">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_10">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_11">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_12">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_13">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_14">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_15">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_16">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_17">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_18">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_19">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_2">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_20">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_21">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_22">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_23">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_24">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_25">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_26">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_27">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_28">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_29">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_3">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_30">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_31">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_32">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_33">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_34">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_35">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_36">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_37">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_38">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_39">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_4">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_40">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_41">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_42">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_43">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_44">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_45">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_46">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_47">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_48">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_5">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_6">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_7">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_8">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_9">X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_TYPE">gtx</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INIT_CLK">78.125</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LINE_RATE">10.3125</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PLL_TYPE">LCPLL</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_REFCLK2_SOURCE">none</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_REFCLK3_SOURCE">none</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_REFCLK4_SOURCE">none</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_REFCLK5_SOURCE">none</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_REFCLK_FREQUENCY">156.250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_REFCLK_FREQUENCY_ACTUAL">156.250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_REFCLK_FREQUENCY_VERSAL">156.250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_REFCLK_SOURCE">none</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_START_LANE">X0Y0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_START_QUAD">X0Y0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UCOLUMN_USED">right</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USER_K">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_BYTESWAP">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_CHIPSCOPE">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_active_transceiverquads">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">aurora_64b66b_pcs_pma</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRP_FREQ">78.125</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INS_LOSS_NYQ">20</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_COUPLING">AC</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_EQ_MODE">AUTO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_PPM_OFFSET">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_TERMINATION">PROGRAMMABLE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_TERMINATION_PROG_VALUE">800</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SINGLEEND_GTREFCLK">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SINGLEEND_INITCLK">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SupportLevel">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverControl">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.crc_mode">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dataflow_config">Duplex</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.drp_mode">AXI4_LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.flow_mode">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.interface_mode">Streaming</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z045</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_0.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_1.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_10.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_11.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_12.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_13.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_14.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_15.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_2.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_3.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_4.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_5.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_6.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_7.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_8.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_DRP_IF_9.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.HAS_TKEEP" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.HAS_TLAST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXIS_TX.TUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.HAS_TREADY" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.TUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.HAS_TKEEP" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.HAS_TLAST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.TUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.HAS_TREADY" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.TUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.TUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.HAS_TKEEP" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.HAS_TLAST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.HAS_TREADY" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.TUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.HAS_TKEEP" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.HAS_TLAST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.USER_K_S_AXIS_TX.TUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INIT_CLK" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LINE_RATE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_BYTESWAP" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DRP_FREQ" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.interface_mode" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v b/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v new file mode 100644 index 000000000..39ed52f8c --- /dev/null +++ b/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v @@ -0,0 +1,329 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_axis_mac #( + parameter PHY_ENDIANNESS = "LITTLE", //{"LITTLE, "BIG"} + parameter PACKET_MODE = 0, + parameter MAX_PACKET_SIZE = 512, + parameter BIST_ENABLED = 1 +) ( + // Clocks and resets + input phy_clk, + input phy_rst, + input sys_clk, + input sys_rst, + input clear, + // PHY TX Interface (Synchronous to phy_clk) + output [63:0] phy_m_axis_tdata, + output phy_m_axis_tvalid, + input phy_m_axis_tready, + // PHY RX Interface (Synchronous to phy_clk) + input [63:0] phy_s_axis_tdata, + input phy_s_axis_tvalid, + // User TX Interface (Synchronous to sys_clk) + input [63:0] s_axis_tdata, + input s_axis_tlast, + input s_axis_tvalid, + output s_axis_tready, + // User RX Interface (Synchronous to sys_clk) + output [63:0] m_axis_tdata, + output m_axis_tlast, + output m_axis_tvalid, + input m_axis_tready, + // PHY Status Inputs (Synchronous to phy_clk) + input channel_up, + input hard_err, + input soft_err, + // Status and Error Outputs (Synchronous to sys_clk) + output [31:0] overruns, + output [31:0] soft_errors, + output reg [31:0] checksum_errors, + output critical_err, + // BIST Interface (Synchronous to sys_clk) + input bist_gen_en, + input [5:0] bist_gen_rate, + input bist_checker_en, + input bist_loopback_en, + output reg bist_checker_locked, + output reg [47:0] bist_checker_samps, + output reg [47:0] bist_checker_errors +); + + // ---------------------------------------------- + // Resets, Clears, Clock crossings + // ---------------------------------------------- + + wire phy_s_axis_tready; // Internal only. The PHY has no backpressure signal. + + // Stay idle if the PHY is not up or if it experiences a fatal error + wire clear_sysclk, clear_phyclk; + synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_phyclk_i ( + .clk(phy_clk), .rst(1'b0 /* no reset */), .in((~channel_up) | hard_err | clear), .out(clear_phyclk)); + synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_sysclk_i ( + .clk(sys_clk), .rst(1'b0 /* no reset */), .in(clear_phyclk), .out(clear_sysclk)); + + // ---------------------------------------------- + // Counters + // ---------------------------------------------- + + reg [31:0] overruns_reg; + reg [31:0] soft_errors_reg; + + // Counter for recoverable errors. For reporting only. + always @(posedge phy_clk) + if (phy_rst | clear_phyclk) + soft_errors_reg <= 32'd0; + else if (soft_err) + soft_errors_reg <= soft_errors_reg + 32'd1; + + // Tag an overrun if the FIFO is full. Samples will get dropped + always @(posedge phy_clk) + if (phy_rst | clear_phyclk) + overruns_reg <= 32'd0; + else if (phy_s_axis_tvalid & ~phy_s_axis_tready) + overruns_reg <= overruns_reg + 32'd1; + + wire [7:0] dummy0; + fifo_short_2clk status_counters_2clk_i ( + .rst(phy_rst), + .wr_clk(phy_clk), .din({8'h00, soft_errors_reg, overruns_reg}), .wr_en(1'b1), .full(), .wr_data_count(), + .rd_clk(sys_clk), .dout({dummy0, soft_errors, overruns}), .rd_en(1'b1), .empty(), .rd_data_count() + ); + + // ---------------------------------------------- + // BIST Wires + // ---------------------------------------------- + + wire [63:0] bist_o_tdata; + wire bist_o_tvalid, bist_o_tready; + wire [63:0] bist_i_tdata; + wire bist_i_tvalid, bist_i_tready; + wire [63:0] loopback_tdata; + wire loopback_tvalid, loopback_tready; + reg bist_gen_en_reg = 1'b0, bist_checker_en_reg = 1'b0, bist_loopback_en_reg = 1'b0; + reg [5:0] bist_gen_rate_reg = 'd0; + + generate if (BIST_ENABLED == 1) begin + // Pipeline control signals + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk) begin + bist_gen_en_reg <= 1'b0; + bist_checker_en_reg <= 1'b0; + bist_loopback_en_reg <= 1'b0; + bist_gen_rate_reg <= 'd0; + end else begin + bist_gen_en_reg <= bist_gen_en; + bist_checker_en_reg <= bist_checker_en; + bist_loopback_en_reg <= bist_loopback_en; + bist_gen_rate_reg <= bist_gen_rate; + end + end + end endgenerate + // ---------------------------------------------- + // RX Data Path + // ---------------------------------------------- + + wire [63:0] i_raw_tdata; + wire i_raw_tvalid, i_raw_tready; + + wire [63:0] i_pip_tdata; + wire i_pip_tvalid, i_pip_tready; + + wire [63:0] i_pkt_tdata; + wire i_pkt_tlast, i_pkt_tvalid, i_pkt_tready; + + wire [63:0] i_gt_tdata; + wire i_gt_tlast, i_gt_tvalid, i_gt_tready; + + wire checksum_err; + + wire [63:0] phy_s_axis_tdata_endian, phy_m_axis_tdata_endian; + + generate if (PHY_ENDIANNESS == "BIG") begin + assign phy_s_axis_tdata_endian = { + phy_s_axis_tdata[7:0], phy_s_axis_tdata[15:8], phy_s_axis_tdata[23:16], phy_s_axis_tdata[31:24], + phy_s_axis_tdata[39:32], phy_s_axis_tdata[47:40], phy_s_axis_tdata[55:48], phy_s_axis_tdata[63:56] + }; + assign phy_m_axis_tdata = { + phy_m_axis_tdata_endian[7:0], phy_m_axis_tdata_endian[15:8], phy_m_axis_tdata_endian[23:16], phy_m_axis_tdata_endian[31:24], + phy_m_axis_tdata_endian[39:32], phy_m_axis_tdata_endian[47:40], phy_m_axis_tdata_endian[55:48], phy_m_axis_tdata_endian[63:56] + }; + end else begin + assign phy_s_axis_tdata_endian = phy_s_axis_tdata; + assign phy_m_axis_tdata = phy_m_axis_tdata_endian; + end endgenerate + + // Large FIFO must be able to run input side at 64b@156MHz to sustain 10Gb Rx. + axi64_4k_2clk_fifo ingress_fifo_i ( + .s_aresetn(~phy_rst), .s_aclk(phy_clk), + .s_axis_tdata(phy_s_axis_tdata_endian), .s_axis_tlast(phy_s_axis_tvalid), .s_axis_tuser(4'h0), + .s_axis_tvalid(phy_s_axis_tvalid), .s_axis_tready(phy_s_axis_tready), .axis_wr_data_count(), + .m_aclk(sys_clk), + .m_axis_tdata(i_raw_tdata), .m_axis_tlast(), .m_axis_tuser(), + .m_axis_tvalid(i_raw_tvalid), .m_axis_tready(i_raw_tready), .axis_rd_data_count() + ); + + // AXI-Flop to ease timing + axi_fifo_flop #(.WIDTH(64)) input_pipe_i0 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(i_raw_tdata), .i_tvalid(i_raw_tvalid), .i_tready(i_raw_tready), + .o_tdata(i_pip_tdata), .o_tvalid(i_pip_tvalid), + .o_tready(bist_checker_en_reg ? bist_i_tready : (bist_loopback_en_reg ? loopback_tready : i_pip_tready)), + .space(), .occupied() + ); + + assign bist_i_tdata = i_pip_tdata; + assign bist_i_tvalid = i_pip_tvalid & bist_checker_en_reg; + + assign loopback_tdata = i_pip_tdata; + assign loopback_tvalid = i_pip_tvalid & bist_loopback_en_reg; + + axi_strip_preamble #(.WIDTH(64), .MAX_PKT_SIZE(MAX_PACKET_SIZE)) axi_strip_preamble_i ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(i_pip_tdata), .i_tvalid(i_pip_tvalid & ~bist_checker_en_reg & ~bist_loopback_en_reg), .i_tready(i_pip_tready), + .o_tdata(i_gt_tdata), .o_tlast(i_gt_tlast), .o_tvalid(i_gt_tvalid), .o_tready(i_gt_tready), + .crc_err(checksum_err), .pkt_dropped(), .crit_error(critical_err) + ); + + axi_fifo_flop #(.WIDTH(65)) input_pipe_i1 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata({i_gt_tlast, i_gt_tdata}), .i_tvalid(i_gt_tvalid), .i_tready(i_gt_tready), + .o_tdata({m_axis_tlast, m_axis_tdata}), .o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready), + .space(), .occupied() + ); + + always @(posedge sys_clk) + if (sys_rst | clear_sysclk) + checksum_errors <= 32'd0; + else if (checksum_err) + checksum_errors <= checksum_errors + 32'd1; + + // ---------------------------------------------- + // TX Data Path + // ---------------------------------------------- + + wire [63:0] o_pkt_tdata; + wire o_pkt_tlast, o_pkt_tvalid, o_pkt_tready; + + wire [63:0] o_pip_tdata; + wire o_pip_tvalid, o_pip_tready; + + wire [63:0] o_raw_tdata; + wire o_raw_tvalid, o_raw_tready; + + // AXI-Flop to ease timing + axi_fifo_flop #(.WIDTH(65)) output_pipe_i0 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata({s_axis_tlast, s_axis_tdata}), .i_tvalid(s_axis_tvalid), .i_tready(s_axis_tready), + .o_tdata({o_pkt_tlast, o_pkt_tdata}), .o_tvalid(o_pkt_tvalid), .o_tready(o_pkt_tready), + .space(), .occupied() + ); + + // Insert preamble and EOP + axi_add_preamble #(.WIDTH(64)) axi_add_preamble_i ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(o_pkt_tdata), .i_tlast(o_pkt_tlast), .i_tvalid(o_pkt_tvalid), .i_tready(o_pkt_tready), + .o_tdata(o_pip_tdata), .o_tvalid(o_pip_tvalid), .o_tready(o_pip_tready & ~bist_gen_en_reg & ~bist_loopback_en_reg) + ); + + // AXI-Flop to ease timing + axi_fifo_flop #(.WIDTH(64)) output_pipe_i1 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(bist_gen_en_reg ? bist_o_tdata : (bist_loopback_en_reg ? loopback_tdata : o_pip_tdata)), + .i_tvalid(bist_gen_en_reg ? bist_o_tvalid : (bist_loopback_en_reg ? loopback_tvalid : o_pip_tvalid)), + .i_tready(o_pip_tready), + .o_tdata(o_raw_tdata), .o_tvalid(o_raw_tvalid), .o_tready(o_raw_tready), + .space(), .occupied() + ); + + assign bist_o_tready = o_pip_tready; + assign loopback_tready = o_pip_tready; + + // Egress FIFO + axi64_4k_2clk_fifo egress_fifo_i ( + .s_aresetn(~phy_rst), .s_aclk(sys_clk), + .s_axis_tdata(o_raw_tdata), .s_axis_tlast(o_raw_tvalid), .s_axis_tuser(4'h0), + .s_axis_tvalid(o_raw_tvalid), .s_axis_tready(o_raw_tready), .axis_wr_data_count(), + .m_aclk(phy_clk), + .m_axis_tdata(phy_m_axis_tdata_endian), .m_axis_tlast(), .m_axis_tuser(), + .m_axis_tvalid(phy_m_axis_tvalid), .m_axis_tready(phy_m_axis_tready), .axis_rd_data_count() + ); + + // ------------------------------------------------- + // BIST: Generator and checker for a LFSR polynomial + // ------------------------------------------------- + localparam LFSR_LEN = 32; + localparam LFSR_SEED = {LFSR_LEN{1'b1}}; + + function [LFSR_LEN-1:0] compute_lfsr_next; + input [LFSR_LEN-1:0] current; + // Maximal length polynomial: x^32 + x^22 + x^2 + x^1 + 1 + compute_lfsr_next = {current[30:0], current[31]^current[21]^current[1]^current[0]}; + endfunction + + function [63:0] lfsr_to_axis; + input [LFSR_LEN-1:0] lfsr; + lfsr_to_axis = {~lfsr, lfsr}; + endfunction + + function [LFSR_LEN-1:0] axis_to_lfsr; + input [63:0] axis; + axis_to_lfsr = axis[LFSR_LEN-1:0]; + endfunction + + generate if (BIST_ENABLED == 1) begin + // Throttle outgoing LFSR to based on the specified rate + // BIST Throughput = sys_clk BW * (bist_gen_rate+1)/64 + reg [5:0] throttle_cnt; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk) + throttle_cnt <= 6'd0; + else if (bist_gen_en_reg) + throttle_cnt <= throttle_cnt + 6'd1; + end + // NOTE: This techinically violates AXIS spec (valid revocation) + assign bist_o_tvalid = bist_gen_en_reg && (throttle_cnt <= bist_gen_rate_reg); + + // Unsynchronized LFSR generator (for BIST output) + reg [LFSR_LEN-1:0] lfsr_gen = LFSR_SEED, lfsr_check = LFSR_SEED; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk | ~bist_gen_en_reg) + lfsr_gen <= LFSR_SEED; + else if (bist_o_tready & bist_o_tvalid) + lfsr_gen <= compute_lfsr_next(lfsr_gen); + end + assign bist_o_tdata = lfsr_to_axis(lfsr_gen); + + // Synchronized LFSR checker (for BIST input) + wire [LFSR_LEN-1:0] lfsr_next = compute_lfsr_next(lfsr_check);; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk | ~bist_checker_en_reg) begin + bist_checker_locked <= 1'b0; + lfsr_check <= LFSR_SEED; + end else if (bist_i_tvalid && bist_i_tready) begin + lfsr_check <= axis_to_lfsr(bist_i_tdata); + if (bist_i_tdata == lfsr_to_axis(LFSR_SEED)) + bist_checker_locked <= 1'b1; + end + end + + // LFSR checker + always @(posedge sys_clk) begin + if (bist_checker_locked) begin + if (bist_i_tvalid & bist_i_tready) begin + bist_checker_samps <= bist_checker_samps + 48'd1; + if (bist_i_tdata != lfsr_to_axis(lfsr_next)) begin + bist_checker_errors <= bist_checker_errors + 48'd1; + end + end + end else begin + bist_checker_samps <= 48'd0; + bist_checker_errors <= 48'd0; + end + end + assign bist_i_tready = 1'b1; + end endgenerate + +endmodule + diff --git a/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v b/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v new file mode 100644 index 000000000..c3fc89749 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v @@ -0,0 +1,370 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_phy_x1 #( + parameter SIMULATION = 0 +)( + // Clocks and Resets + input areset, + input refclk, + input init_clk, + output user_clk, + output user_rst, + // GTX Serial I/O + input rx_p, + input rx_n, + output tx_p, + output tx_n, + // AXI4-Stream TX Interface + input [63:0] s_axis_tdata, + input s_axis_tvalid, + output s_axis_tready, + // AXI4-Stream RX Interface + output [63:0] m_axis_tdata, + output m_axis_tvalid, + // AXI4-Lite Config Interface + input [31:0] s_axi_awaddr, + input [31:0] s_axi_araddr, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + input s_axi_awvalid, + input s_axi_rready, + output [31:0] s_axi_rdata, + output s_axi_awready, + output s_axi_wready, + output s_axi_bvalid, + output [1:0] s_axi_bresp, + output [1:0] s_axi_rresp, + input s_axi_bready, + output s_axi_arready, + output s_axi_rvalid, + input s_axi_arvalid, + input s_axi_wvalid, + // Status and Error Reporting Interface + output reg channel_up, + output reg hard_err, + output reg soft_err +); + + //-------------------------------------------------------------- + // Status and Error Signals + //-------------------------------------------------------------- + wire hard_err_i, soft_err_i, channel_up_i, lane_up_i; + always @(posedge user_clk) begin + hard_err <= hard_err_i; + soft_err <= soft_err_i; + channel_up <= channel_up_i && lane_up_i; + end + + //-------------------------------------------------------------- + // Reset and PMA Init Sequence + //-------------------------------------------------------------- + // Requirements from PG074: + // - It is expected that user_clock is stable when the reset_pb signal is applied. + // - During the board power-on sequence, both the pma_init and reset_pb signals are + // expected to be High. INIT_CLK and GT_REFCLK are expected to be stable during + // power-on for the proper functioning of the Aurora 64B/66B core. When both clocks are + // stable, pma_init is deasserted followed by the deassertion of reset_pb. + // - Normal Operation Reset Sequence: + // 1. Assert reset. Wait for a minimum time equal to 128*user_clk's time-period. + // 2. Assert pma_init. Keep pma_init and reset asserted for at least one second to prevent + // the transmission of CC characters and ensure that the remote agent detects a hot plug event. + // 3. Deassert pma_init. + // 4. Deassert reset_pb. + + localparam PWRON_PMA_INIT_CYC = 32'd1024; + localparam SYSRST_ASSERT_CYC = 32'd128; + localparam PMA_INIT_ASSERT_CYC_LOG2 = (SIMULATION == 1) ? 4 : 26; + localparam SYSRST_DEASSERT_CYC = 32'd20; + + wire reset_iclk, pma_init, reset_pb; + wire gt_pll_lock, gt_pll_lock_iclk, mmcm_locked, mmcm_locked_iclk; + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b1) ) input_rst_sync_i ( + .clk(init_clk), .rst(1'b0), .in(areset), .out(reset_iclk) + ); + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b0) ) gt_pll_lock_sync_i ( + .clk(init_clk), .rst(1'b0), .in(gt_pll_lock), .out(gt_pll_lock_iclk) + ); + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b0) ) mmcm_locked_sync_i ( + .clk(init_clk), .rst(1'b0), .in(mmcm_locked), .out(mmcm_locked_iclk) + ); + + localparam [2:0] RST_ST_PWRON_PMA_INIT = 3'd0; + localparam [2:0] RST_ST_PWRON_PMA_SYSRST = 3'd1; + localparam [2:0] RST_ST_IDLE = 3'd2; + localparam [2:0] RST_ST_SYSRST_PRE = 3'd3; + localparam [2:0] RST_ST_PMA_INIT = 3'd4; + localparam [2:0] RST_ST_SYSRST_POST = 3'd5; + + reg [2:0] rst_state = RST_ST_PWRON_PMA_INIT; + reg [31:0] rst_counter = PWRON_PMA_INIT_CYC; + + always @(posedge init_clk) begin + case (rst_state) + RST_ST_PWRON_PMA_INIT: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_PWRON_PMA_SYSRST; + rst_counter <= SYSRST_DEASSERT_CYC; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_PWRON_PMA_SYSRST: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_IDLE; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_IDLE: begin + if (reset_iclk) begin + rst_state <= RST_ST_SYSRST_PRE; + rst_counter <= SYSRST_ASSERT_CYC; + end + end + RST_ST_SYSRST_PRE: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_PMA_INIT; + rst_counter <= {{(32-PMA_INIT_ASSERT_CYC_LOG2){1'b0}}, {PMA_INIT_ASSERT_CYC_LOG2{1'b1}}}; + end else if (mmcm_locked_iclk) begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_PMA_INIT: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_SYSRST_POST; + rst_counter <= SYSRST_DEASSERT_CYC; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_SYSRST_POST: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_IDLE; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + endcase + end + + assign reset_pb = (rst_state != RST_ST_IDLE); + assign pma_init = (rst_state == RST_ST_PMA_INIT || rst_state == RST_ST_PWRON_PMA_INIT); + + //-------------------------------------------------------------- + // Clocking + //-------------------------------------------------------------- + + wire tx_out_clk, tx_out_clk_bufg; + wire sync_clk_i; + wire user_clk_i; + wire mmcm_fb_clk; + wire sync_clk; + + localparam MULT = 10; + localparam DIVIDE = 5; + localparam CLK_PERIOD = 3.103; + localparam OUT0_DIVIDE = 4; + localparam OUT1_DIVIDE = 2; + localparam OUT2_DIVIDE = 6; + localparam OUT3_DIVIDE = 8; + + MMCME2_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (DIVIDE), + .CLKFBOUT_MULT_F (MULT), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (OUT0_DIVIDE), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (CLK_PERIOD), + .CLKOUT1_DIVIDE (OUT1_DIVIDE), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKOUT2_DIVIDE (OUT2_DIVIDE), + .CLKOUT2_PHASE (0.000), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKOUT2_USE_FINE_PS ("FALSE"), + .CLKOUT3_DIVIDE (OUT3_DIVIDE), + .CLKOUT3_PHASE (0.000), + .CLKOUT3_DUTY_CYCLE (0.500), + .CLKOUT3_USE_FINE_PS ("FALSE"), + .REF_JITTER1 (0.010) + ) mmcm_adv_inst ( + .CLKFBOUT (mmcm_fb_clk), + .CLKFBOUTB (), + .CLKOUT0 (user_clk_i), + .CLKOUT0B (), + .CLKOUT1 (sync_clk_i), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + // Input clock control + .CLKFBIN (mmcm_fb_clk), + .CLKIN1 (tx_out_clk_bufg), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (mmcm_locked), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (!gt_pll_lock) + ); + + // BUFG for the feedback clock. The feedback signal is phase aligned to the input + // and must come from the CLK0 or CLK2X output of the PLL. In this case, we use + // the CLK0 output. + BUFG txout_clock_net_i ( + .I(tx_out_clk), + .O(tx_out_clk_bufg) + ); + BUFG user_clk_net_i ( + .I(user_clk_i), + .O(user_clk) + ); + BUFG sync_clock_net_i ( + .I(sync_clk_i), + .O(sync_clk) + ); + + //-------------------------------------------------------------- + // GT Common + //-------------------------------------------------------------- + + wire gt_qpllclk_quad1_i; + wire gt_qpllrefclk_quad1_i; + wire gt_to_common_qpllreset_i; + wire gt_qpllrefclklost_i; + wire gt_qplllock_i; + + wire [7:0] qpll_drpaddr_in_i = 8'h0; + wire [15:0] qpll_drpdi_in_i = 16'h0; + wire qpll_drpen_in_i = 1'b0; + wire qpll_drpwe_in_i = 1'b0; + wire [15:0] qpll_drpdo_out_i; + wire qpll_drprdy_out_i; + + aurora_64b66b_pcs_pma_gt_common_wrapper gt_common_support ( + .gt_qpllclk_quad1_out (gt_qpllclk_quad1_i), + .gt_qpllrefclk_quad1_out (gt_qpllrefclk_quad1_i), + .GT0_GTREFCLK0_COMMON_IN (refclk), + //----------------------- Common Block - QPLL Ports ------------------------ + .GT0_QPLLLOCK_OUT (gt_qplllock_i), + .GT0_QPLLRESET_IN (gt_to_common_qpllreset_i), + .GT0_QPLLLOCKDETCLK_IN (init_clk), + .GT0_QPLLREFCLKLOST_OUT (gt_qpllrefclklost_i), + //---------------------- Common DRP Ports ---------------------- + .qpll_drpaddr_in (qpll_drpaddr_in_i), + .qpll_drpdi_in (qpll_drpdi_in_i), + .qpll_drpclk_in (init_clk), + .qpll_drpdo_out (qpll_drpdo_out_i), + .qpll_drprdy_out (qpll_drprdy_out_i), + .qpll_drpen_in (qpll_drpen_in_i), + .qpll_drpwe_in (qpll_drpwe_in_i) + ); + + //-------------------------------------------------------------- + // IP Instantiation + //-------------------------------------------------------------- + + wire gt_rxcdrovrden_i = 1'b0; + wire [2:0] loopback_i = 3'b000; + wire power_down_i = 1'b0; + + aurora_64b66b_pcs_pma aurora_64b66b_pcs_pma_i ( + .refclk1_in (refclk), + // TX AXI4-S Interface + .s_axi_tx_tdata (s_axis_tdata), + .s_axi_tx_tvalid (s_axis_tvalid), + .s_axi_tx_tready (s_axis_tready), + // RX AXI4-S Interface + .m_axi_rx_tdata (m_axis_tdata), + .m_axi_rx_tvalid (m_axis_tvalid), + // GTX Serial I/O + .rxp (rx_p), + .rxn (rx_n), + .txp (tx_p), + .txn (tx_n), + // Status and Error + .hard_err (hard_err_i), + .soft_err (soft_err_i), + .channel_up (channel_up_i), + .lane_up (lane_up_i), + // System Interface + .mmcm_not_locked (!mmcm_locked), + .user_clk (user_clk), + .sync_clk (sync_clk), + .reset_pb (reset_pb), + .gt_rxcdrovrden_in (gt_rxcdrovrden_i), + .power_down (power_down_i), + .loopback (loopback_i), + .pma_init (pma_init), + .gt_pll_lock (gt_pll_lock), + .drp_clk_in (init_clk), + .gt_qpllclk_quad1_in (gt_qpllclk_quad1_i), + .gt_qpllrefclk_quad1_in (gt_qpllrefclk_quad1_i), + .gt_to_common_qpllreset_out(gt_to_common_qpllreset_i), + .gt_qplllock_in (gt_qplllock_i), + .gt_qpllrefclklost_in (gt_qpllrefclklost_i), + // AXI4-Lite config + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bresp (s_axi_bresp), + .s_axi_bready (s_axi_bready), + .s_axi_araddr (s_axi_araddr), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + .s_axi_rdata (s_axi_rdata), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rresp (s_axi_rresp), + .s_axi_rready (s_axi_rready), + // GTXE2 COMMON DRP Ports + .qpll_drpaddr_in (qpll_drpaddr_in_i), + .qpll_drpdi_in (qpll_drpdi_in_i), + .qpll_drpdo_out (), + .qpll_drprdy_out (), + .qpll_drpen_in (qpll_drpen_in_i), + .qpll_drpwe_in (qpll_drpwe_in_i), + .init_clk (init_clk), + .link_reset_out (), + .sys_reset_out (user_rst), + .tx_out_clk (tx_out_clk) + ); + + endmodule diff --git a/fpga/usrp3/top/e320/ip/axi64_4k_2clk_fifo/Makefile.inc b/fpga/usrp3/top/e320/ip/axi64_4k_2clk_fifo/Makefile.inc new file mode 100644 index 000000000..75bdf99c3 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi64_4k_2clk_fifo/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI64_4K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci + +IP_AXI64_4K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/, \ +axi64_4k_2clk_fifo.xci.out \ +synth/axi64_4k_2clk_fifo.vhd \ +) + +$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci + $(call BUILD_VIVADO_IP,axi64_4k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/e320/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci b/fpga/usrp3/top/e320/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci new file mode 100644 index 000000000..26d706087 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci @@ -0,0 +1,584 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>axi64_4k_2clk_fifo</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ARESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">69</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">12</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">12</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">12</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">4kx4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">512x72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">509</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">13</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">13</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">13</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">511</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">512</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">9</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Independent_Clock</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axi64_4k_2clk_fifo</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">509</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">13</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">13</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">13</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Independent_Clocks_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Independent_Clocks_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Independent_Clocks_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">511</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">AXI_STREAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">512</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Clock_Type_AXI" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_Data_Counts_axis" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_TLAST" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_axis" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rdch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wdch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wrch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INTERFACE_TYPE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth_axis" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/e320/ip/axi64_8k_2clk_fifo/Makefile.inc b/fpga/usrp3/top/e320/ip/axi64_8k_2clk_fifo/Makefile.inc new file mode 100644 index 000000000..647ca003b --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi64_8k_2clk_fifo/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI64_8K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci + +IP_AXI64_8K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/, \ +axi64_8k_2clk_fifo.xci.out \ +synth/axi64_8k_2clk_fifo.vhd \ +) + +$(IP_AXI64_8K_2CLK_FIFO_SRCS) $(IP_AXI64_8K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci + $(call BUILD_VIVADO_IP,axi64_8k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/e320/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci b/fpga/usrp3/top/e320/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci new file mode 100644 index 000000000..2f6ec0d88 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci @@ -0,0 +1,582 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>axi64_8k_2clk_fifo</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ARESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">69</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">12</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">12</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">12</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">4kx4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">13</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">13</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">13</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Independent_Clock</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axi64_8k_2clk_fifo</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">13</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">13</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">13</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Independent_Clocks_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Independent_Clocks_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Independent_Clocks_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">AXI_STREAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Clock_Type_AXI" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_Data_Counts_axis" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_TLAST" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_axis" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rdch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wdch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wrch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INTERFACE_TYPE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/e320/ip/axi_eth_dma/Makefile.inc b/fpga/usrp3/top/e320/ip/axi_eth_dma/Makefile.inc new file mode 100644 index 000000000..658891469 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi_eth_dma/Makefile.inc @@ -0,0 +1,14 @@ +# +# Copyright 2017 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_ETH_DMA_SRCS = $(IP_BUILD_DIR)/axi_eth_dma/axi_eth_dma.xci + +IP_AXI_ETH_DMA_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_eth_dma/, \ +axi_eth_dma.xci.out \ +) + +$(IP_AXI_ETH_DMA_SRCS) $(IP_AXI_ETH_DMA_OUTS) : $(IP_DIR)/axi_eth_dma/axi_eth_dma.xci + $(call BUILD_VIVADO_IP,axi_eth_dma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/e320/ip/axi_eth_dma/axi_eth_dma.xci b/fpga/usrp3/top/e320/ip/axi_eth_dma/axi_eth_dma.xci new file mode 100644 index 000000000..ec1df69ec --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi_eth_dma/axi_eth_dma.xci @@ -0,0 +1,412 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>axi_eth_dma</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_dma" spirit:version="7.1"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_RESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MM2S_CNTRL_RESET_OUT_N.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MM2S_INTROUT.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MM2S_PRMRY_RESET_OUT_N.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.HAS_TKEEP">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.HAS_TLAST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.HAS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.TDATA_NUM_BYTES">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_RRESP">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.MAX_BURST_LENGTH">256</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.PROTOCOL">AXI4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.READ_WRITE_MODE">READ_ONLY</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_BRESP">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_WSTRB">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.MAX_BURST_LENGTH">256</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.PROTOCOL">AXI4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.READ_WRITE_MODE">WRITE_ONLY</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_BRESP">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_BURST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_CACHE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_PROT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_RRESP">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_WSTRB">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.PROTOCOL">AXI4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2MM_INTROUT.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2MM_PRMRY_RESET_OUT_N.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2MM_STS_RESET_OUT_N.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TKEEP">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TLAST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.TDATA_NUM_BYTES">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DLYTMR_RESOLUTION">125</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_MULTI_CHANNEL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_MM2S">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_MM2S_DRE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_MM2S_SF">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_S2MM">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_S2MM_DRE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_S2MM_SF">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_SG">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCREASE_THROUGHPUT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MICRO_DMA">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MM2S_BURST_SIZE">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_MM2S_TDATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_MM2S_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_MM2S_DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_S2MM_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_S2MM_DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_SG_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_MM2S_CHANNELS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_S2MM_CHANNELS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRMRY_IS_ACLK_ASYNC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S2MM_BURST_SIZE">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SG_INCLUDE_STSCNTRL_STRM">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SG_LENGTH_WIDTH">23</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SG_USE_STSAPP_LENGTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_S2MM_STS_TDATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_S2MM_TDATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axi_eth_dma</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_addr_width">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_dlytmr_resolution">125</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_enable_multi_channel">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_include_mm2s">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_include_mm2s_dre">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_include_mm2s_sf">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_include_s2mm">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_include_s2mm_dre">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_include_s2mm_sf">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_include_sg">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_increase_throughput">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_m_axi_mm2s_data_width">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_m_axi_s2mm_data_width">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_m_axis_mm2s_tdata_width">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_micro_dma">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_mm2s_burst_size">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_num_mm2s_channels">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_num_s2mm_channels">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_prmry_is_aclk_async">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_s2mm_burst_size">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_s_axis_s2mm_tdata_width">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_sg_include_stscntrl_strm">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_sg_length_width">23</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_sg_use_stsapp_length">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_single_interface">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">20</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.TUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.HAS_TKEEP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.HAS_TLAST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_BRESP" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.READ_WRITE_MODE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_RRESP" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.READ_WRITE_MODE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TKEEP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TLAST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.READ_WRITE_MODE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_include_mm2s_dre" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_include_s2mm_dre" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_m_axi_mm2s_data_width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_m_axi_s2mm_data_width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_m_axis_mm2s_tdata_width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_mm2s_burst_size" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_s2mm_burst_size" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_s_axis_s2mm_tdata_width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_sg_include_stscntrl_strm" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_sg_length_width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_sg_use_stsapp_length" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/Makefile.inc b/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/Makefile.inc new file mode 100644 index 000000000..2f5ba57c6 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/Makefile.inc @@ -0,0 +1,17 @@ +# +# Copyright 2016 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTERCON_4X64_256_BD_SRCS = $(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd \ +$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml \ +$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v + +BD_AXI_INTERCON_4X64_256_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/, \ +axi_intercon_4x64_256_bd.bd.out \ +axi_intercon_4x64_256_bd_ooc.xdc \ +) + +$(IP_AXI_INTERCON_4X64_256_BD_SRCS) $(IP_AXI_INTERCON_4X64_256_BD_OUTS) : $(IP_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd + $(call BUILD_VIVADO_BD,axi_intercon_4x64_256_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd b/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd new file mode 100644 index 000000000..eb6c30100 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd @@ -0,0 +1,2191 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<bd:repository xmlns:bd="http://www.xilinx.com/bd" bd:isValidated="true" bd:synthFlowMode="None" bd:tool_version="2015.4" bd:top="axi_intercon_4x64_256_bd" bd:version="1.00.a"> + + <spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>BlockDiagram</spirit:library> + <spirit:name>axi_intercon_4x64_256_bd</spirit:name> + <spirit:version>1.00.a</spirit:version> + <spirit:parameters> + <spirit:parameter> + <spirit:name>isTop</spirit:name> + <spirit:value spirit:format="bool" spirit:resolve="immediate">true</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>M00_AXI</spirit:name> + <spirit:master/> + <spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:parameters> + <spirit:parameter> + <spirit:name>DATA_WIDTH</spirit:name> + <spirit:value>256</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PROTOCOL</spirit:name> + <spirit:value>AXI4</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>200000000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ID_WIDTH</spirit:name> + <spirit:value>4</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user_prop"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ADDR_WIDTH</spirit:name> + <spirit:value>32</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AWUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ARUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>WUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>RUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>BUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>READ_WRITE_MODE</spirit:name> + <spirit:value>READ_WRITE</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_LOCK</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_PROT</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_CACHE</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_QOS</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_REGION</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_WSTRB</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_RRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>SUPPORTS_NARROW_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="ip_prop"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_READ_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>MAX_BURST_LENGTH</spirit:name> + <spirit:value>256</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="ip_prop"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PHASE</spirit:name> + <spirit:value>0.000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_4x64_128_bd_M00_ACLK</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>S00_AXI</spirit:name> + <spirit:slave/> + <spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:parameters> + <spirit:parameter> + <spirit:name>DATA_WIDTH</spirit:name> + <spirit:value>64</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PROTOCOL</spirit:name> + <spirit:value>AXI4</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>350000000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ID_WIDTH</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ADDR_WIDTH</spirit:name> + <spirit:value>32</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AWUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ARUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>WUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>RUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>BUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>READ_WRITE_MODE</spirit:name> + <spirit:value>READ_WRITE</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_LOCK</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_PROT</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_CACHE</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_QOS</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_REGION</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_WSTRB</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_RRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>SUPPORTS_NARROW_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_READ_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>MAX_BURST_LENGTH</spirit:name> + <spirit:value>256</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PHASE</spirit:name> + <spirit:value>0.000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_4x64_128_bd_S00_ACLK</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>S01_AXI</spirit:name> + <spirit:slave/> + <spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:parameters> + <spirit:parameter> + <spirit:name>DATA_WIDTH</spirit:name> + <spirit:value>64</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PROTOCOL</spirit:name> + <spirit:value>AXI4</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>350000000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ID_WIDTH</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ADDR_WIDTH</spirit:name> + <spirit:value>32</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AWUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ARUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>WUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>RUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>BUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>READ_WRITE_MODE</spirit:name> + <spirit:value>READ_WRITE</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_LOCK</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_PROT</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_CACHE</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_QOS</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_REGION</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_WSTRB</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_RRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>SUPPORTS_NARROW_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_READ_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>MAX_BURST_LENGTH</spirit:name> + <spirit:value>256</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PHASE</spirit:name> + <spirit:value>0.000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_4x64_128_bd_S01_ACLK</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>S02_AXI</spirit:name> + <spirit:slave/> + <spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:parameters> + <spirit:parameter> + <spirit:name>DATA_WIDTH</spirit:name> + <spirit:value>64</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PROTOCOL</spirit:name> + <spirit:value>AXI4</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>350000000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ID_WIDTH</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ADDR_WIDTH</spirit:name> + <spirit:value>32</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AWUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ARUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>WUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>RUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>BUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>READ_WRITE_MODE</spirit:name> + <spirit:value>READ_WRITE</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_LOCK</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_PROT</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_CACHE</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_QOS</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_REGION</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_WSTRB</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_RRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>SUPPORTS_NARROW_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_READ_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>MAX_BURST_LENGTH</spirit:name> + <spirit:value>256</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PHASE</spirit:name> + <spirit:value>0.000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_4x64_128_bd_S00_ACLK</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>S03_AXI</spirit:name> + <spirit:slave/> + <spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:parameters> + <spirit:parameter> + <spirit:name>DATA_WIDTH</spirit:name> + <spirit:value>64</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PROTOCOL</spirit:name> + <spirit:value>AXI4</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>350000000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ID_WIDTH</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ADDR_WIDTH</spirit:name> + <spirit:value>32</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AWUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ARUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>WUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>RUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>BUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>READ_WRITE_MODE</spirit:name> + <spirit:value>READ_WRITE</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_LOCK</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_PROT</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_CACHE</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_QOS</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_REGION</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_WSTRB</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_RRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>SUPPORTS_NARROW_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_READ_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>MAX_BURST_LENGTH</spirit:name> + <spirit:value>256</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PHASE</spirit:name> + <spirit:value>0.000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_4x64_128_bd_S00_ACLK</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>CLK.M00_AXI_ACLK</spirit:name> + <spirit:displayName>Clk</spirit:displayName> + <spirit:description>Clock</spirit:description> + <spirit:busType spirit:library="signal" spirit:name="clock" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="signal" spirit:name="clock_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>CLK</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>M00_AXI_ACLK</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>200000000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PHASE</spirit:name> + <spirit:value>0.000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_4x64_128_bd_M00_ACLK</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ASSOCIATED_BUSIF</spirit:name> + <spirit:value>M00_AXI</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ASSOCIATED_RESET</spirit:name> + <spirit:value>M00_AXI_ARESETN</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>RST.M00_AXI_ARESETN</spirit:name> + <spirit:displayName>Reset</spirit:displayName> + <spirit:description>Reset</spirit:description> + <spirit:busType spirit:library="signal" spirit:name="reset" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="signal" spirit:name="reset_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RST</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>M00_AXI_ARESETN</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>POLARITY</spirit:name> + <spirit:value>ACTIVE_LOW</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>CLK.S00_AXI_ACLK</spirit:name> + <spirit:displayName>Clk</spirit:displayName> + <spirit:description>Clock</spirit:description> + <spirit:busType spirit:library="signal" spirit:name="clock" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="signal" spirit:name="clock_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>CLK</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S00_AXI_ACLK</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>350000000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PHASE</spirit:name> + <spirit:value>0.000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_4x64_128_bd_S00_ACLK</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ASSOCIATED_BUSIF</spirit:name> + <spirit:value>S00_AXI</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ASSOCIATED_RESET</spirit:name> + <spirit:value>S00_AXI_ARESETN</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>RST.S00_AXI_ARESETN</spirit:name> + <spirit:displayName>Reset</spirit:displayName> + <spirit:description>Reset</spirit:description> + <spirit:busType spirit:library="signal" spirit:name="reset" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="signal" spirit:name="reset_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RST</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S00_AXI_ARESETN</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>POLARITY</spirit:name> + <spirit:value>ACTIVE_LOW</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>CLK.S01_AXI_ACLK</spirit:name> + <spirit:displayName>Clk</spirit:displayName> + <spirit:description>Clock</spirit:description> + <spirit:busType spirit:library="signal" spirit:name="clock" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="signal" spirit:name="clock_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>CLK</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S01_AXI_ACLK</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>350000000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PHASE</spirit:name> + <spirit:value>0.000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_4x64_128_bd_S01_ACLK</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ASSOCIATED_BUSIF</spirit:name> + <spirit:value>S01_AXI</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ASSOCIATED_RESET</spirit:name> + <spirit:value>S01_AXI_ARESETN</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>RST.S01_AXI_ARESETN</spirit:name> + <spirit:displayName>Reset</spirit:displayName> + <spirit:description>Reset</spirit:description> + <spirit:busType spirit:library="signal" spirit:name="reset" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="signal" spirit:name="reset_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RST</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S01_AXI_ARESETN</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>POLARITY</spirit:name> + <spirit:value>ACTIVE_LOW</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>CLK.S02_AXI_ACLK</spirit:name> + <spirit:displayName>Clk</spirit:displayName> + <spirit:description>Clock</spirit:description> + <spirit:busType spirit:library="signal" spirit:name="clock" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="signal" spirit:name="clock_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>CLK</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S02_AXI_ACLK</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>350000000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PHASE</spirit:name> + <spirit:value>0.000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_4x64_128_bd_S00_ACLK</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ASSOCIATED_BUSIF</spirit:name> + <spirit:value>S02_AXI</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ASSOCIATED_RESET</spirit:name> + <spirit:value>S00_AXI_ARESETN:S02_AXI_ARESETN</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>RST.S02_AXI_ARESETN</spirit:name> + <spirit:displayName>Reset</spirit:displayName> + <spirit:description>Reset</spirit:description> + <spirit:busType spirit:library="signal" spirit:name="reset" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="signal" spirit:name="reset_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RST</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S02_AXI_ARESETN</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>POLARITY</spirit:name> + <spirit:value>ACTIVE_LOW</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>CLK.S03_AXI_ACLK</spirit:name> + <spirit:displayName>Clk</spirit:displayName> + <spirit:description>Clock</spirit:description> + <spirit:busType spirit:library="signal" spirit:name="clock" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="signal" spirit:name="clock_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>CLK</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S03_AXI_ACLK</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>350000000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PHASE</spirit:name> + <spirit:value>0.000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_4x64_128_bd_S00_ACLK</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ASSOCIATED_BUSIF</spirit:name> + <spirit:value>S02_AXI:S03_AXI</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ASSOCIATED_RESET</spirit:name> + <spirit:value>S00_AXI_ARESETN:S02_AXI_ARESETN:S03_AXI_ARESETN</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>RST.S03_AXI_ARESETN</spirit:name> + <spirit:displayName>Reset</spirit:displayName> + <spirit:description>Reset</spirit:description> + <spirit:busType spirit:library="signal" spirit:name="reset" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="signal" spirit:name="reset_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RST</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S03_AXI_ARESETN</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>POLARITY</spirit:name> + <spirit:value>ACTIVE_LOW</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>BlockDiagram</spirit:name> + <spirit:envIdentifier>:vivado.xilinx.com:</spirit:envIdentifier> + <spirit:hierarchyRef spirit:library="BlockDiagram" spirit:name="axi_intercon_4x64_256_bd_imp" spirit:vendor="xilinx.com" spirit:version="1.00.a"/> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>M00_AXI_ACLK</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>M00_AXI_ARESETN</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>S00_AXI_ACLK</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>S00_AXI_ARESETN</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>S01_AXI_ACLK</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>S01_AXI_ARESETN</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>S02_AXI_ACLK</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>S02_AXI_ARESETN</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>S03_AXI_ACLK</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>S03_AXI_ARESETN</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:addressSpaces> + <spirit:addressSpace> + <spirit:name>S00_AXI</spirit:name> + <spirit:range>4G</spirit:range> + <spirit:width>32</spirit:width> + <spirit:segments> + <spirit:segment> + <spirit:name>SEG_M00_AXI_Reg</spirit:name> + <spirit:displayName>/M00_AXI/Reg</spirit:displayName> + <spirit:addressOffset>0x00000000</spirit:addressOffset> + <spirit:range>1G</spirit:range> + </spirit:segment> + </spirit:segments> + </spirit:addressSpace> + <spirit:addressSpace> + <spirit:name>S01_AXI</spirit:name> + <spirit:range>4G</spirit:range> + <spirit:width>32</spirit:width> + <spirit:segments> + <spirit:segment> + <spirit:name>SEG_M00_AXI_Reg</spirit:name> + <spirit:displayName>/M00_AXI/Reg</spirit:displayName> + <spirit:addressOffset>0x00000000</spirit:addressOffset> + <spirit:range>1G</spirit:range> + </spirit:segment> + </spirit:segments> + </spirit:addressSpace> + <spirit:addressSpace> + <spirit:name>S02_AXI</spirit:name> + <spirit:range>4G</spirit:range> + <spirit:width>32</spirit:width> + <spirit:segments> + <spirit:segment> + <spirit:name>SEG_M00_AXI_Reg</spirit:name> + <spirit:displayName>/M00_AXI/Reg</spirit:displayName> + <spirit:addressOffset>0x00000000</spirit:addressOffset> + <spirit:range>1G</spirit:range> + </spirit:segment> + </spirit:segments> + </spirit:addressSpace> + <spirit:addressSpace> + <spirit:name>S03_AXI</spirit:name> + <spirit:range>4G</spirit:range> + <spirit:width>32</spirit:width> + <spirit:segments> + <spirit:segment> + <spirit:name>SEG_M00_AXI_Reg</spirit:name> + <spirit:displayName>/M00_AXI/Reg</spirit:displayName> + <spirit:addressOffset>0x00000000</spirit:addressOffset> + <spirit:range>1G</spirit:range> + </spirit:segment> + </spirit:segments> + </spirit:addressSpace> + </spirit:addressSpaces> + <spirit:memoryMaps> + <spirit:memoryMap> + <spirit:name>M00_AXI</spirit:name> + <spirit:addressBlock> + <spirit:name>Reg</spirit:name> + <spirit:baseAddress>0</spirit:baseAddress> + <spirit:range>64K</spirit:range> + <spirit:width>32</spirit:width> + <spirit:usage>register</spirit:usage> + </spirit:addressBlock> + </spirit:memoryMap> + </spirit:memoryMaps> + </spirit:component> + + <spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>BlockDiagram</spirit:library> + <spirit:name>axi_intercon_4x64_256_bd_imp</spirit:name> + <spirit:version>1.00.a</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>m00_rs</spirit:instanceName> + <spirit:componentRef spirit:library="ip" spirit:name="axi_register_slice" spirit:vendor="xilinx.com" spirit:version="2.1"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="bd:xciName">axi_intercon_4x64_256_bd_m00_rs_0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AW">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AR">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_B">1</spirit:configurableElementValue> + </spirit:configurableElementValues> + </spirit:componentInstance> + <spirit:componentInstance> + <spirit:instanceName>s00_rs</spirit:instanceName> + <spirit:componentRef spirit:library="ip" spirit:name="axi_register_slice" spirit:vendor="xilinx.com" spirit:version="2.1"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="bd:xciName">axi_intercon_4x64_256_bd_s00_rs_0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AW">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AR">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_R">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_W">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_B">1</spirit:configurableElementValue> + </spirit:configurableElementValues> + </spirit:componentInstance> + <spirit:componentInstance> + <spirit:instanceName>s00_width_conv</spirit:instanceName> + <spirit:componentRef spirit:library="ip" spirit:name="axi_dwidth_converter" spirit:vendor="xilinx.com" spirit:version="2.1"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="bd:xciName">axi_intercon_4x64_256_bd_s00_width_conv_0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="SI_DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MI_DATA_WIDTH">256</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="FIFO_MODE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="ACLK_ASYNC">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="SYNCHRONIZATION_STAGES">2</spirit:configurableElementValue> + </spirit:configurableElementValues> + </spirit:componentInstance> + <spirit:componentInstance> + <spirit:instanceName>s01_rs</spirit:instanceName> + <spirit:componentRef spirit:library="ip" spirit:name="axi_register_slice" spirit:vendor="xilinx.com" spirit:version="2.1"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="bd:xciName">axi_intercon_4x64_256_bd_s01_rs_0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AW">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AR">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_R">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_W">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_B">1</spirit:configurableElementValue> + </spirit:configurableElementValues> + </spirit:componentInstance> + <spirit:componentInstance> + <spirit:instanceName>s01_width_conv</spirit:instanceName> + <spirit:componentRef spirit:library="ip" spirit:name="axi_dwidth_converter" spirit:vendor="xilinx.com" spirit:version="2.1"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="bd:xciName">axi_intercon_4x64_256_bd_s01_width_conv_0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="SI_DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MI_DATA_WIDTH">256</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="FIFO_MODE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="ACLK_ASYNC">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="SYNCHRONIZATION_STAGES">2</spirit:configurableElementValue> + </spirit:configurableElementValues> + </spirit:componentInstance> + <spirit:componentInstance> + <spirit:instanceName>xbar</spirit:instanceName> + <spirit:componentRef spirit:library="ip" spirit:name="axi_crossbar" spirit:vendor="xilinx.com" spirit:version="2.1"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="bd:xciName">axi_intercon_4x64_256_bd_xbar_0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="NUM_SI">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="NUM_MI">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="STRATEGY">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="DATA_WIDTH">256</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="CONNECTIVITY_MODE">SAMD</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="S00_SINGLE_THREAD">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="S01_BASE_ID">0x00000004</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="S02_BASE_ID">0x00000008</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="S03_BASE_ID">0x0000000c</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="S04_BASE_ID">0x00000010</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="S05_BASE_ID">0x00000014</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="S06_BASE_ID">0x00000018</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="S07_BASE_ID">0x0000001c</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="S08_BASE_ID">0x00000020</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="S09_BASE_ID">0x00000024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="S10_BASE_ID">0x00000028</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="S11_BASE_ID">0x0000002c</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="S12_BASE_ID">0x00000030</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="S13_BASE_ID">0x00000034</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="S14_BASE_ID">0x00000038</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="S15_BASE_ID">0x0000003c</spirit:configurableElementValue> + </spirit:configurableElementValues> + </spirit:componentInstance> + <spirit:componentInstance> + <spirit:instanceName>s01_rs_256</spirit:instanceName> + <spirit:componentRef spirit:library="ip" spirit:name="axi_register_slice" spirit:vendor="xilinx.com" spirit:version="2.1"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="bd:xciName">axi_intercon_4x64_256_bd_s01_rs_256_0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AW">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AR">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_R">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_W">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_B">1</spirit:configurableElementValue> + </spirit:configurableElementValues> + </spirit:componentInstance> + <spirit:componentInstance> + <spirit:instanceName>s00_rs_256</spirit:instanceName> + <spirit:componentRef spirit:library="ip" spirit:name="axi_register_slice" spirit:vendor="xilinx.com" spirit:version="2.1"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="bd:xciName">axi_intercon_4x64_256_bd_s00_rs_256_0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AW">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AR">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_R">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_W">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_B">1</spirit:configurableElementValue> + </spirit:configurableElementValues> + </spirit:componentInstance> + <spirit:componentInstance> + <spirit:instanceName>s02_rs</spirit:instanceName> + <spirit:componentRef spirit:library="ip" spirit:name="axi_register_slice" spirit:vendor="xilinx.com" spirit:version="2.1"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="bd:xciName">axi_intercon_4x64_256_bd_s02_rs_0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AW">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AR">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_R">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_W">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_B">1</spirit:configurableElementValue> + </spirit:configurableElementValues> + </spirit:componentInstance> + <spirit:componentInstance> + <spirit:instanceName>s03_rs</spirit:instanceName> + <spirit:componentRef spirit:library="ip" spirit:name="axi_register_slice" spirit:vendor="xilinx.com" spirit:version="2.1"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="bd:xciName">axi_intercon_4x64_256_bd_s03_rs_0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AW">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AR">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_R">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_W">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_B">1</spirit:configurableElementValue> + </spirit:configurableElementValues> + </spirit:componentInstance> + <spirit:componentInstance> + <spirit:instanceName>s02_width_conv</spirit:instanceName> + <spirit:componentRef spirit:library="ip" spirit:name="axi_dwidth_converter" spirit:vendor="xilinx.com" spirit:version="2.1"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="bd:xciName">axi_intercon_4x64_256_bd_s02_width_conv_0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="SI_DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MI_DATA_WIDTH">256</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="FIFO_MODE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="ACLK_ASYNC">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="SYNCHRONIZATION_STAGES">2</spirit:configurableElementValue> + </spirit:configurableElementValues> + </spirit:componentInstance> + <spirit:componentInstance> + <spirit:instanceName>s03_width_conv</spirit:instanceName> + <spirit:componentRef spirit:library="ip" spirit:name="axi_dwidth_converter" spirit:vendor="xilinx.com" spirit:version="2.1"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="bd:xciName">axi_intercon_4x64_256_bd_s03_width_conv_0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="SI_DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MI_DATA_WIDTH">256</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="FIFO_MODE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="ACLK_ASYNC">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="SYNCHRONIZATION_STAGES">2</spirit:configurableElementValue> + </spirit:configurableElementValues> + </spirit:componentInstance> + <spirit:componentInstance> + <spirit:instanceName>s03_rs_256</spirit:instanceName> + <spirit:componentRef spirit:library="ip" spirit:name="axi_register_slice" spirit:vendor="xilinx.com" spirit:version="2.1"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="bd:xciName">axi_intercon_4x64_256_bd_s03_rs_256_0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AW">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AR">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_R">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_W">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_B">1</spirit:configurableElementValue> + </spirit:configurableElementValues> + </spirit:componentInstance> + <spirit:componentInstance> + <spirit:instanceName>s02_rs_256</spirit:instanceName> + <spirit:componentRef spirit:library="ip" spirit:name="axi_register_slice" spirit:vendor="xilinx.com" spirit:version="2.1"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="bd:xciName">axi_intercon_4x64_256_bd_s02_rs_256_0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AW">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AR">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_R">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_W">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_B">1</spirit:configurableElementValue> + </spirit:configurableElementValues> + </spirit:componentInstance> + </spirit:componentInstances> + <spirit:interconnections> + <spirit:interconnection> + <spirit:name>s00_rs_M_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s00_rs"/> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s00_width_conv"/> + </spirit:interconnection> + <spirit:interconnection> + <spirit:name>s01_rs_M_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s01_rs"/> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s01_width_conv"/> + </spirit:interconnection> + <spirit:interconnection> + <spirit:name>xbar_M00_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="m00_rs"/> + <spirit:activeInterface spirit:busRef="M00_AXI" spirit:componentRef="xbar"/> + </spirit:interconnection> + <spirit:interconnection> + <spirit:name>s00_rs_256_M_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s00_rs_256"/> + <spirit:activeInterface spirit:busRef="S00_AXI" spirit:componentRef="xbar"/> + </spirit:interconnection> + <spirit:interconnection> + <spirit:name>s01_rs_256_M_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s01_rs_256"/> + <spirit:activeInterface spirit:busRef="S01_AXI" spirit:componentRef="xbar"/> + </spirit:interconnection> + <spirit:interconnection> + <spirit:name>s00_width_conv_M_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s00_width_conv"/> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s00_rs_256"/> + </spirit:interconnection> + <spirit:interconnection> + <spirit:name>s01_width_conv_M_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s01_width_conv"/> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s01_rs_256"/> + </spirit:interconnection> + <spirit:interconnection> + <spirit:name>s02_rs_M_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s02_rs"/> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s02_width_conv"/> + </spirit:interconnection> + <spirit:interconnection> + <spirit:name>s03_rs_M_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s03_rs"/> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s03_width_conv"/> + </spirit:interconnection> + <spirit:interconnection> + <spirit:name>s02_width_conv_M_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s02_width_conv"/> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s02_rs_256"/> + </spirit:interconnection> + <spirit:interconnection> + <spirit:name>s03_width_conv_M_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s03_width_conv"/> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s03_rs_256"/> + </spirit:interconnection> + <spirit:interconnection> + <spirit:name>s02_rs_256_M_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s02_rs_256"/> + <spirit:activeInterface spirit:busRef="S02_AXI" spirit:componentRef="xbar"/> + </spirit:interconnection> + <spirit:interconnection> + <spirit:name>s03_rs_256_M_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s03_rs_256"/> + <spirit:activeInterface spirit:busRef="S03_AXI" spirit:componentRef="xbar"/> + </spirit:interconnection> + </spirit:interconnections> + <spirit:adHocConnections> + <spirit:adHocConnection> + <spirit:name>M00_AXI_ACLK_1</spirit:name> + <spirit:externalPortReference spirit:portRef="M00_AXI_ACLK"/> + <spirit:internalPortReference spirit:componentRef="xbar" spirit:portRef="aclk"/> + <spirit:internalPortReference spirit:componentRef="m00_rs" spirit:portRef="aclk"/> + <spirit:internalPortReference spirit:componentRef="s00_rs_256" spirit:portRef="aclk"/> + <spirit:internalPortReference spirit:componentRef="s01_rs_256" spirit:portRef="aclk"/> + <spirit:internalPortReference spirit:componentRef="s01_width_conv" spirit:portRef="m_axi_aclk"/> + <spirit:internalPortReference spirit:componentRef="s00_width_conv" spirit:portRef="m_axi_aclk"/> + <spirit:internalPortReference spirit:componentRef="s02_width_conv" spirit:portRef="m_axi_aclk"/> + <spirit:internalPortReference spirit:componentRef="s03_width_conv" spirit:portRef="m_axi_aclk"/> + <spirit:internalPortReference spirit:componentRef="s02_rs_256" spirit:portRef="aclk"/> + <spirit:internalPortReference spirit:componentRef="s03_rs_256" spirit:portRef="aclk"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>M00_AXI_ARESETN_1</spirit:name> + <spirit:externalPortReference spirit:portRef="M00_AXI_ARESETN"/> + <spirit:internalPortReference spirit:componentRef="xbar" spirit:portRef="aresetn"/> + <spirit:internalPortReference spirit:componentRef="m00_rs" spirit:portRef="aresetn"/> + <spirit:internalPortReference spirit:componentRef="s00_rs_256" spirit:portRef="aresetn"/> + <spirit:internalPortReference spirit:componentRef="s01_rs_256" spirit:portRef="aresetn"/> + <spirit:internalPortReference spirit:componentRef="s01_width_conv" spirit:portRef="m_axi_aresetn"/> + <spirit:internalPortReference spirit:componentRef="s00_width_conv" spirit:portRef="m_axi_aresetn"/> + <spirit:internalPortReference spirit:componentRef="s02_width_conv" spirit:portRef="m_axi_aresetn"/> + <spirit:internalPortReference spirit:componentRef="s03_width_conv" spirit:portRef="m_axi_aresetn"/> + <spirit:internalPortReference spirit:componentRef="s02_rs_256" spirit:portRef="aresetn"/> + <spirit:internalPortReference spirit:componentRef="s03_rs_256" spirit:portRef="aresetn"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>S00_AXI_ACLK_1</spirit:name> + <spirit:externalPortReference spirit:portRef="S00_AXI_ACLK"/> + <spirit:internalPortReference spirit:componentRef="s00_rs" spirit:portRef="aclk"/> + <spirit:internalPortReference spirit:componentRef="s00_width_conv" spirit:portRef="s_axi_aclk"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>S00_AXI_ARESETN_1</spirit:name> + <spirit:externalPortReference spirit:portRef="S00_AXI_ARESETN"/> + <spirit:internalPortReference spirit:componentRef="s00_rs" spirit:portRef="aresetn"/> + <spirit:internalPortReference spirit:componentRef="s00_width_conv" spirit:portRef="s_axi_aresetn"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>S01_AXI_ACLK_1</spirit:name> + <spirit:externalPortReference spirit:portRef="S01_AXI_ACLK"/> + <spirit:internalPortReference spirit:componentRef="s01_rs" spirit:portRef="aclk"/> + <spirit:internalPortReference spirit:componentRef="s01_width_conv" spirit:portRef="s_axi_aclk"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>S01_AXI_ARESETN_1</spirit:name> + <spirit:externalPortReference spirit:portRef="S01_AXI_ARESETN"/> + <spirit:internalPortReference spirit:componentRef="s01_rs" spirit:portRef="aresetn"/> + <spirit:internalPortReference spirit:componentRef="s01_width_conv" spirit:portRef="s_axi_aresetn"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>S02_AXI_ACLK_1</spirit:name> + <spirit:externalPortReference spirit:portRef="S02_AXI_ACLK"/> + <spirit:internalPortReference spirit:componentRef="s02_rs" spirit:portRef="aclk"/> + <spirit:internalPortReference spirit:componentRef="s02_width_conv" spirit:portRef="s_axi_aclk"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>S02_AXI_ARESETN_1</spirit:name> + <spirit:externalPortReference spirit:portRef="S02_AXI_ARESETN"/> + <spirit:internalPortReference spirit:componentRef="s02_rs" spirit:portRef="aresetn"/> + <spirit:internalPortReference spirit:componentRef="s02_width_conv" spirit:portRef="s_axi_aresetn"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>S03_AXI_ACLK_1</spirit:name> + <spirit:externalPortReference spirit:portRef="S03_AXI_ACLK"/> + <spirit:internalPortReference spirit:componentRef="s03_rs" spirit:portRef="aclk"/> + <spirit:internalPortReference spirit:componentRef="s03_width_conv" spirit:portRef="s_axi_aclk"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>S03_AXI_ARESETN_1</spirit:name> + <spirit:externalPortReference spirit:portRef="S03_AXI_ARESETN"/> + <spirit:internalPortReference spirit:componentRef="s03_rs" spirit:portRef="aresetn"/> + <spirit:internalPortReference spirit:componentRef="s03_width_conv" spirit:portRef="s_axi_aresetn"/> + </spirit:adHocConnection> + </spirit:adHocConnections> + <spirit:hierConnections> + <spirit:hierConnection spirit:interfaceRef="M00_AXI/m00_rs_M_AXI"> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="m00_rs"/> + </spirit:hierConnection> + <spirit:hierConnection spirit:interfaceRef="S00_AXI/S00_AXI_1"> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s00_rs"/> + </spirit:hierConnection> + <spirit:hierConnection spirit:interfaceRef="S01_AXI/S01_AXI_1"> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s01_rs"/> + </spirit:hierConnection> + <spirit:hierConnection spirit:interfaceRef="S02_AXI/S02_AXI_1"> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s02_rs"/> + </spirit:hierConnection> + <spirit:hierConnection spirit:interfaceRef="S03_AXI/S03_AXI_1"> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s03_rs"/> + </spirit:hierConnection> + </spirit:hierConnections> + </spirit:design> + +</bd:repository> diff --git a/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml b/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml new file mode 100644 index 000000000..217597784 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml @@ -0,0 +1,123 @@ +<?xml version="1.0" encoding="UTF-8"?> +<Root MajorVersion="0" MinorVersion="33"> + <CompositeFile CompositeFileTopName="axi_intercon_4x64_256_bd" CanBeSetAsTop="true" CanDisplayChildGraph="true"> + <Description>Composite Fileset</Description> + <Generation Name="SYNTHESIS" State="STALE" Timestamp="1501543653"/> + <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1501543653"/> + <Generation Name="SIMULATION" State="STALE" Timestamp="1501543653"/> + <FileCollection Name="SOURCES" Type="SOURCES"> + <File Name="ip/axi_intercon_4x64_256_bd_m00_rs_0/axi_intercon_4x64_256_bd_m00_rs_0.xci" Type="IP"> + <Instance HierarchyPath="m00_rs"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_4x64_256_bd_s00_rs_0/axi_intercon_4x64_256_bd_s00_rs_0.xci" Type="IP"> + <Instance HierarchyPath="s00_rs"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_4x64_256_bd_s00_width_conv_0/axi_intercon_4x64_256_bd_s00_width_conv_0.xci" Type="IP"> + <Instance HierarchyPath="s00_width_conv"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_4x64_256_bd_s01_rs_0/axi_intercon_4x64_256_bd_s01_rs_0.xci" Type="IP"> + <Instance HierarchyPath="s01_rs"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_4x64_256_bd_s01_width_conv_0/axi_intercon_4x64_256_bd_s01_width_conv_0.xci" Type="IP"> + <Instance HierarchyPath="s01_width_conv"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_4x64_256_bd_xbar_0/axi_intercon_4x64_256_bd_xbar_0.xci" Type="IP"> + <Instance HierarchyPath="xbar"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_4x64_256_bd_s01_rs_256_0/axi_intercon_4x64_256_bd_s01_rs_256_0.xci" Type="IP"> + <Instance HierarchyPath="s01_rs_256"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_4x64_256_bd_s00_rs_256_0/axi_intercon_4x64_256_bd_s00_rs_256_0.xci" Type="IP"> + <Instance HierarchyPath="s00_rs_256"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_4x64_256_bd_s02_rs_0/axi_intercon_4x64_256_bd_s02_rs_0.xci" Type="IP"> + <Instance HierarchyPath="s02_rs"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_4x64_256_bd_s03_rs_0/axi_intercon_4x64_256_bd_s03_rs_0.xci" Type="IP"> + <Instance HierarchyPath="s03_rs"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_4x64_256_bd_s02_width_conv_0/axi_intercon_4x64_256_bd_s02_width_conv_0.xci" Type="IP"> + <Instance HierarchyPath="s02_width_conv"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_4x64_256_bd_s03_width_conv_0/axi_intercon_4x64_256_bd_s03_width_conv_0.xci" Type="IP"> + <Instance HierarchyPath="s03_width_conv"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_4x64_256_bd_s03_rs_256_0/axi_intercon_4x64_256_bd_s03_rs_256_0.xci" Type="IP"> + <Instance HierarchyPath="s03_rs_256"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_4x64_256_bd_s02_rs_256_0/axi_intercon_4x64_256_bd_s02_rs_256_0.xci" Type="IP"> + <Instance HierarchyPath="s02_rs_256"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + </FileCollection> + </CompositeFile> +</Root> diff --git a/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v b/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v new file mode 100644 index 000000000..71e446f92 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v @@ -0,0 +1,419 @@ +//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +`timescale 1 ps / 1 ps + +module axi_intercon_4x64_256_bd_wrapper ( + input M00_AXI_ACLK, + input M00_AXI_ARESETN, + output [31:0]M00_AXI_ARADDR, + output [1:0]M00_AXI_ARBURST, + output [3:0]M00_AXI_ARCACHE, + output [3:0]M00_AXI_ARID, + output [7:0]M00_AXI_ARLEN, + output [0:0]M00_AXI_ARLOCK, + output [2:0]M00_AXI_ARPROT, + output [3:0]M00_AXI_ARQOS, + input M00_AXI_ARREADY, + output [3:0]M00_AXI_ARREGION, + output [2:0]M00_AXI_ARSIZE, + output M00_AXI_ARVALID, + output [31:0]M00_AXI_AWADDR, + output [1:0]M00_AXI_AWBURST, + output [3:0]M00_AXI_AWCACHE, + output [3:0]M00_AXI_AWID, + output [7:0]M00_AXI_AWLEN, + output [0:0]M00_AXI_AWLOCK, + output [2:0]M00_AXI_AWPROT, + output [3:0]M00_AXI_AWQOS, + input M00_AXI_AWREADY, + output [3:0]M00_AXI_AWREGION, + output [2:0]M00_AXI_AWSIZE, + output M00_AXI_AWVALID, + input [3:0]M00_AXI_BID, + output M00_AXI_BREADY, + input [1:0]M00_AXI_BRESP, + input M00_AXI_BVALID, + input [255:0]M00_AXI_RDATA, + input [3:0]M00_AXI_RID, + input M00_AXI_RLAST, + output M00_AXI_RREADY, + input [1:0]M00_AXI_RRESP, + input M00_AXI_RVALID, + output [255:0]M00_AXI_WDATA, + output M00_AXI_WLAST, + input M00_AXI_WREADY, + output [31:0]M00_AXI_WSTRB, + output M00_AXI_WVALID, + input S00_AXI_ACLK, + input S00_AXI_ARESETN, + input [31:0]S00_AXI_ARADDR, + input [1:0]S00_AXI_ARBURST, + input [3:0]S00_AXI_ARCACHE, + input [0:0]S00_AXI_ARID, + input [7:0]S00_AXI_ARLEN, + input [0:0]S00_AXI_ARLOCK, + input [2:0]S00_AXI_ARPROT, + input [3:0]S00_AXI_ARQOS, + output S00_AXI_ARREADY, + input [3:0]S00_AXI_ARREGION, + input [2:0]S00_AXI_ARSIZE, + input S00_AXI_ARVALID, + input [31:0]S00_AXI_AWADDR, + input [1:0]S00_AXI_AWBURST, + input [3:0]S00_AXI_AWCACHE, + input [0:0]S00_AXI_AWID, + input [7:0]S00_AXI_AWLEN, + input [0:0]S00_AXI_AWLOCK, + input [2:0]S00_AXI_AWPROT, + input [3:0]S00_AXI_AWQOS, + output S00_AXI_AWREADY, + input [3:0]S00_AXI_AWREGION, + input [2:0]S00_AXI_AWSIZE, + input S00_AXI_AWVALID, + output [0:0]S00_AXI_BID, + input S00_AXI_BREADY, + output [1:0]S00_AXI_BRESP, + output S00_AXI_BVALID, + output [63:0]S00_AXI_RDATA, + output [0:0]S00_AXI_RID, + output S00_AXI_RLAST, + input S00_AXI_RREADY, + output [1:0]S00_AXI_RRESP, + output S00_AXI_RVALID, + input [63:0]S00_AXI_WDATA, + input S00_AXI_WLAST, + output S00_AXI_WREADY, + input [7:0]S00_AXI_WSTRB, + input S00_AXI_WVALID, + input S01_AXI_ACLK, + input S01_AXI_ARESETN, + input [31:0]S01_AXI_ARADDR, + input [1:0]S01_AXI_ARBURST, + input [3:0]S01_AXI_ARCACHE, + input [0:0]S01_AXI_ARID, + input [7:0]S01_AXI_ARLEN, + input [0:0]S01_AXI_ARLOCK, + input [2:0]S01_AXI_ARPROT, + input [3:0]S01_AXI_ARQOS, + output S01_AXI_ARREADY, + input [3:0]S01_AXI_ARREGION, + input [2:0]S01_AXI_ARSIZE, + input S01_AXI_ARVALID, + input [31:0]S01_AXI_AWADDR, + input [1:0]S01_AXI_AWBURST, + input [3:0]S01_AXI_AWCACHE, + input [0:0]S01_AXI_AWID, + input [7:0]S01_AXI_AWLEN, + input [0:0]S01_AXI_AWLOCK, + input [2:0]S01_AXI_AWPROT, + input [3:0]S01_AXI_AWQOS, + output S01_AXI_AWREADY, + input [3:0]S01_AXI_AWREGION, + input [2:0]S01_AXI_AWSIZE, + input S01_AXI_AWVALID, + output [0:0]S01_AXI_BID, + input S01_AXI_BREADY, + output [1:0]S01_AXI_BRESP, + output S01_AXI_BVALID, + output [63:0]S01_AXI_RDATA, + output [0:0]S01_AXI_RID, + output S01_AXI_RLAST, + input S01_AXI_RREADY, + output [1:0]S01_AXI_RRESP, + output S01_AXI_RVALID, + input [63:0]S01_AXI_WDATA, + input S01_AXI_WLAST, + output S01_AXI_WREADY, + input [7:0]S01_AXI_WSTRB, + input S01_AXI_WVALID, + input S02_AXI_ACLK, + input S02_AXI_ARESETN, + input [31:0]S02_AXI_ARADDR, + input [1:0]S02_AXI_ARBURST, + input [3:0]S02_AXI_ARCACHE, + input [0:0]S02_AXI_ARID, + input [7:0]S02_AXI_ARLEN, + input [0:0]S02_AXI_ARLOCK, + input [2:0]S02_AXI_ARPROT, + input [3:0]S02_AXI_ARQOS, + output S02_AXI_ARREADY, + input [3:0]S02_AXI_ARREGION, + input [2:0]S02_AXI_ARSIZE, + input S02_AXI_ARVALID, + input [31:0]S02_AXI_AWADDR, + input [1:0]S02_AXI_AWBURST, + input [3:0]S02_AXI_AWCACHE, + input [0:0]S02_AXI_AWID, + input [7:0]S02_AXI_AWLEN, + input [0:0]S02_AXI_AWLOCK, + input [2:0]S02_AXI_AWPROT, + input [3:0]S02_AXI_AWQOS, + output S02_AXI_AWREADY, + input [3:0]S02_AXI_AWREGION, + input [2:0]S02_AXI_AWSIZE, + input S02_AXI_AWVALID, + output [0:0]S02_AXI_BID, + input S02_AXI_BREADY, + output [1:0]S02_AXI_BRESP, + output S02_AXI_BVALID, + output [63:0]S02_AXI_RDATA, + output [0:0]S02_AXI_RID, + output S02_AXI_RLAST, + input S02_AXI_RREADY, + output [1:0]S02_AXI_RRESP, + output S02_AXI_RVALID, + input [63:0]S02_AXI_WDATA, + input S02_AXI_WLAST, + output S02_AXI_WREADY, + input [7:0]S02_AXI_WSTRB, + input S02_AXI_WVALID, + input S03_AXI_ACLK, + input S03_AXI_ARESETN, + input [31:0]S03_AXI_ARADDR, + input [1:0]S03_AXI_ARBURST, + input [3:0]S03_AXI_ARCACHE, + input [0:0]S03_AXI_ARID, + input [7:0]S03_AXI_ARLEN, + input [0:0]S03_AXI_ARLOCK, + input [2:0]S03_AXI_ARPROT, + input [3:0]S03_AXI_ARQOS, + output S03_AXI_ARREADY, + input [3:0]S03_AXI_ARREGION, + input [2:0]S03_AXI_ARSIZE, + input S03_AXI_ARVALID, + input [31:0]S03_AXI_AWADDR, + input [1:0]S03_AXI_AWBURST, + input [3:0]S03_AXI_AWCACHE, + input [0:0]S03_AXI_AWID, + input [7:0]S03_AXI_AWLEN, + input [0:0]S03_AXI_AWLOCK, + input [2:0]S03_AXI_AWPROT, + input [3:0]S03_AXI_AWQOS, + output S03_AXI_AWREADY, + input [3:0]S03_AXI_AWREGION, + input [2:0]S03_AXI_AWSIZE, + input S03_AXI_AWVALID, + output [0:0]S03_AXI_BID, + input S03_AXI_BREADY, + output [1:0]S03_AXI_BRESP, + output S03_AXI_BVALID, + output [63:0]S03_AXI_RDATA, + output [0:0]S03_AXI_RID, + output S03_AXI_RLAST, + input S03_AXI_RREADY, + output [1:0]S03_AXI_RRESP, + output S03_AXI_RVALID, + input [63:0]S03_AXI_WDATA, + input S03_AXI_WLAST, + output S03_AXI_WREADY, + input [7:0]S03_AXI_WSTRB, + input S03_AXI_WVALID +); + + axi_intercon_4x64_256_bd axi_intercon_4x64_256_bd_i ( + .M00_AXI_ACLK(M00_AXI_ACLK), + .M00_AXI_ARESETN(M00_AXI_ARESETN), + .M00_AXI_araddr(M00_AXI_ARADDR), + .M00_AXI_arburst(M00_AXI_ARBURST), + .M00_AXI_arcache(M00_AXI_ARCACHE), + .M00_AXI_arid(M00_AXI_ARID), + .M00_AXI_arlen(M00_AXI_ARLEN), + .M00_AXI_arlock(M00_AXI_ARLOCK), + .M00_AXI_arprot(M00_AXI_ARPROT), + .M00_AXI_arqos(M00_AXI_ARQOS), + .M00_AXI_arready(M00_AXI_ARREADY), + .M00_AXI_arregion(M00_AXI_ARREGION), + .M00_AXI_arsize(M00_AXI_ARSIZE), + .M00_AXI_arvalid(M00_AXI_ARVALID), + .M00_AXI_awaddr(M00_AXI_AWADDR), + .M00_AXI_awburst(M00_AXI_AWBURST), + .M00_AXI_awcache(M00_AXI_AWCACHE), + .M00_AXI_awid(M00_AXI_AWID), + .M00_AXI_awlen(M00_AXI_AWLEN), + .M00_AXI_awlock(M00_AXI_AWLOCK), + .M00_AXI_awprot(M00_AXI_AWPROT), + .M00_AXI_awqos(M00_AXI_AWQOS), + .M00_AXI_awready(M00_AXI_AWREADY), + .M00_AXI_awregion(M00_AXI_AWREGION), + .M00_AXI_awsize(M00_AXI_AWSIZE), + .M00_AXI_awvalid(M00_AXI_AWVALID), + .M00_AXI_bid(M00_AXI_BID), + .M00_AXI_bready(M00_AXI_BREADY), + .M00_AXI_bresp(M00_AXI_BRESP), + .M00_AXI_bvalid(M00_AXI_BVALID), + .M00_AXI_rdata(M00_AXI_RDATA), + .M00_AXI_rid(M00_AXI_RID), + .M00_AXI_rlast(M00_AXI_RLAST), + .M00_AXI_rready(M00_AXI_RREADY), + .M00_AXI_rresp(M00_AXI_RRESP), + .M00_AXI_rvalid(M00_AXI_RVALID), + .M00_AXI_wdata(M00_AXI_WDATA), + .M00_AXI_wlast(M00_AXI_WLAST), + .M00_AXI_wready(M00_AXI_WREADY), + .M00_AXI_wstrb(M00_AXI_WSTRB), + .M00_AXI_wvalid(M00_AXI_WVALID), + .S00_AXI_ACLK(S00_AXI_ACLK), + .S00_AXI_ARESETN(S00_AXI_ARESETN), + .S00_AXI_araddr(S00_AXI_ARADDR), + .S00_AXI_arburst(S00_AXI_ARBURST), + .S00_AXI_arcache(S00_AXI_ARCACHE), + .S00_AXI_arid(S00_AXI_ARID), + .S00_AXI_arlen(S00_AXI_ARLEN), + .S00_AXI_arlock(S00_AXI_ARLOCK), + .S00_AXI_arprot(S00_AXI_ARPROT), + .S00_AXI_arqos(S00_AXI_ARQOS), + .S00_AXI_arready(S00_AXI_ARREADY), + .S00_AXI_arregion(S00_AXI_ARREGION), + .S00_AXI_arsize(S00_AXI_ARSIZE), + .S00_AXI_arvalid(S00_AXI_ARVALID), + .S00_AXI_awaddr(S00_AXI_AWADDR), + .S00_AXI_awburst(S00_AXI_AWBURST), + .S00_AXI_awcache(S00_AXI_AWCACHE), + .S00_AXI_awid(S00_AXI_AWID), + .S00_AXI_awlen(S00_AXI_AWLEN), + .S00_AXI_awlock(S00_AXI_AWLOCK), + .S00_AXI_awprot(S00_AXI_AWPROT), + .S00_AXI_awqos(S00_AXI_AWQOS), + .S00_AXI_awready(S00_AXI_AWREADY), + .S00_AXI_awregion(S00_AXI_AWREGION), + .S00_AXI_awsize(S00_AXI_AWSIZE), + .S00_AXI_awvalid(S00_AXI_AWVALID), + .S00_AXI_bid(S00_AXI_BID), + .S00_AXI_bready(S00_AXI_BREADY), + .S00_AXI_bresp(S00_AXI_BRESP), + .S00_AXI_bvalid(S00_AXI_BVALID), + .S00_AXI_rdata(S00_AXI_RDATA), + .S00_AXI_rid(S00_AXI_RID), + .S00_AXI_rlast(S00_AXI_RLAST), + .S00_AXI_rready(S00_AXI_RREADY), + .S00_AXI_rresp(S00_AXI_RRESP), + .S00_AXI_rvalid(S00_AXI_RVALID), + .S00_AXI_wdata(S00_AXI_WDATA), + .S00_AXI_wlast(S00_AXI_WLAST), + .S00_AXI_wready(S00_AXI_WREADY), + .S00_AXI_wstrb(S00_AXI_WSTRB), + .S00_AXI_wvalid(S00_AXI_WVALID), + .S01_AXI_ACLK(S01_AXI_ACLK), + .S01_AXI_ARESETN(S01_AXI_ARESETN), + .S01_AXI_araddr(S01_AXI_ARADDR), + .S01_AXI_arburst(S01_AXI_ARBURST), + .S01_AXI_arcache(S01_AXI_ARCACHE), + .S01_AXI_arid(S01_AXI_ARID), + .S01_AXI_arlen(S01_AXI_ARLEN), + .S01_AXI_arlock(S01_AXI_ARLOCK), + .S01_AXI_arprot(S01_AXI_ARPROT), + .S01_AXI_arqos(S01_AXI_ARQOS), + .S01_AXI_arready(S01_AXI_ARREADY), + .S01_AXI_arregion(S01_AXI_ARREGION), + .S01_AXI_arsize(S01_AXI_ARSIZE), + .S01_AXI_arvalid(S01_AXI_ARVALID), + .S01_AXI_awaddr(S01_AXI_AWADDR), + .S01_AXI_awburst(S01_AXI_AWBURST), + .S01_AXI_awcache(S01_AXI_AWCACHE), + .S01_AXI_awid(S01_AXI_AWID), + .S01_AXI_awlen(S01_AXI_AWLEN), + .S01_AXI_awlock(S01_AXI_AWLOCK), + .S01_AXI_awprot(S01_AXI_AWPROT), + .S01_AXI_awqos(S01_AXI_AWQOS), + .S01_AXI_awready(S01_AXI_AWREADY), + .S01_AXI_awregion(S01_AXI_AWREGION), + .S01_AXI_awsize(S01_AXI_AWSIZE), + .S01_AXI_awvalid(S01_AXI_AWVALID), + .S01_AXI_bid(S01_AXI_BID), + .S01_AXI_bready(S01_AXI_BREADY), + .S01_AXI_bresp(S01_AXI_BRESP), + .S01_AXI_bvalid(S01_AXI_BVALID), + .S01_AXI_rdata(S01_AXI_RDATA), + .S01_AXI_rid(S01_AXI_RID), + .S01_AXI_rlast(S01_AXI_RLAST), + .S01_AXI_rready(S01_AXI_RREADY), + .S01_AXI_rresp(S01_AXI_RRESP), + .S01_AXI_rvalid(S01_AXI_RVALID), + .S01_AXI_wdata(S01_AXI_WDATA), + .S01_AXI_wlast(S01_AXI_WLAST), + .S01_AXI_wready(S01_AXI_WREADY), + .S01_AXI_wstrb(S01_AXI_WSTRB), + .S01_AXI_wvalid(S01_AXI_WVALID), + .S02_AXI_ACLK(S02_AXI_ACLK), + .S02_AXI_ARESETN(S02_AXI_ARESETN), + .S02_AXI_araddr(S02_AXI_ARADDR), + .S02_AXI_arburst(S02_AXI_ARBURST), + .S02_AXI_arcache(S02_AXI_ARCACHE), + .S02_AXI_arid(S02_AXI_ARID), + .S02_AXI_arlen(S02_AXI_ARLEN), + .S02_AXI_arlock(S02_AXI_ARLOCK), + .S02_AXI_arprot(S02_AXI_ARPROT), + .S02_AXI_arqos(S02_AXI_ARQOS), + .S02_AXI_arready(S02_AXI_ARREADY), + .S02_AXI_arregion(S02_AXI_ARREGION), + .S02_AXI_arsize(S02_AXI_ARSIZE), + .S02_AXI_arvalid(S02_AXI_ARVALID), + .S02_AXI_awaddr(S02_AXI_AWADDR), + .S02_AXI_awburst(S02_AXI_AWBURST), + .S02_AXI_awcache(S02_AXI_AWCACHE), + .S02_AXI_awid(S02_AXI_AWID), + .S02_AXI_awlen(S02_AXI_AWLEN), + .S02_AXI_awlock(S02_AXI_AWLOCK), + .S02_AXI_awprot(S02_AXI_AWPROT), + .S02_AXI_awqos(S02_AXI_AWQOS), + .S02_AXI_awready(S02_AXI_AWREADY), + .S02_AXI_awregion(S02_AXI_AWREGION), + .S02_AXI_awsize(S02_AXI_AWSIZE), + .S02_AXI_awvalid(S02_AXI_AWVALID), + .S02_AXI_bid(S02_AXI_BID), + .S02_AXI_bready(S02_AXI_BREADY), + .S02_AXI_bresp(S02_AXI_BRESP), + .S02_AXI_bvalid(S02_AXI_BVALID), + .S02_AXI_rdata(S02_AXI_RDATA), + .S02_AXI_rid(S02_AXI_RID), + .S02_AXI_rlast(S02_AXI_RLAST), + .S02_AXI_rready(S02_AXI_RREADY), + .S02_AXI_rresp(S02_AXI_RRESP), + .S02_AXI_rvalid(S02_AXI_RVALID), + .S02_AXI_wdata(S02_AXI_WDATA), + .S02_AXI_wlast(S02_AXI_WLAST), + .S02_AXI_wready(S02_AXI_WREADY), + .S02_AXI_wstrb(S02_AXI_WSTRB), + .S02_AXI_wvalid(S02_AXI_WVALID), + .S03_AXI_ACLK(S03_AXI_ACLK), + .S03_AXI_ARESETN(S03_AXI_ARESETN), + .S03_AXI_araddr(S03_AXI_ARADDR), + .S03_AXI_arburst(S03_AXI_ARBURST), + .S03_AXI_arcache(S03_AXI_ARCACHE), + .S03_AXI_arid(S03_AXI_ARID), + .S03_AXI_arlen(S03_AXI_ARLEN), + .S03_AXI_arlock(S03_AXI_ARLOCK), + .S03_AXI_arprot(S03_AXI_ARPROT), + .S03_AXI_arqos(S03_AXI_ARQOS), + .S03_AXI_arready(S03_AXI_ARREADY), + .S03_AXI_arregion(S03_AXI_ARREGION), + .S03_AXI_arsize(S03_AXI_ARSIZE), + .S03_AXI_arvalid(S03_AXI_ARVALID), + .S03_AXI_awaddr(S03_AXI_AWADDR), + .S03_AXI_awburst(S03_AXI_AWBURST), + .S03_AXI_awcache(S03_AXI_AWCACHE), + .S03_AXI_awid(S03_AXI_AWID), + .S03_AXI_awlen(S03_AXI_AWLEN), + .S03_AXI_awlock(S03_AXI_AWLOCK), + .S03_AXI_awprot(S03_AXI_AWPROT), + .S03_AXI_awqos(S03_AXI_AWQOS), + .S03_AXI_awready(S03_AXI_AWREADY), + .S03_AXI_awregion(S03_AXI_AWREGION), + .S03_AXI_awsize(S03_AXI_AWSIZE), + .S03_AXI_awvalid(S03_AXI_AWVALID), + .S03_AXI_bid(S03_AXI_BID), + .S03_AXI_bready(S03_AXI_BREADY), + .S03_AXI_bresp(S03_AXI_BRESP), + .S03_AXI_bvalid(S03_AXI_BVALID), + .S03_AXI_rdata(S03_AXI_RDATA), + .S03_AXI_rid(S03_AXI_RID), + .S03_AXI_rlast(S03_AXI_RLAST), + .S03_AXI_rready(S03_AXI_RREADY), + .S03_AXI_rresp(S03_AXI_RRESP), + .S03_AXI_rvalid(S03_AXI_RVALID), + .S03_AXI_wdata(S03_AXI_WDATA), + .S03_AXI_wlast(S03_AXI_WLAST), + .S03_AXI_wready(S03_AXI_WREADY), + .S03_AXI_wstrb(S03_AXI_WSTRB), + .S03_AXI_wvalid(S03_AXI_WVALID) + ); +endmodule diff --git a/fpga/usrp3/top/e320/ip/ddr3_32bit/Makefile.inc b/fpga/usrp3/top/e320/ip/ddr3_32bit/Makefile.inc new file mode 100644 index 000000000..90b0be153 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/ddr3_32bit/Makefile.inc @@ -0,0 +1,26 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_DDR3_32BIT_SRCS = \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit.xci \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v + +IP_DDR3_32BIT_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_32bit/, \ +ddr3_32bit.xci.out \ +ddr3_32bit/user_design/rtl/ddr3_32bit.v \ +ddr3_32bit/user_design/rtl/ddr3_32bit_mig.v \ +) + +IP_DDR3_32BIT_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_32bit/, \ +ddr3_32bit/example_design/sim/ddr3_model.sv \ +ddr3_32bit/example_design/sim/ddr3_model_parameters.vh \ +) + + +$(IP_DDR3_32BIT_SRCS) $(IP_DDR3_32BIT_OUTS) : $(IP_DIR)/ddr3_32bit/ddr3_32bit.xci $(IP_DIR)/ddr3_32bit/mig_*.prj + cp -f $(IP_DIR)/ddr3_32bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_32bit/mig_a.prj # Note: This won't allow parallel IP builds + $(call BUILD_VIVADO_IP,ddr3_32bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + rm -f $(IP_DIR)/ddr3_32bit/mig_a.prj diff --git a/fpga/usrp3/top/e320/ip/ddr3_32bit/ddr3_32bit.xci b/fpga/usrp3/top/e320/ip/ddr3_32bit/ddr3_32bit.xci new file mode 100644 index 000000000..70d1ff5f1 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/ddr3_32bit/ddr3_32bit.xci @@ -0,0 +1,2648 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>ddr3_32bit</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="mig_7series" spirit:version="4.2"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_ARESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_CLOCK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_CLOCK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT0.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT1.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT2.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT3.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT4.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT4.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_ARESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_CLOCK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_CLOCK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR3.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR3.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR3.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR3.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR3.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR3.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR3.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR3.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT0.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT1.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT2.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT3.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT4.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT4.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_ARESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_CLOCK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_CLOCK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT1.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT2.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT3.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT4.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT4.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_ARESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_CLOCK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_CLOCK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT0.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT1.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT2.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT3.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT4.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT4.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_SYS_CLK_I.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_SYS_CLK_I.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_SYS_CLK_I.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_ARESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_CLOCK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_CLOCK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_ARESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_CLOCK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_CLOCK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_ARESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_CLOCK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_CLOCK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_ARESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_CLOCK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_CLOCK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT0.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT0.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT1.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT1.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT2.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT2.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT3.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT3.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT4.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT4.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT4.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYSTEM_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_CLK_I.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_CLK_I.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_CLK_I.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">31</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">256</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDRX_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_ECC">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_FREQ_HZ">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_IS_CLK_SHARED">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MEM_TYPE">DDR3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_VCO">1200.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_POLARITY">ACTIVE_LOW</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_QDRIIP_BURST_LEN">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_DK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_QK_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_DK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_QK_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDX_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDX_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDX_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_SYSCLK_TYPE">DIFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_USE_AXI">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDRX_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_ECC">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_FREQ_HZ">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_IS_CLK_SHARED">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MEM_TYPE">DDR3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_VCO">1200.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_POLARITY">ACTIVE_LOW</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_QDRIIP_BURST_LEN">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_DK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_QK_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_DK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_QK_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDX_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDX_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDX_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_SYSCLK_TYPE">DIFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_USE_AXI">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDRX_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_ECC">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_FREQ_HZ">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_IS_CLK_SHARED">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MEM_TYPE">DDR3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_VCO">1200.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_POLARITY">ACTIVE_LOW</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_QDRIIP_BURST_LEN">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_DK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_QK_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_DK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_QK_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDX_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDX_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDX_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_SYSCLK_TYPE">DIFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_USE_AXI">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDRX_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_ECC">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_FREQ_HZ">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_IS_CLK_SHARED">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MEM_TYPE">DDR3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_VCO">1200.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_POLARITY">ACTIVE_LOW</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_QDRIIP_BURST_LEN">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_DK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_QK_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_DK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_QK_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDX_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDX_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDX_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_SYSCLK_TYPE">DIFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_USE_AXI">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDRX_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_ECC">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_FREQ_HZ">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_IS_CLK_SHARED">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MEM_TYPE">DDR3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_VCO">1200.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_POLARITY">ACTIVE_LOW</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_QDRIIP_BURST_LEN">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_DK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_QK_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_DK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_QK_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDX_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDX_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDX_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_SYSCLK_TYPE">DIFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_USE_AXI">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDRX_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_ECC">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_FREQ_HZ">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_IS_CLK_SHARED">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MEM_TYPE">DDR3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_VCO">1200.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_POLARITY">ACTIVE_LOW</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_QDRIIP_BURST_LEN">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_DK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_QK_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_DK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_QK_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDX_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDX_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDX_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_SYSCLK_TYPE">DIFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_USE_AXI">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDRX_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_ECC">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_FREQ_HZ">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_IS_CLK_SHARED">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MEM_TYPE">DDR3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_VCO">1200.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_POLARITY">ACTIVE_LOW</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_QDRIIP_BURST_LEN">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_DK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_QK_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_DK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_QK_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDX_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDX_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDX_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_SYSCLK_TYPE">DIFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_USE_AXI">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDRX_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_ECC">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_FREQ_HZ">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_IS_CLK_SHARED">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MEM_TYPE">DDR3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_VCO">1200.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_POLARITY">ACTIVE_LOW</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_QDRIIP_BURST_LEN">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_DK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_QK_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_DK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_QK_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDX_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDX_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDX_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_SYSCLK_TYPE">DIFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_USE_AXI">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.COMBINED_INTERFACE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">31</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">256</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_MEM_SIZE">2147483648</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_ADDR_WIDTH">30</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_DM_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_DQS_CNT_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_DQS_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_DQ_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_ROW_WIDTH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_nCK_PER_CLK">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDRX_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDRX_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDRX_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ECC">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.FREQ_HZ">166666667</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IS_CLK_SHARED">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MEM_TYPE">DDR3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_VCO">666</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.NoOfControllers">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.POLARITY">ACTIVE_HIGH</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.QDRIIP_BURST_LEN">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.QDRIIP_BW_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.REFCLK_TYPE">NOBUF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_DK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_QK_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_DK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_NUM_DEVICES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_QK_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_QVLD_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDX_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDX_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDX_CMD_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDX_DATA_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDX_DM_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDX_nCK_PER_CLK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SYSCLK_TYPE">DIFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TEMP_MON_CONTROL">EXTERNAL</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USE_AXI">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BOARD_MIG_PARAM">Custom</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">ddr3_32bit</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MIG_DONT_TOUCH_PARAM">Custom</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.XML_INPUT_FILE">mig_a.prj</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z045</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BOARD_MIG_PARAM" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MIG_DONT_TOUCH_PARAM" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.XML_INPUT_FILE" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/e320/ip/ddr3_32bit/mig_xc7z045ffg900-3.prj b/fpga/usrp3/top/e320/ip/ddr3_32bit/mig_xc7z045ffg900-3.prj new file mode 100644 index 000000000..eebc03e4c --- /dev/null +++ b/fpga/usrp3/top/e320/ip/ddr3_32bit/mig_xc7z045ffg900-3.prj @@ -0,0 +1,161 @@ +<?xml version='1.0' encoding='UTF-8'?> +<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. --> +<Project NoOfControllers="1" > + <ModuleName>ddr3_32bit</ModuleName> + <dci_inouts_inputs>1</dci_inouts_inputs> + <dci_inputs>1</dci_inputs> + <Debug_En>OFF</Debug_En> + <DataDepth_En>1024</DataDepth_En> + <LowPower_En>ON</LowPower_En> + <XADC_En>Disabled</XADC_En> + <TargetFPGA>xc7z045-ffg900/-3</TargetFPGA> + <Version>4.0</Version> + <SystemClock>Differential</SystemClock> + <ReferenceClock>No Buffer</ReferenceClock> + <SysResetPolarity>ACTIVE HIGH</SysResetPolarity> + <BankSelectionFlag>FALSE</BankSelectionFlag> + <InternalVref>0</InternalVref> + <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs> + <dci_cascade>0</dci_cascade> + <Controller number="0" > + <MemoryDevice>DDR3_SDRAM/Components/MT41K512M8XX-125</MemoryDevice> + <TimePeriod>1500</TimePeriod> + <VccAuxIO>1.8V</VccAuxIO> + <PHYRatio>4:1</PHYRatio> + <InputClkFreq>133.333</InputClkFreq> + <UIExtraClocks>0</UIExtraClocks> + <MMCM_VCO>666</MMCM_VCO> + <MMCMClkOut0> 1.000</MMCMClkOut0> + <MMCMClkOut1>1</MMCMClkOut1> + <MMCMClkOut2>1</MMCMClkOut2> + <MMCMClkOut3>1</MMCMClkOut3> + <MMCMClkOut4>1</MMCMClkOut4> + <DataWidth>32</DataWidth> + <DeepMemory>1</DeepMemory> + <DataMask>1</DataMask> + <ECC>Disabled</ECC> + <Ordering>Normal</Ordering> + <BankMachineCnt>4</BankMachineCnt> + <CustomPart>TRUE</CustomPart> + <NewPartName>MT41K512M16XX-125</NewPartName> + <RowAddress>16</RowAddress> + <ColAddress>10</ColAddress> + <BankAddress>3</BankAddress> + <MemoryVoltage>1.5V</MemoryVoltage> + <UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap> + <PinSelection> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D8" SLEW="" name="ddr3_addr[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B7" SLEW="" name="ddr3_addr[10]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="J9" SLEW="" name="ddr3_addr[11]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D11" SLEW="" name="ddr3_addr[12]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F7" SLEW="" name="ddr3_addr[13]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D6" SLEW="" name="ddr3_addr[14]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B6" SLEW="" name="ddr3_addr[15]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F9" SLEW="" name="ddr3_addr[1]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A7" SLEW="" name="ddr3_addr[2]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D9" SLEW="" name="ddr3_addr[3]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="H7" SLEW="" name="ddr3_addr[4]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E8" SLEW="" name="ddr3_addr[5]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F8" SLEW="" name="ddr3_addr[6]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E7" SLEW="" name="ddr3_addr[7]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C6" SLEW="" name="ddr3_addr[8]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C7" SLEW="" name="ddr3_addr[9]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C9" SLEW="" name="ddr3_ba[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="G7" SLEW="" name="ddr3_ba[1]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B9" SLEW="" name="ddr3_ba[2]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D10" SLEW="" name="ddr3_cas_n" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="H8" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="J8" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E11" SLEW="" name="ddr3_cke[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E10" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D16" SLEW="" name="ddr3_dm[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C12" SLEW="" name="ddr3_dm[1]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="J13" SLEW="" name="ddr3_dm[2]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F14" SLEW="" name="ddr3_dm[3]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B16" SLEW="" name="ddr3_dq[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C11" SLEW="" name="ddr3_dq[10]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C14" SLEW="" name="ddr3_dq[11]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A12" SLEW="" name="ddr3_dq[12]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="" name="ddr3_dq[13]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B11" SLEW="" name="ddr3_dq[14]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A14" SLEW="" name="ddr3_dq[15]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J16" SLEW="" name="ddr3_dq[16]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J14" SLEW="" name="ddr3_dq[17]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L15" SLEW="" name="ddr3_dq[18]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="H14" SLEW="" name="ddr3_dq[19]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A17" SLEW="" name="ddr3_dq[1]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K15" SLEW="" name="ddr3_dq[20]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="H13" SLEW="" name="ddr3_dq[21]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L14" SLEW="" name="ddr3_dq[22]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J15" SLEW="" name="ddr3_dq[23]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="" name="ddr3_dq[24]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="" name="ddr3_dq[25]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F13" SLEW="" name="ddr3_dq[26]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G16" SLEW="" name="ddr3_dq[27]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="" name="ddr3_dq[28]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G15" SLEW="" name="ddr3_dq[29]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C16" SLEW="" name="ddr3_dq[2]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="" name="ddr3_dq[30]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G14" SLEW="" name="ddr3_dq[31]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="" name="ddr3_dq[3]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C17" SLEW="" name="ddr3_dq[4]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D14" SLEW="" name="ddr3_dq[5]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B17" SLEW="" name="ddr3_dq[6]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="" name="ddr3_dq[7]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B12" SLEW="" name="ddr3_dq[8]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A13" SLEW="" name="ddr3_dq[9]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E17" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A15" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K13" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F12" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F17" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B15" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="L13" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G12" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="G11" SLEW="" name="ddr3_odt[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A10" SLEW="" name="ddr3_ras_n" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="LVCMOS15" PADName="B10" SLEW="" name="ddr3_reset_n" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A9" SLEW="" name="ddr3_we_n" IN_TERM="" /> + </PinSelection> + <System_Clock> + <Pin PADName="H9/G9(CC_P/N)" Bank="34" name="sys_clk_p/n" /> + </System_Clock> + <System_Control> + <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" /> + <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" /> + <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" /> + </System_Control> + <TimingParameters> + <Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="40" trtp="7.5" tcke="5" trfc="350" trp="13.75" tras="35" trcd="13.75" /> + </TimingParameters> + <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength> + <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType> + <mrCasLatency name="CAS Latency" >9</mrCasLatency> + <mrMode name="Mode" >Normal</mrMode> + <mrDllReset name="DLL Reset" >No</mrDllReset> + <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode> + <emrDllEnable name="DLL Enable" >Enable</emrDllEnable> + <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength> + <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection> + <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection> + <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT> + <emrPosted name="Additive Latency (AL)" >0</emrPosted> + <emrOCD name="Write Leveling Enable" >Disabled</emrOCD> + <emrDQS name="TDQS enable" >Enabled</emrDQS> + <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS> + <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh> + <mr2CasWriteLatency name="CAS write latency" >7</mr2CasWriteLatency> + <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh> + <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange> + <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR> + <PortInterface>AXI</PortInterface> + <AXIParameters> + <C0_C_RD_WR_ARB_ALGORITHM>ROUND_ROBIN</C0_C_RD_WR_ARB_ALGORITHM> + <C0_S_AXI_ADDR_WIDTH>31</C0_S_AXI_ADDR_WIDTH> + <C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH> + <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH> + <C0_S_AXI_SUPPORTS_NARROW_BURST>1</C0_S_AXI_SUPPORTS_NARROW_BURST> + </AXIParameters> + </Controller> + +</Project> diff --git a/fpga/usrp3/top/e320/ip/e320_ps_bd/Makefile.inc b/fpga/usrp3/top/e320/ip/e320_ps_bd/Makefile.inc new file mode 100644 index 000000000..23db0e8e8 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/e320_ps_bd/Makefile.inc @@ -0,0 +1,35 @@ +# +# Copyright 2018 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak +include $(LIB_DIR)/rfnoc/utils/Makefile.srcs + +IP_E320_PS_ORIG_SRCS = $(addprefix $(IP_DIR)/e320_ps_bd/, \ +e320_ps_bd.tcl \ +chdr_dma_rx.tcl \ +chdr_dma_tx.tcl \ +chdr_dma_frame_size.tcl \ +chdr_dma_top.tcl \ +) + +IP_E320_PS_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/e320_ps_bd/, \ +e320_ps_bd.tcl \ +chdr_dma_rx.tcl \ +chdr_dma_tx.tcl \ +chdr_dma_frame_size.tcl \ +chdr_dma_top.tcl \ +) + +IP_E320_PS_HDL_SRCS = $(RFNOC_UTIL_SRCS) + +IP_E320_PS_BD_SRCS = $(IP_BUILD_DIR)/e320_ps_bd/e320_ps_bd/e320_ps_bd.bd + +BD_E320_PS_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/e320_ps_bd/, \ +e320_ps_bd.bd.out \ +e320_ps_bd/e320_ps_bd_ooc.xdc \ +) + +$(IP_E320_PS_BD_SRCS) $(BD_E320_PS_BD_OUTS) $(IP_E320_PS_BDTCL_SRCS): $(IP_E320_PS_ORIG_SRCS) $(IP_E320_PS_HDL_SRCS) + $(call BUILD_VIVADO_BDTCL,e320_ps_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_E320_PS_HDL_SRCS)) + diff --git a/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_frame_size.tcl b/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_frame_size.tcl new file mode 100644 index 000000000..387f67d9c --- /dev/null +++ b/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_frame_size.tcl @@ -0,0 +1,59 @@ +# Hierarchical cell: mtu +proc create_hier_cell_mtu { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" } { + puts "ERROR: create_hier_cell_mtu() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create cells and wire everything up + create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs + connect_bd_net -net mtu_regs_1 [get_bd_pins mtu_regs] + # BUG: Vivado 2015.4 does not connect nets the first time with just the driver + connect_bd_net -quiet -net mtu_regs_1 [get_bd_pins mtu_regs] + + for {set i 0} {$i < $numPorts} {incr i} { + # Create instance: xlslice_0, and set properties + set xlslice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_$i ] + set_property -dict [ list \ + CONFIG.DIN_FROM [expr $i * 32 + 15] \ + CONFIG.DIN_TO [expr $i * 32] \ + CONFIG.DIN_WIDTH [expr $numPorts * 32] \ + CONFIG.DOUT_WIDTH {16} \ + ] $xlslice + + connect_bd_net -net mtu_regs_1 [get_bd_pins $xlslice/Din] + + create_bd_pin -dir O -from 15 -to 0 mtu$i + connect_bd_net [get_bd_pins mtu$i] [get_bd_pins $xlslice/Dout] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + diff --git a/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_rx.tcl b/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_rx.tcl new file mode 100644 index 000000000..500771071 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_rx.tcl @@ -0,0 +1,339 @@ +set scriptDir [file dirname [info script]] + +source "$scriptDir/chdr_dma_frame_size.tcl" + +proc create_hier_cell_rx_dma_channel { parentCell nameHier } { + + if { $parentCell eq "" || $nameHier eq "" } { + puts "ERROR: create_hier_cell_dma() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_dest_axi + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_pin -dir I -from 15 -to 0 frame_size + create_bd_pin -dir O -type intr irq + create_bd_pin -dir I -type rst m_dest_axi_aresetn + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk s_axis_aclk + + ######################### + # Instantiate IPs + ######################### + set reset_inv [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 reset_inv ] + set_property -dict [ list \ + CONFIG.C_SIZE {1} \ + CONFIG.C_OPERATION {not} \ + ] $reset_inv + + set chdr_padder [ create_bd_cell -type module -reference chdr_pad_packet chdr_padder ] + set_property -dict [ list \ + CONFIG.CHDR_W {64} \ + ] $chdr_padder + set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_pins chdr_padder/rst] + + set axi_rx_dmac [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_rx_dmac ] + set_property -dict [ list \ + CONFIG.ASYNC_CLK_DEST_REQ {true} \ + CONFIG.ASYNC_CLK_REQ_SRC {true} \ + CONFIG.ASYNC_CLK_SRC_DEST {false} \ + CONFIG.DMA_AXI_PROTOCOL_DEST {1} \ + CONFIG.DMA_TYPE_SRC {1} \ + CONFIG.SYNC_TRANSFER_START {false} \ + ] $axi_rx_dmac + + ######################### + # Wiring + ######################### + + # Top-level connections + connect_bd_net -net aclk_1 \ + [get_bd_pins s_axis_aclk] \ + [get_bd_pins chdr_padder/clk] \ + [get_bd_pins axi_rx_dmac/m_dest_axi_aclk] \ + [get_bd_pins axi_rx_dmac/s_axis_aclk] + connect_bd_net -net aresetn_1 \ + [get_bd_pins m_dest_axi_aresetn] \ + [get_bd_pins reset_inv/Op1] \ + [get_bd_pins axi_rx_dmac/m_dest_axi_aresetn] + connect_bd_net -net areset_1 \ + [get_bd_pins reset_inv/Res] \ + [get_bd_pins chdr_padder/rst] + connect_bd_net -net s_axi_aclk_1 \ + [get_bd_pins s_axi_aclk] \ + [get_bd_pins axi_rx_dmac/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 \ + [get_bd_pins s_axi_aresetn] \ + [get_bd_pins axi_rx_dmac/s_axi_aresetn] + connect_bd_net -net axi_rx_dmac_irq \ + [get_bd_pins irq] \ + [get_bd_pins axi_rx_dmac/irq] + connect_bd_net -net mtu \ + [get_bd_pins frame_size] \ + [get_bd_pins chdr_padder/len] + + # Control and DMA ports + connect_bd_intf_net -intf_net axi_rx_dmac_s_axi \ + [get_bd_intf_pins s_axi] \ + [get_bd_intf_pins axi_rx_dmac/s_axi] + connect_bd_intf_net -intf_net axi_rx_dmac_m_dest_axi \ + [get_bd_intf_pins m_dest_axi] \ + [get_bd_intf_pins axi_rx_dmac/m_dest_axi] + + # AXI-Stream ports + connect_bd_intf_net -intf_net s_axis_dma \ + [get_bd_intf_pins S_AXIS] \ + [get_bd_intf_pins chdr_padder/s_axis] + connect_bd_intf_net -intf_net s_axis_dma_padded \ + [get_bd_intf_pins chdr_padder/m_axis] \ + [get_bd_intf_pins axi_rx_dmac/s_axis] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: rx +proc create_hier_cell_rx_dma { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { + puts "ERROR: create_hier_cell_rx() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + if { $numPorts < 1 } { + puts "ERROR: numPorts invalid: $numPorts" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_rx_dmac + + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq + create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs + ######################### + # Instantiate IPs + ######################### + # For sharing one S_AXI_HP port across all RX DMA engines + set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ] + set_property -dict [ list \ + CONFIG.CONNECTIVITY_MODE {SASD} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI $numPorts \ + CONFIG.R_REGISTER {1} \ + ] $axi_crossbar_0 + + # For fanning out AXI-Lite bus to all RX DMA engines + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI $numPorts \ + ] $axi_interconnect_0 + + # Routes AXI-Stream to appropriate RX DMA engine + set axis_switch_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_0 ] + set_property -dict [ list \ + CONFIG.DECODER_REG {1} \ + CONFIG.NUM_MI $numPorts \ + CONFIG.NUM_SI {1} \ + ] $axis_switch_0 + + # Cross domains from incoming AXI-Stream to RX DMA engines domain + # Note that the fifo_generator_0 is hard-coded to have 4 TDEST bits, so we + # are limited to 16 RX DMA channels + set fifo_generator_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 fifo_generator_0 ] + set_property -dict [ list \ + CONFIG.Clock_Type_AXI {Independent_Clock} \ + CONFIG.Empty_Threshold_Assert_Value_axis {1021} \ + CONFIG.Empty_Threshold_Assert_Value_rach {13} \ + CONFIG.Empty_Threshold_Assert_Value_rdch {1021} \ + CONFIG.Empty_Threshold_Assert_Value_wach {13} \ + CONFIG.Empty_Threshold_Assert_Value_wdch {1021} \ + CONFIG.Empty_Threshold_Assert_Value_wrch {13} \ + CONFIG.Enable_TLAST {true} \ + CONFIG.FIFO_Implementation_axis {Independent_Clocks_Block_RAM} \ + CONFIG.FIFO_Implementation_rach {Independent_Clocks_Distributed_RAM} \ + CONFIG.FIFO_Implementation_rdch {Independent_Clocks_Block_RAM} \ + CONFIG.FIFO_Implementation_wach {Independent_Clocks_Distributed_RAM} \ + CONFIG.FIFO_Implementation_wdch {Independent_Clocks_Block_RAM} \ + CONFIG.FIFO_Implementation_wrch {Independent_Clocks_Distributed_RAM} \ + CONFIG.Full_Flags_Reset_Value {1} \ + CONFIG.Full_Threshold_Assert_Value_axis {1023} \ + CONFIG.Full_Threshold_Assert_Value_rach {15} \ + CONFIG.Full_Threshold_Assert_Value_wach {15} \ + CONFIG.Full_Threshold_Assert_Value_wrch {15} \ + CONFIG.HAS_TKEEP {false} \ + CONFIG.INTERFACE_TYPE {AXI_STREAM} \ + CONFIG.Input_Depth_axis {1024} \ + CONFIG.Reset_Type {Asynchronous_Reset} \ + CONFIG.TDATA_NUM_BYTES {8} \ + CONFIG.TDEST_WIDTH {4} \ + CONFIG.TKEEP_WIDTH {0} \ + CONFIG.TSTRB_WIDTH {8} \ + CONFIG.TUSER_WIDTH {0} \ + ] $fifo_generator_0 + + set rx_dmac_irq_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 rx_dmac_irq_concat ] + set_property -dict [ list \ + CONFIG.NUM_PORTS $numPorts \ + ] $rx_dmac_irq_concat + + create_hier_cell_mtu $hier_obj mtu $numPorts + + ######################### + # Wiring + ######################### + connect_bd_intf_net -intf_net S00_AXIS_1 \ + [get_bd_intf_pins S_AXIS_DMA] \ + [get_bd_intf_pins fifo_generator_0/S_AXIS] + + connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI \ + [get_bd_intf_pins M_AXI_RX_DMA] \ + [get_bd_intf_pins axi_crossbar_0/M00_AXI] + + connect_bd_intf_net -intf_net fifo_generator_0_M_AXIS \ + [get_bd_intf_pins axis_switch_0/S00_AXIS] \ + [get_bd_intf_pins fifo_generator_0/M_AXIS] + + connect_bd_intf_net -intf_net s_axi_rx_dmac_1 \ + [get_bd_intf_pins s_axi_rx_dmac] \ + [get_bd_intf_pins axi_interconnect_0/S00_AXI] + + connect_bd_net -net aresetn_1 \ + [get_bd_pins bus_rstn] \ + [get_bd_pins fifo_generator_0/s_aresetn] + connect_bd_net -net bus_clk \ + [get_bd_pins bus_clk] \ + [get_bd_pins fifo_generator_0/s_aclk] + + connect_bd_net -net clk40 \ + [get_bd_pins clk40] \ + [get_bd_pins axi_crossbar_0/aclk] \ + [get_bd_pins axi_interconnect_0/ACLK] \ + [get_bd_pins axi_interconnect_0/S00_ACLK] \ + [get_bd_pins axis_switch_0/aclk] \ + [get_bd_pins fifo_generator_0/m_aclk] + + connect_bd_net -net clk40_rstn \ + [get_bd_pins clk40_rstn] \ + [get_bd_pins axi_crossbar_0/aresetn] \ + [get_bd_pins axi_interconnect_0/ARESETN] \ + [get_bd_pins axi_interconnect_0/S00_ARESETN] \ + [get_bd_pins axis_switch_0/aresetn] + + connect_bd_net -net mtu_regs_1 \ + [get_bd_pins mtu_regs] \ + [get_bd_pins mtu/mtu_regs] + + connect_bd_net -net rx_dmac_irq_concat_dout \ + [get_bd_pins irq] \ + [get_bd_pins rx_dmac_irq_concat/dout] + + ######################### + # Per-port Section + ######################### + for {set i 0} {$i < $numPorts} {incr i} { + puts "Instantiating rx_dma port ${i}" + create_hier_cell_rx_dma_channel $hier_obj dma$i + + set_property -dict [ list \ + [format "CONFIG.S%02d_SINGLE_THREAD" ${i}] {1} \ + ] $axi_crossbar_0 + + connect_bd_intf_net -intf_net [format "axis_switch_0_M%02d_AXIS" ${i}] \ + [get_bd_intf_pins [format "axis_switch_0/M%02d_AXIS" ${i}]] \ + [get_bd_intf_pins dma${i}/S_AXIS] + + connect_bd_intf_net -intf_net [format "axi_interconnect_0_M%02d_AXI" ${i}] \ + [get_bd_intf_pins [format "axi_interconnect_0/M%02d_AXI" ${i}]] \ + [get_bd_intf_pins dma${i}/s_axi] + + connect_bd_intf_net -intf_net dma${i}_m_dest_axi \ + [get_bd_intf_pins [format "axi_crossbar_0/S%02d_AXI" ${i}]] \ + [get_bd_intf_pins dma${i}/m_dest_axi] + + connect_bd_net -net clk40 \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ACLK" ${i}]] \ + [get_bd_pins dma${i}/s_axi_aclk] \ + [get_bd_pins dma${i}/s_axis_aclk] + + connect_bd_net -net clk40_rstn \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ARESETN" ${i}]] \ + [get_bd_pins dma${i}/m_dest_axi_aresetn] \ + [get_bd_pins dma${i}/s_axi_aresetn] + + connect_bd_net -net dma${i}_irq \ + [get_bd_pins dma${i}/irq] \ + [get_bd_pins rx_dmac_irq_concat/In${i}] + + connect_bd_net -net frame_size_${i} \ + [get_bd_pins dma${i}/frame_size] \ + [get_bd_pins mtu/mtu${i}] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + + diff --git a/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_top.tcl b/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_top.tcl new file mode 100644 index 000000000..9a4e832aa --- /dev/null +++ b/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_top.tcl @@ -0,0 +1,159 @@ +set scriptDir [file dirname [info script]] + +source "$scriptDir/chdr_dma_rx.tcl" +source "$scriptDir/chdr_dma_tx.tcl" + +# Hierarchical cell: dma +proc create_hier_cell_dma { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { + puts "ERROR: create_hier_cell_dma() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + if { $numPorts < 2 } { + puts "ERROR: numPorts invalid: $numPorts" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_rx_dmac + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_tx_dmac + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_regfile + + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O rx_irq + create_bd_pin -dir O tx_irq + + ######################### + # Instantiate IPs + ######################### + # Create instance: rx + create_hier_cell_rx_dma $hier_obj rx $numPorts + + # Create instance: tx + create_hier_cell_tx_dma $hier_obj tx $numPorts + + # Used to set frame size of RX DMA engines + set axi_regfile_0 [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_regfile:1.0 axi_regfile_0 ] + set_property -dict [ list \ +CONFIG.NUM_REGS $numPorts \ + ] $axi_regfile_0 + + set util_reduced_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_reduced_logic_0 ] + set_property -dict [ list \ +CONFIG.C_OPERATION {or} \ +CONFIG.C_SIZE $numPorts \ + ] $util_reduced_logic_0 + + set util_reduced_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_reduced_logic_1 ] + set_property -dict [ list \ +CONFIG.C_OPERATION {or} \ +CONFIG.C_SIZE $numPorts \ + ] $util_reduced_logic_1 + + ######################### + # Wiring + ######################### + # Clocks and resets + connect_bd_net -net bus_clk_1 \ + [get_bd_pins bus_clk] \ + [get_bd_pins rx/bus_clk] \ + [get_bd_pins tx/bus_clk] + connect_bd_net -net bus_rstn_1 \ + [get_bd_pins bus_rstn] \ + [get_bd_pins rx/bus_rstn] \ + [get_bd_pins tx/bus_rstn] + connect_bd_net -net clk40_1 \ + [get_bd_pins clk40] \ + [get_bd_pins rx/clk40] \ + [get_bd_pins tx/clk40] \ + [get_bd_pins axi_regfile_0/S_AXI_ACLK] + connect_bd_net -net clk40_rstn_1 \ + [get_bd_pins clk40_rstn] \ + [get_bd_pins axi_regfile_0/S_AXI_ARESETN] \ + [get_bd_pins rx/clk40_rstn] \ + [get_bd_pins tx/clk40_rstn] + + # AXI buses + connect_bd_intf_net -intf_net s_axi_rx_dmac_1 \ + [get_bd_intf_pins s_axi_rx_dmac] \ + [get_bd_intf_pins rx/s_axi_rx_dmac] + connect_bd_intf_net -intf_net rx_dma_M_AXI_RX_DMA \ + [get_bd_intf_pins M_AXI_RX_DMA] \ + [get_bd_intf_pins rx/M_AXI_RX_DMA] + connect_bd_intf_net -intf_net s_axi_tx_dmac_1 \ + [get_bd_intf_pins s_axi_tx_dmac] \ + [get_bd_intf_pins tx/s_axi_tx_dmac] + connect_bd_intf_net -intf_net tx_M_AXI_TX_DMA \ + [get_bd_intf_pins M_AXI_TX_DMA] \ + [get_bd_intf_pins tx/M_AXI_TX_DMA] + connect_bd_intf_net -intf_net s_axi_regfile_1 \ + [get_bd_intf_pins s_axi_regfile] \ + [get_bd_intf_pins axi_regfile_0/S_AXI] + + # RX CHDR + connect_bd_intf_net -intf_net s_axis_dma_1 \ + [get_bd_intf_pins s_axis_dma] \ + [get_bd_intf_pins rx/S_AXIS_DMA] + + # TX CHDR + connect_bd_intf_net -intf_net m_axis_dma_1 \ + [get_bd_intf_pins tx/M_AXIS_DMA] \ + [get_bd_intf_pins m_axis_dma] + + # IRQs and Frame Sizes + connect_bd_net -net frame_sizes \ + [get_bd_pins axi_regfile_0/regs] \ + [get_bd_pins rx/mtu_regs] + connect_bd_net -net rx_irq1 \ + [get_bd_pins rx/irq] \ + [get_bd_pins util_reduced_logic_0/Op1] + connect_bd_net -net tx_irq1 \ + [get_bd_pins tx/irq] \ + [get_bd_pins util_reduced_logic_1/Op1] + connect_bd_net -net util_reduced_logic_0_Res \ + [get_bd_pins rx_irq] \ + [get_bd_pins util_reduced_logic_0/Res] + connect_bd_net -net util_reduced_logic_1_Res \ + [get_bd_pins tx_irq] \ + [get_bd_pins util_reduced_logic_1/Res] + + # Restore current instance + current_bd_instance $oldCurInst +} + + diff --git a/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_tx.tcl b/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_tx.tcl new file mode 100644 index 000000000..e2d160f69 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_tx.tcl @@ -0,0 +1,193 @@ +# Hierarchical cell: tx +proc create_hier_cell_tx_dma { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { + puts "ERROR: create_hier_cell_tx() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + if { $numPorts < 1 } { + puts "ERROR: numPorts invalid: $numPorts" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_DMA + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_tx_dmac + + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq + + ######################### + # Instantiate IPs + ######################### + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI $numPorts \ + ] $axi_interconnect_0 + + set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI $numPorts + ] $axi_crossbar_0 + + set axis_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_interconnect:2.1 axis_interconnect_0 ] + set_property -dict [ list \ + CONFIG.ARB_ON_TLAST {1} \ + CONFIG.ARB_ON_MAX_XFERS {0} \ + CONFIG.ENABLE_ADVANCED_OPTIONS {1} \ + CONFIG.M00_HAS_REGSLICE {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI $numPorts \ + ] $axis_interconnect_0 + + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ + CONFIG.NUM_PORTS $numPorts \ + ] $xlconcat_0 + + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property -dict [ list \ +CONFIG.CONST_VAL {0} \ + ] $xlconstant_0 + + ######################### + # Wiring + ######################### + connect_bd_net -net bus_clk \ + [get_bd_pins bus_clk] \ + [get_bd_pins axis_interconnect_0/ACLK] \ + [get_bd_pins axis_interconnect_0/M00_AXIS_ACLK] + connect_bd_net -net bus_rstn \ + [get_bd_pins bus_rstn] \ + [get_bd_pins axis_interconnect_0/ARESETN] \ + [get_bd_pins axis_interconnect_0/M00_AXIS_ARESETN] + connect_bd_net -net clk40 \ + [get_bd_pins clk40] \ + [get_bd_pins axi_crossbar_0/aclk] \ + [get_bd_pins axi_interconnect_0/ACLK] \ + [get_bd_pins axi_interconnect_0/S00_ACLK] + connect_bd_net -net clk40_rstn \ + [get_bd_pins clk40_rstn] \ + [get_bd_pins axi_crossbar_0/aresetn] \ + [get_bd_pins axi_interconnect_0/ARESETN] \ + [get_bd_pins axi_interconnect_0/S00_ARESETN] + + connect_bd_net -net xlconstant_0_dout \ + [get_bd_pins xlconstant_0/dout] + connect_bd_net -net xlconcat_0_dout \ + [get_bd_pins irq] \ + [get_bd_pins xlconcat_0/dout] + + connect_bd_intf_net -intf_net M_AXI_TX_DMAC_1 \ + [get_bd_intf_pins s_axi_tx_dmac] \ + [get_bd_intf_pins axi_interconnect_0/S00_AXI] + connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI \ + [get_bd_intf_pins M_AXI_TX_DMA] \ + [get_bd_intf_pins axi_crossbar_0/M00_AXI] + connect_bd_intf_net -intf_net axis_interconnect_0_M00_AXIS \ + [get_bd_intf_pins M_AXIS_DMA] \ + [get_bd_intf_pins axis_interconnect_0/M00_AXIS] + + ######################### + # Per-port Section + ######################### + for {set i 0} {$i < $numPorts} {incr i} { + # Configure each port on axi_crossbar and axis_interconnect + puts "Creating TX dma port ${i}" + set_property [format "CONFIG.S%02d_SINGLE_THREAD" ${i}] {1} $axi_crossbar_0 + set_property -dict [ list \ + [format "CONFIG.S%02d_HAS_REGSLICE" ${i}] {1} \ + ] $axis_interconnect_0 + + set axi_tx_dmac [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_tx_dmac_$i ] + set_property -dict [ list \ + CONFIG.DMA_TYPE_DEST {1} \ + CONFIG.DMA_TYPE_SRC {0} \ + ] $axi_tx_dmac + + # Add a tuser signal indicating which DMA channel originated the packet + # Hard-coded to handle up to 16 DMA channels + # Convert i (in decimal) to 4-bit binary: + binary scan [binary format c ${i}] B* i_binary + set i_binary [string range ${i_binary} end-3 end] + + set tuser_appender [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_subset_converter_${i} ] + set_property -dict [ list \ + CONFIG.M_TUSER_WIDTH.VALUE_SRC USER \ + ] $tuser_appender + set_property -dict [ list \ + CONFIG.M_TUSER_WIDTH {4} \ + CONFIG.TUSER_REMAP 4'b${i_binary} \ + ] $tuser_appender + + connect_bd_intf_net -intf_net [format "axis_subset_converter_%d_S_AXIS" ${i}] \ + [get_bd_intf_pins $axi_tx_dmac/m_axis] \ + [get_bd_intf_pins ${tuser_appender}/S_AXIS] + connect_bd_intf_net -intf_net [format "S%02d_AXIS_1" ${i}] \ + [get_bd_intf_pins ${tuser_appender}/M_AXIS] \ + [get_bd_intf_pins [format "axis_interconnect_0/S%02d_AXIS" ${i}]] + connect_bd_intf_net -intf_net axi_dmac_${i}_m_src_axi \ + [get_bd_intf_pins [format "axi_crossbar_0/S%02d_AXI" ${i}]] \ + [get_bd_intf_pins $axi_tx_dmac/m_src_axi] + connect_bd_intf_net -intf_net [format "axi_interconnect_0_M%02d_AXI" ${i}] \ + [get_bd_intf_pins [format "axi_interconnect_0/M%02d_AXI" ${i}]] \ + [get_bd_intf_pins $axi_tx_dmac/s_axi] + + connect_bd_net [get_bd_pins $axi_tx_dmac/irq] [get_bd_pins xlconcat_0/In${i}] + + connect_bd_net -net clk40 \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ACLK" ${i}]]\ + [get_bd_pins $axi_tx_dmac/m_axis_aclk] \ + [get_bd_pins $axi_tx_dmac/m_src_axi_aclk] \ + [get_bd_pins $axi_tx_dmac/s_axi_aclk] \ + [get_bd_pins $tuser_appender/aclk] \ + [get_bd_pins [format "axis_interconnect_0/S%02d_AXIS_ACLK" ${i}]] + + connect_bd_net -net clk40_rstn \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ARESETN" ${i}]] \ + [get_bd_pins $axi_tx_dmac/m_src_axi_aresetn] \ + [get_bd_pins $axi_tx_dmac/s_axi_aresetn] \ + [get_bd_pins $tuser_appender/aresetn] \ + [get_bd_pins [format "axis_interconnect_0/S%02d_AXIS_ARESETN" ${i}]] + + connect_bd_net -net xlconstant_0_dout \ + [get_bd_pins [format "axis_interconnect_0/S%02d_ARB_REQ_SUPPRESS" ${i}]] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + diff --git a/fpga/usrp3/top/e320/ip/e320_ps_bd/e320_ps_bd.pdf b/fpga/usrp3/top/e320/ip/e320_ps_bd/e320_ps_bd.pdf new file mode 100644 index 000000000..158c6caac --- /dev/null +++ b/fpga/usrp3/top/e320/ip/e320_ps_bd/e320_ps_bd.pdf @@ -0,0 +1,7164 @@ +%PDF-1.4 +1 0 obj +<< + /Title (first) + /Author (sugandha) + /Producer (Concept Engineering GmbH) + /Creator (Nlview 6.6.11 2017-06-12 bk=1.3860 VDI=40 GEI=35) + /CreationDate (D:20180320170927) +>> +endobj +2 0 obj +<< + /Type /Catalog + /Pages 3 0 R + /Outlines 7 0 R + /PageMode /UseThumbs + /ViewerPreferences << /DisplayDocTitle true >> +>> +endobj +4 0 obj +<< + /Type /Font + /Subtype /Type1 + /Name /F1 + /BaseFont /Helvetica + /Encoding /MacRomanEncoding +>> +endobj +5 0 obj +<< + /ExtGState 6 0 R + /Font << /F1 4 0 R >> + /ColorSpace << /PCS [/Pattern /DeviceRGB] >> + /Pattern 8 0 R + /XObject 9 0 R +>> +endobj +% +% Nlview page 1 +% (user space scaling 0.279435) +% +10 0 obj +<< + /Type /Page + /Parent 3 0 R + /Resources 5 0 R + /Contents 11 0 R + /MediaBox [0 0 612 792] + /Rotate 0 +>> +endobj +11 0 obj +<< + /Length 53730 +>> +stream +1 0 0 1 0 2.53669 cm +1 0 0 1 28.8 28.8 cm +0.279435 0 0 -0.279435 0 0 cm +1 0 0 1 0 -2610 cm +0 0 1984 2610 re +W n +/GS gs +1 0 0 1 239 470 cm +q +1.000 1.000 1.000 rg +/GSa0 gs +-239 -470 1984 2611 re +f +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 20 m +1580 13 l +1594 13 l +1601 20 l +1594 27 l +1580 27 l +h f +Q +[] 0 d +3 w +0.165 0.369 0.435 RG +/GSA0 gs +1580 20 m +1580 13 l +1594 13 l +1601 20 l +1594 27 l +1580 27 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 20 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(DDR) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 40 m +1587 33 l +1596 33 l +1603 40 l +1596 47 l +1587 47 l +h f +Q +1 w +0.063 0.133 0.208 RG +1580 40 m +1587 33 l +1596 33 l +1603 40 l +1596 47 l +1587 47 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1607 40 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(DDR_VRN) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 -320 m +1587 -327 l +1596 -327 l +1603 -320 l +1596 -313 l +1587 -313 l +h f +Q +1580 -320 m +1587 -327 l +1596 -327 l +1603 -320 l +1596 -313 l +1587 -313 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1607 -320 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(DDR_VRP) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 80 m +1580 73 l +1594 73 l +1601 80 l +1594 87 l +1580 87 l +h f +Q +1580 80 m +1580 73 l +1594 73 l +1601 80 l +1594 87 l +1580 87 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 80 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(FCLK_CLK0) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 640 m +1580 633 l +1594 633 l +1601 640 l +1594 647 l +1580 647 l +h f +Q +1580 640 m +1580 633 l +1594 633 l +1601 640 l +1594 647 l +1580 647 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 640 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(FCLK_CLK1) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 620 m +1580 613 l +1594 613 l +1601 620 l +1594 627 l +1580 627 l +h f +Q +1580 620 m +1580 613 l +1594 613 l +1601 620 l +1594 627 l +1580 627 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 620 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(FCLK_CLK2) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 140 m +1580 133 l +1594 133 l +1601 140 l +1594 147 l +1580 147 l +h f +Q +1580 140 m +1580 133 l +1594 133 l +1601 140 l +1594 147 l +1580 147 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 140 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(FCLK_CLK3) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 600 m +1580 593 l +1594 593 l +1601 600 l +1594 607 l +1580 607 l +h f +Q +1580 600 m +1580 593 l +1594 593 l +1601 600 l +1594 607 l +1580 607 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 600 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(FCLK_RESET0_N) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 -420 m +1580 -427 l +1594 -427 l +1601 -420 l +1594 -413 l +1580 -413 l +h f +Q +3 w +0.165 0.369 0.435 RG +1580 -420 m +1580 -427 l +1594 -427 l +1601 -420 l +1594 -413 l +1580 -413 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 -420 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(GPIO_0) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 20 m +-47 27 l +-61 27 l +-61 13 l +-47 13 l +h f +Q +0.063 0.133 0.208 RG +-40 20 m +-47 27 l +-61 27 l +-61 13 l +-47 13 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 20 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-80.04 -4.308 Td +(IRQ_F2P[15:0]) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 200 m +1587 193 l +1596 193 l +1603 200 l +1596 207 l +1587 207 l +h f +Q +1580 200 m +1587 193 l +1596 193 l +1603 200 l +1596 207 l +1587 207 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1607 200 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(MIO[53:0]) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 -280 m +1587 -287 l +1596 -287 l +1603 -280 l +1596 -273 l +1587 -273 l +h f +Q +1 w +1580 -280 m +1587 -287 l +1596 -287 l +1603 -280 l +1596 -273 l +1587 -273 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1607 -280 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(PS_CLK) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 -260 m +1587 -267 l +1596 -267 l +1603 -260 l +1596 -253 l +1587 -253 l +h f +Q +1580 -260 m +1587 -267 l +1596 -267 l +1603 -260 l +1596 -253 l +1587 -253 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1607 -260 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(PS_PORB) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 260 m +1587 253 l +1596 253 l +1603 260 l +1596 267 l +1587 267 l +h f +Q +1580 260 m +1587 253 l +1596 253 l +1603 260 l +1596 267 l +1587 267 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1607 260 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(PS_SRSTB) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 40 m +-47 47 l +-61 47 l +-61 33 l +-47 33 l +h f +Q +-40 40 m +-47 47 l +-61 47 l +-61 33 l +-47 33 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 40 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-73.368 -4.308 Td +(SPI0_MISO_I) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 -80 m +1580 -87 l +1594 -87 l +1601 -80 l +1594 -73 l +1580 -73 l +h f +Q +1580 -80 m +1580 -87 l +1594 -87 l +1601 -80 l +1594 -73 l +1580 -73 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 -80 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI0_MISO_O) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 -60 m +1580 -67 l +1594 -67 l +1601 -60 l +1594 -53 l +1580 -53 l +h f +Q +1580 -60 m +1580 -67 l +1594 -67 l +1601 -60 l +1594 -53 l +1580 -53 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 -60 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI0_MISO_T) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 -90 m +-47 -83 l +-61 -83 l +-61 -97 l +-47 -97 l +h f +Q +-40 -90 m +-47 -83 l +-61 -83 l +-61 -97 l +-47 -97 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 -90 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-73.368 -4.308 Td +(SPI0_MOSI_I) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 -140 m +1580 -147 l +1594 -147 l +1601 -140 l +1594 -133 l +1580 -133 l +h f +Q +1580 -140 m +1580 -147 l +1594 -147 l +1601 -140 l +1594 -133 l +1580 -133 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 -140 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI0_MOSI_O) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 -120 m +1580 -127 l +1594 -127 l +1601 -120 l +1594 -113 l +1580 -113 l +h f +Q +1580 -120 m +1580 -127 l +1594 -127 l +1601 -120 l +1594 -113 l +1580 -113 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 -120 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI0_MOSI_T) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 -120 m +-47 -113 l +-61 -113 l +-61 -127 l +-47 -127 l +h f +Q +-40 -120 m +-47 -113 l +-61 -113 l +-61 -127 l +-47 -127 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 -120 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-74.04 -4.308 Td +(SPI0_SCLK_I) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 360 m +1580 353 l +1594 353 l +1601 360 l +1594 367 l +1580 367 l +h f +Q +1580 360 m +1580 353 l +1594 353 l +1601 360 l +1594 367 l +1580 367 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 360 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI0_SCLK_O) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 380 m +1580 373 l +1594 373 l +1601 380 l +1594 387 l +1580 387 l +h f +Q +1580 380 m +1580 373 l +1594 373 l +1601 380 l +1594 387 l +1580 387 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 380 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI0_SCLK_T) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 100 m +-47 107 l +-61 107 l +-61 93 l +-47 93 l +h f +Q +-40 100 m +-47 107 l +-61 107 l +-61 93 l +-47 93 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 100 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-58.704 -4.308 Td +(SPI0_SS_I) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 400 m +1580 393 l +1594 393 l +1601 400 l +1594 407 l +1580 407 l +h f +Q +1580 400 m +1580 393 l +1594 393 l +1601 400 l +1594 407 l +1580 407 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 400 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI0_SS_O) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 420 m +1580 413 l +1594 413 l +1601 420 l +1594 427 l +1580 427 l +h f +Q +1580 420 m +1580 413 l +1594 413 l +1601 420 l +1594 427 l +1580 427 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 420 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI0_SS_T) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 440 m +1580 433 l +1594 433 l +1601 440 l +1594 447 l +1580 447 l +h f +Q +1580 440 m +1580 433 l +1594 433 l +1601 440 l +1594 447 l +1580 447 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 440 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI0_SS1_O) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 460 m +1580 453 l +1594 453 l +1601 460 l +1594 467 l +1580 467 l +h f +Q +1580 460 m +1580 453 l +1594 453 l +1601 460 l +1594 467 l +1580 467 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 460 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI0_SS2_O) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 200 m +-47 207 l +-61 207 l +-61 193 l +-47 193 l +h f +Q +-40 200 m +-47 207 l +-61 207 l +-61 193 l +-47 193 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 200 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-73.368 -4.308 Td +(SPI1_MISO_I) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 220 m +1580 213 l +1594 213 l +1601 220 l +1594 227 l +1580 227 l +h f +Q +1580 220 m +1580 213 l +1594 213 l +1601 220 l +1594 227 l +1580 227 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 220 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI1_MISO_O) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 240 m +1580 233 l +1594 233 l +1601 240 l +1594 247 l +1580 247 l +h f +Q +1580 240 m +1580 233 l +1594 233 l +1601 240 l +1594 247 l +1580 247 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 240 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI1_MISO_T) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 140 m +-47 147 l +-61 147 l +-61 133 l +-47 133 l +h f +Q +-40 140 m +-47 147 l +-61 147 l +-61 133 l +-47 133 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 140 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-73.368 -4.308 Td +(SPI1_MOSI_I) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 160 m +1580 153 l +1594 153 l +1601 160 l +1594 167 l +1580 167 l +h f +Q +1580 160 m +1580 153 l +1594 153 l +1601 160 l +1594 167 l +1580 167 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 160 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI1_MOSI_O) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 180 m +1580 173 l +1594 173 l +1601 180 l +1594 187 l +1580 187 l +h f +Q +1580 180 m +1580 173 l +1594 173 l +1601 180 l +1594 187 l +1580 187 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 180 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI1_MOSI_T) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 80 m +-47 87 l +-61 87 l +-61 73 l +-47 73 l +h f +Q +-40 80 m +-47 87 l +-61 87 l +-61 73 l +-47 73 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 80 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-74.04 -4.308 Td +(SPI1_SCLK_I) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 100 m +1580 93 l +1594 93 l +1601 100 l +1594 107 l +1580 107 l +h f +Q +1580 100 m +1580 93 l +1594 93 l +1601 100 l +1594 107 l +1580 107 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 100 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI1_SCLK_O) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 120 m +1580 113 l +1594 113 l +1601 120 l +1594 127 l +1580 127 l +h f +Q +1580 120 m +1580 113 l +1594 113 l +1601 120 l +1594 127 l +1580 127 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 120 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI1_SCLK_T) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 260 m +-47 267 l +-61 267 l +-61 253 l +-47 253 l +h f +Q +-40 260 m +-47 267 l +-61 267 l +-61 253 l +-47 253 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 260 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-58.704 -4.308 Td +(SPI1_SS_I) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 280 m +1580 273 l +1594 273 l +1601 280 l +1594 287 l +1580 287 l +h f +Q +1580 280 m +1580 273 l +1594 273 l +1601 280 l +1594 287 l +1580 287 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 280 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI1_SS_O) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 340 m +1580 333 l +1594 333 l +1601 340 l +1594 347 l +1580 347 l +h f +Q +1580 340 m +1580 333 l +1594 333 l +1601 340 l +1594 347 l +1580 347 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 340 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI1_SS_T) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 300 m +1580 293 l +1594 293 l +1601 300 l +1594 307 l +1580 307 l +h f +Q +1580 300 m +1580 293 l +1594 293 l +1601 300 l +1594 307 l +1580 307 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 300 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI1_SS1_O) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 320 m +1580 313 l +1594 313 l +1601 320 l +1594 327 l +1580 327 l +h f +Q +1580 320 m +1580 313 l +1594 313 l +1601 320 l +1594 327 l +1580 327 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 320 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI1_SS2_O) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 120 m +-47 127 l +-61 127 l +-61 113 l +-47 113 l +h f +Q +-40 120 m +-47 127 l +-61 127 l +-61 113 l +-47 113 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 120 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-102.72 -4.308 Td +(S_AXI_GP0_ACLK) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 380 m +-47 387 l +-61 387 l +-61 373 l +-47 373 l +h f +Q +-40 380 m +-47 387 l +-61 387 l +-61 373 l +-47 373 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 380 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-128.052 -4.308 Td +(S_AXI_GP0_ARESETN) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 160 m +-47 167 l +-61 167 l +-61 153 l +-47 153 l +h f +Q +3 w +0.165 0.369 0.435 RG +-40 160 m +-47 167 l +-61 167 l +-61 153 l +-47 153 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 160 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-64.032 -4.308 Td +(S_AXI_HP0) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 180 m +-47 187 l +-61 187 l +-61 173 l +-47 173 l +h f +Q +1 w +0.063 0.133 0.208 RG +-40 180 m +-47 187 l +-61 187 l +-61 173 l +-47 173 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 180 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-102.048 -4.308 Td +(S_AXI_HP0_ACLK) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 60 m +-47 67 l +-61 67 l +-61 53 l +-47 53 l +h f +Q +-40 60 m +-47 67 l +-61 67 l +-61 53 l +-47 53 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 60 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-127.38 -4.308 Td +(S_AXI_HP0_ARESETN) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 480 m +1580 473 l +1594 473 l +1601 480 l +1594 487 l +1580 487 l +h f +Q +3 w +0.165 0.369 0.435 RG +1580 480 m +1580 473 l +1594 473 l +1601 480 l +1594 487 l +1580 487 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 480 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(USBIND_0) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +247 32 m +453 32 l +453 32 l +456 33 l +458 34 l +459 36 l +460 39 l +460 39 l +460 261 l +460 261 l +459 264 l +458 266 l +456 267 l +453 268 l +453 268 l +247 268 l +247 268 l +244 267 l +242 266 l +241 264 l +240 261 l +240 261 l +240 39 l +240 39 l +241 36 l +242 34 l +244 33 l +h f +Q +q +1 0 0 1 360 150 cm +1 0 0 1 -7 -7 cm +14 0 0 -14 0 14 cm /Im0 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 350 30 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-57.03 2.484 Td +(axi_interconnect_hp0) Tj +ET +Q +q +0.255 0.380 0.624 rg +/GSa0 gs +1 0 0 1 350 270 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-44.358 -8.616 Td +(AXI Interconnect) Tj +ET +Q +q +1 0 0 1 251 43 cm +1 0 0 1 -8 -8 cm +16 0 0 -16 0 16 cm /Im1 Do +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +230 51 10 18 re +f +Q +q +1 0 0 1 249.5 60.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 235 60 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 257 60 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S00_AXI) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +460 141 10 18 re +f +Q +q +1 0 0 1 450.5 150.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 465 150 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 443 150 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-41.13 -3.59 Td +(M00_AXI) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +230 71 10 18 re +f +Q +q +1 0 0 1 249.5 80.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 235 80 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 257 80 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S01_AXI) Tj +ET +Q +0.000 0.000 0.000 RG +230 100 m +240 100 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 100 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(ACLK) Tj +ET +Q +230 120 m +240 120 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 120 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(ARESETN) Tj +ET +Q +230 140 m +240 140 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 140 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S00_ACLK) Tj +ET +Q +230 160 m +240 160 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 160 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S00_ARESETN) Tj +ET +Q +230 180 m +240 180 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 180 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M00_ACLK) Tj +ET +Q +230 200 m +240 200 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 200 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M00_ARESETN) Tj +ET +Q +230 220 m +240 220 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 220 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S01_ACLK) Tj +ET +Q +230 240 m +240 240 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 240 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S01_ARESETN) Tj +ET +Q +1 w +0.255 0.380 0.624 RG +247 32 m +453 32 l +S +460 39 m +460.003 38.8889 460.003 38.7778 460 38.6667 c +459.908 34.8927 456.774 31.908 453 32 c +S +460 39 m +460 261 l +S +453 268 m +453.111 268.003 453.222 268.003 453.333 268 c +457.107 267.908 460.092 264.774 460 261 c +S +453 268 m +247 268 l +S +240 261 m +239.997 261.111 239.997 261.222 240 261.333 c +240.092 265.107 243.226 268.092 247 268 c +S +240 261 m +240 39 l +S +247 32 m +246.889 31.9973 246.778 31.9973 246.667 32 c +242.893 32.092 239.908 35.2261 240 39 c +S +q +0.929 0.965 0.996 rg +/GSa0 gs +247 312 m +453 312 l +453 312 l +456 313 l +458 314 l +459 316 l +460 319 l +460 319 l +460 721 l +460 721 l +459 724 l +458 726 l +456 727 l +453 728 l +453 728 l +247 728 l +247 728 l +244 727 l +242 726 l +241 724 l +240 721 l +240 721 l +240 319 l +240 319 l +241 316 l +242 314 l +244 313 l +h f +Q +q +1 0 0 1 360 520 cm +1 0 0 1 -7 -7 cm +14 0 0 -14 0 14 cm /Im0 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 350 310 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-50.358 2.484 Td +(axi_interconnect_0) Tj +ET +Q +q +0.255 0.380 0.624 rg +/GSa0 gs +1 0 0 1 350 730 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-44.358 -8.616 Td +(AXI Interconnect) Tj +ET +Q +q +1 0 0 1 251 323 cm +1 0 0 1 -8 -8 cm +16 0 0 -16 0 16 cm /Im1 Do +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +230 331 10 18 re +f +Q +q +1 0 0 1 249.5 340.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 235 340 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 257 340 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S00_AXI) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +460 451 10 18 re +f +Q +q +1 0 0 1 450.5 460.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 465 460 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 443 460 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-41.13 -3.59 Td +(M00_AXI) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +460 471 10 18 re +f +Q +q +1 0 0 1 450.5 480.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 465 480 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 443 480 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-41.13 -3.59 Td +(M01_AXI) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +460 491 10 18 re +f +Q +q +1 0 0 1 450.5 500.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 465 500 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 443 500 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-41.13 -3.59 Td +(M02_AXI) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +460 511 10 18 re +f +Q +q +1 0 0 1 450.5 520.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 465 520 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 443 520 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-41.13 -3.59 Td +(M03_AXI) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +460 531 10 18 re +f +Q +q +1 0 0 1 450.5 540.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 465 540 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 443 540 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-41.13 -3.59 Td +(M04_AXI) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +460 551 10 18 re +f +Q +q +1 0 0 1 450.5 560.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 465 560 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 443 560 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-41.13 -3.59 Td +(M05_AXI) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +460 571 10 18 re +f +Q +q +1 0 0 1 450.5 580.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 465 580 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 443 580 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-41.13 -3.59 Td +(M06_AXI) Tj +ET +Q +3 w +0.000 0.000 0.000 RG +230 360 m +240 360 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 360 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(ACLK) Tj +ET +Q +230 380 m +240 380 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 380 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(ARESETN) Tj +ET +Q +230 400 m +240 400 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 400 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S00_ACLK) Tj +ET +Q +230 420 m +240 420 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 420 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S00_ARESETN) Tj +ET +Q +230 440 m +240 440 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 440 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M00_ACLK) Tj +ET +Q +230 460 m +240 460 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 460 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M00_ARESETN) Tj +ET +Q +230 480 m +240 480 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 480 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M01_ACLK) Tj +ET +Q +230 500 m +240 500 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 500 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M01_ARESETN) Tj +ET +Q +230 520 m +240 520 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 520 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M02_ACLK) Tj +ET +Q +230 540 m +240 540 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 540 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M02_ARESETN) Tj +ET +Q +230 560 m +240 560 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 560 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M03_ACLK) Tj +ET +Q +230 580 m +240 580 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 580 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M03_ARESETN) Tj +ET +Q +230 600 m +240 600 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 600 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M04_ACLK) Tj +ET +Q +230 620 m +240 620 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 620 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M04_ARESETN) Tj +ET +Q +230 640 m +240 640 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 640 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M05_ACLK) Tj +ET +Q +230 660 m +240 660 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 660 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M05_ARESETN) Tj +ET +Q +230 680 m +240 680 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 680 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M06_ACLK) Tj +ET +Q +230 700 m +240 700 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 700 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M06_ARESETN) Tj +ET +Q +1 w +0.255 0.380 0.624 RG +247 312 m +453 312 l +S +460 319 m +460.003 318.889 460.003 318.778 460 318.667 c +459.908 314.893 456.774 311.908 453 312 c +S +460 319 m +460 721 l +S +453 728 m +453.111 728.003 453.222 728.003 453.333 728 c +457.107 727.908 460.092 724.774 460 721 c +S +453 728 m +247 728 l +S +240 721 m +239.997 721.111 239.997 721.222 240 721.333 c +240.092 725.107 243.226 728.092 247 728 c +S +240 721 m +240 319 l +S +247 312 m +246.889 311.997 246.778 311.997 246.667 312 c +242.893 312.092 239.908 315.226 240 319 c +S +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 220 m +-47 227 l +-61 227 l +-61 213 l +-47 213 l +h f +Q +0.063 0.133 0.208 RG +-40 220 m +-47 227 l +-61 227 l +-61 213 l +-47 213 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 220 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-40.68 -4.308 Td +(bus_clk) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 240 m +-47 247 l +-61 247 l +-61 233 l +-47 233 l +h f +Q +-40 240 m +-47 247 l +-61 247 l +-61 233 l +-47 233 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 240 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-46.02 -4.308 Td +(bus_rstn) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 -50 m +-47 -43 l +-61 -43 l +-61 -57 l +-47 -57 l +h f +Q +-40 -50 m +-47 -43 l +-61 -43 l +-61 -57 l +-47 -57 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 -50 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-28.008 -4.308 Td +(clk40) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 280 m +-47 287 l +-61 287 l +-61 273 l +-47 273 l +h f +Q +-40 280 m +-47 287 l +-61 287 l +-61 273 l +-47 273 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 280 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-54.684 -4.308 Td +(clk40_rstn) Tj +ET +Q +q +0.667 0.769 0.969 rg +/GSa0 gs +207 772 m +493 772 l +493 772 l +496 773 l +498 774 l +499 776 l +500 779 l +500 779 l +500 981 l +500 981 l +499 984 l +498 986 l +496 987 l +493 988 l +493 988 l +207 988 l +207 988 l +204 987 l +202 986 l +201 984 l +200 981 l +200 981 l +200 779 l +200 779 l +201 776 l +202 774 l +204 773 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 350 770 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-11.67 2.484 Td +(dma) Tj +ET +Q +q +1 0 0 1 211 783 cm +1 0 0 1 -8 -8 cm +16 0 0 -16 0 16 cm /Im1 Do +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +500 831 10 18 re +f +Q +q +1 0 0 1 490.5 840.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 505 840 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im5 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 483 840 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-56.69 -3.59 Td +(o_cvita_dma) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +500 851 10 18 re +f +Q +q +1 0 0 1 490.5 860.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 505 860 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 483 860 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-77.24 -3.59 Td +(M_AXI_RX_DMA) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +500 871 10 18 re +f +Q +q +1 0 0 1 490.5 880.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 505 880 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 483 880 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-76.13 -3.59 Td +(M_AXI_TX_DMA) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +190 791 10 18 re +f +Q +q +1 0 0 1 209.5 800.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 195 800 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im6 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 217 800 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(i_cvita_dma) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +190 811 10 18 re +f +Q +q +1 0 0 1 209.5 820.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 195 820 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 217 820 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(s_axi_rx_dmac) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +190 831 10 18 re +f +Q +q +1 0 0 1 209.5 840.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 195 840 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 217 840 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(s_axi_tx_dmac) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +190 851 10 18 re +f +Q +q +1 0 0 1 209.5 860.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 195 860 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 217 860 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(s_axi_regfile) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +190 871 10 18 re +f +Q +q +1 0 0 1 209.5 880.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 195 880 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 217 880 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(s_axi_dma_rx_mapper) Tj +ET +Q +3 w +0.000 0.000 0.000 RG +190 900 m +200 900 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 202 900 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(bus_clk) Tj +ET +Q +190 920 m +200 920 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 202 920 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(bus_rstn) Tj +ET +Q +190 940 m +200 940 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 202 940 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(clk40) Tj +ET +Q +190 960 m +200 960 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 202 960 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(clk40_rstn) Tj +ET +Q +510 900 m +500 900 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 498 900 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-25 -3.59 Td +(rx_irq) Tj +ET +Q +510 920 m +500 920 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 498 920 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-24.45 -3.59 Td +(tx_irq) Tj +ET +Q +1 w +0.255 0.380 0.624 RG +207 772 m +493 772 l +S +500 779 m +500.003 778.889 500.003 778.778 500 778.667 c +499.908 774.893 496.774 771.908 493 772 c +S +500 779 m +500 981 l +S +493 988 m +493.111 988.003 493.222 988.003 493.333 988 c +497.107 987.908 500.092 984.774 500 981 c +S +493 988 m +207 988 l +S +200 981 m +199.997 981.111 199.997 981.222 200 981.333 c +200.092 985.107 203.226 988.092 207 988 c +S +200 981 m +200 779 l +S +207 772 m +206.889 771.997 206.778 771.997 206.667 772 c +202.893 772.092 199.908 775.226 200 779 c +S +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 300 m +-47 307 l +-61 307 l +-61 293 l +-47 293 l +h f +Q +3 w +0.165 0.369 0.435 RG +-40 300 m +-47 307 l +-61 307 l +-61 293 l +-47 293 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 300 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-64.02 -4.308 Td +(i_cvita_dma) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 500 m +1580 493 l +1594 493 l +1601 500 l +1594 507 l +1580 507 l +h f +Q +1580 500 m +1580 493 l +1594 493 l +1601 500 l +1594 507 l +1580 507 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 500 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(m_axi_eth_dma) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 520 m +1580 513 l +1594 513 l +1601 520 l +1594 527 l +1580 527 l +h f +Q +1580 520 m +1580 513 l +1594 513 l +1601 520 l +1594 527 l +1580 527 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 520 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(m_axi_net) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 540 m +1580 533 l +1594 533 l +1601 540 l +1594 547 l +1580 547 l +h f +Q +1580 540 m +1580 533 l +1594 533 l +1601 540 l +1594 547 l +1580 547 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 540 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(m_axi_xbar) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 560 m +1580 553 l +1594 553 l +1601 560 l +1594 567 l +1580 567 l +h f +Q +1580 560 m +1580 553 l +1594 553 l +1601 560 l +1594 567 l +1580 567 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 560 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(o_cvita_dma) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +767 -440 m +1133 -440 l +1133 -440 l +1136 -439 l +1138 -438 l +1139 -436 l +1140 -433 l +1140 -433 l +1140 493 l +1140 493 l +1139 496 l +1138 498 l +1136 499 l +1133 500 l +1133 500 l +767 500 l +767 500 l +764 499 l +762 498 l +761 496 l +760 493 l +760 493 l +760 -433 l +760 -433 l +761 -436 l +762 -438 l +764 -439 l +h f +Q +q +1 0 0 1 975 30 cm +1 0 0 1 -50 -15 cm +100 0 0 -30 0 30 cm /Im7 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 950 -442 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-61.356 2.484 Td +(processing_system7_0) Tj +ET +Q +q +0.255 0.380 0.624 rg +/GSa0 gs +1 0 0 1 950 502 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-73.02 -8.616 Td +(ZYNQ7 Processing System) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +1140 -429 10 18 re +f +Q +q +1 0 0 1 1130.5 -419.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 1145 -420 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im5 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1123 -420 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-36.13 -3.59 Td +(GPIO_0) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +1140 -409 10 18 re +f +Q +q +1 0 0 1 1130.5 -399.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 1145 -400 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im5 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1123 -400 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-21.66 -3.59 Td +(DDR) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +1140 -389 10 138 re +f +Q +q +1 0 0 1 1130.5 -379.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im8 Do +Q +q +1 0 0 1 1145 -380 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im5 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1123 -380 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-45.57 -3.59 Td +(FIXED_IO) Tj +ET +Q +0.000 0.000 0.000 RG +1150 -360 m +1140 -360 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1123 -365 m +1118 -360 l +1123 -355 l +1128 -360 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -360 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-43.91 -3.59 Td +(MIO[53:0]) Tj +ET +Q +2 w +1150 -340 m +1140 -340 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1123 -345 m +1118 -340 l +1123 -335 l +1128 -340 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -340 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-48.33 -3.59 Td +(DDR_VRN) Tj +ET +Q +1150 -320 m +1140 -320 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1123 -325 m +1118 -320 l +1123 -315 l +1128 -320 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -320 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-47.78 -3.59 Td +(DDR_VRP) Tj +ET +Q +1150 -300 m +1140 -300 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1123 -305 m +1118 -300 l +1123 -295 l +1128 -300 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -300 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-52.24 -3.59 Td +(PS_SRSTB) Tj +ET +Q +1150 -280 m +1140 -280 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1123 -285 m +1118 -280 l +1123 -275 l +1128 -280 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -280 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-38.35 -3.59 Td +(PS_CLK) Tj +ET +Q +1150 -260 m +1140 -260 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1123 -265 m +1118 -260 l +1123 -255 l +1128 -260 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -260 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-47.24 -3.59 Td +(PS_PORB) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +1140 -249 10 298 re +f +Q +q +1 0 0 1 1130.5 -239.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im8 Do +Q +q +1 0 0 1 1145 -240 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im5 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1123 -240 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-27.24 -3.59 Td +(SPI_0) Tj +ET +Q +1150 -220 m +1140 -220 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1127 -225 m +1119 -220 l +1127 -215 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -220 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-61.7 -3.59 Td +(SPI0_SCLK_I) Tj +ET +Q +1150 -200 m +1140 -200 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 -205 m +1127 -200 l +1119 -195 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -200 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-66.7 -3.59 Td +(SPI0_SCLK_O) Tj +ET +Q +1150 -180 m +1140 -180 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 -185 m +1127 -180 l +1119 -175 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -180 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-65.03 -3.59 Td +(SPI0_SCLK_T) Tj +ET +Q +1150 -160 m +1140 -160 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1127 -165 m +1119 -160 l +1127 -155 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -160 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-61.14 -3.59 Td +(SPI0_MOSI_I) Tj +ET +Q +1150 -140 m +1140 -140 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 -145 m +1127 -140 l +1119 -135 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -140 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-66.14 -3.59 Td +(SPI0_MOSI_O) Tj +ET +Q +1150 -120 m +1140 -120 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 -125 m +1127 -120 l +1119 -115 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -120 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-64.47 -3.59 Td +(SPI0_MOSI_T) Tj +ET +Q +1150 -100 m +1140 -100 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1127 -105 m +1119 -100 l +1127 -95 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -100 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-61.14 -3.59 Td +(SPI0_MISO_I) Tj +ET +Q +1150 -80 m +1140 -80 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 -85 m +1127 -80 l +1119 -75 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -80 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-66.14 -3.59 Td +(SPI0_MISO_O) Tj +ET +Q +1150 -60 m +1140 -60 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 -65 m +1127 -60 l +1119 -55 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -60 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-64.47 -3.59 Td +(SPI0_MISO_T) Tj +ET +Q +1150 -40 m +1140 -40 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1127 -45 m +1119 -40 l +1127 -35 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -40 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-48.92 -3.59 Td +(SPI0_SS_I) Tj +ET +Q +1150 -20 m +1140 -20 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 -25 m +1127 -20 l +1119 -15 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -20 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-53.92 -3.59 Td +(SPI0_SS_O) Tj +ET +Q +1150 0 m +1140 0 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 -5 m +1127 0 l +1119 5 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 0 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-59.48 -3.59 Td +(SPI0_SS1_O) Tj +ET +Q +1150 20 m +1140 20 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 15 m +1127 20 l +1119 25 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 20 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-59.48 -3.59 Td +(SPI0_SS2_O) Tj +ET +Q +1150 40 m +1140 40 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 35 m +1127 40 l +1119 45 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 40 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-52.25 -3.59 Td +(SPI0_SS_T) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +1140 51 10 298 re +f +Q +q +1 0 0 1 1130.5 60.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im8 Do +Q +q +1 0 0 1 1145 60 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im5 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1123 60 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-27.24 -3.59 Td +(SPI_1) Tj +ET +Q +1150 80 m +1140 80 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1127 75 m +1119 80 l +1127 85 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 80 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-61.7 -3.59 Td +(SPI1_SCLK_I) Tj +ET +Q +1150 100 m +1140 100 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 95 m +1127 100 l +1119 105 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 100 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-66.7 -3.59 Td +(SPI1_SCLK_O) Tj +ET +Q +1150 120 m +1140 120 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 115 m +1127 120 l +1119 125 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 120 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-65.03 -3.59 Td +(SPI1_SCLK_T) Tj +ET +Q +1150 140 m +1140 140 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1127 135 m +1119 140 l +1127 145 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 140 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-61.14 -3.59 Td +(SPI1_MOSI_I) Tj +ET +Q +1150 160 m +1140 160 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 155 m +1127 160 l +1119 165 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 160 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-66.14 -3.59 Td +(SPI1_MOSI_O) Tj +ET +Q +1150 180 m +1140 180 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 175 m +1127 180 l +1119 185 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 180 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-64.47 -3.59 Td +(SPI1_MOSI_T) Tj +ET +Q +1150 200 m +1140 200 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1127 195 m +1119 200 l +1127 205 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 200 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-61.14 -3.59 Td +(SPI1_MISO_I) Tj +ET +Q +1150 220 m +1140 220 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 215 m +1127 220 l +1119 225 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 220 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-66.14 -3.59 Td +(SPI1_MISO_O) Tj +ET +Q +1150 240 m +1140 240 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 235 m +1127 240 l +1119 245 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 240 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-64.47 -3.59 Td +(SPI1_MISO_T) Tj +ET +Q +1150 260 m +1140 260 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1127 255 m +1119 260 l +1127 265 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 260 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-48.92 -3.59 Td +(SPI1_SS_I) Tj +ET +Q +1150 280 m +1140 280 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 275 m +1127 280 l +1119 285 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 280 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-53.92 -3.59 Td +(SPI1_SS_O) Tj +ET +Q +1150 300 m +1140 300 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 295 m +1127 300 l +1119 305 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 300 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-59.48 -3.59 Td +(SPI1_SS1_O) Tj +ET +Q +1150 320 m +1140 320 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 315 m +1127 320 l +1119 325 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 320 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-59.48 -3.59 Td +(SPI1_SS2_O) Tj +ET +Q +1150 340 m +1140 340 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 335 m +1127 340 l +1119 345 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 340 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-52.25 -3.59 Td +(SPI1_SS_T) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +1140 351 10 18 re +f +Q +q +1 0 0 1 1130.5 360.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 1145 360 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im5 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1123 360 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-48.9 -3.59 Td +(USBIND_0) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +750 -79 10 18 re +f +Q +q +1 0 0 1 769.5 -69.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 755 -70 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im6 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 777 -70 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S_AXI_HP0_FIFO_CTRL) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +750 -59 10 18 re +f +Q +q +1 0 0 1 769.5 -49.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 755 -50 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im6 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 777 -50 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S_AXI_HP1_FIFO_CTRL) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +750 -39 10 18 re +f +Q +q +1 0 0 1 769.5 -29.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 755 -30 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im6 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 777 -30 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S_AXI_HP2_FIFO_CTRL) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +1140 371 10 18 re +f +Q +q +1 0 0 1 1130.5 380.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 1145 380 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1123 380 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-55.58 -3.59 Td +(M_AXI_GP0) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +750 -19 10 18 re +f +Q +q +1 0 0 1 769.5 -9.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 755 -10 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 777 -10 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S_AXI_HP0) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +750 1 10 18 re +f +Q +q +1 0 0 1 769.5 10.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 755 10 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 777 10 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S_AXI_HP1) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +750 21 10 18 re +f +Q +q +1 0 0 1 769.5 30.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 755 30 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 777 30 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S_AXI_HP2) Tj +ET +Q +3 w +750 50 m +760 50 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 762 50 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M_AXI_GP0_ACLK) Tj +ET +Q +750 70 m +760 70 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 762 70 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S_AXI_HP0_ACLK) Tj +ET +Q +750 90 m +760 90 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 762 90 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S_AXI_HP1_ACLK) Tj +ET +Q +750 110 m +760 110 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 762 110 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S_AXI_HP2_ACLK) Tj +ET +Q +5 w +750 130 m +760 130 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 762 130 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(IRQ_F2P[0:0]) Tj +ET +Q +3 w +1150 400 m +1140 400 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1138 400 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-56.13 -3.59 Td +(FCLK_CLK0) Tj +ET +Q +1150 420 m +1140 420 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1138 420 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-56.13 -3.59 Td +(FCLK_CLK1) Tj +ET +Q +1150 440 m +1140 440 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1138 440 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-56.13 -3.59 Td +(FCLK_CLK2) Tj +ET +Q +1150 460 m +1140 460 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1138 460 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-56.13 -3.59 Td +(FCLK_CLK3) Tj +ET +Q +1146 480 m +1146 478.343 1144.66 477 1143 477 c +1141.34 477 1140 478.343 1140 480 c +1140 481.657 1141.34 483 1143 483 c +1144.66 483 1146 481.657 1146 480 c +S +1150 480 m +1146 480 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1138 480 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-82.8 -3.59 Td +(FCLK_RESET0_N) Tj +ET +Q +1 w +0.255 0.380 0.624 RG +767 -440 m +1133 -440 l +S +1140 -433 m +1140 -433.111 1140 -433.222 1140 -433.333 c +1139.91 -437.107 1136.77 -440.092 1133 -440 c +S +1140 -433 m +1140 493 l +S +1133 500 m +1133.11 500.003 1133.22 500.003 1133.33 500 c +1137.11 499.908 1140.09 496.774 1140 493 c +S +1133 500 m +767 500 l +S +760 493 m +759.997 493.111 759.997 493.222 760 493.333 c +760.092 497.107 763.226 500.092 767 500 c +S +760 493 m +760 -433 l +S +767 -440 m +766.889 -440.003 766.778 -440.003 766.667 -440 c +762.893 -439.908 759.908 -436.774 760 -433 c +S +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 320 m +-47 327 l +-61 327 l +-61 313 l +-47 313 l +h f +Q +3 w +0.165 0.369 0.435 RG +-40 320 m +-47 327 l +-61 327 l +-61 313 l +-47 313 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 320 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-110.712 -4.308 Td +(s_axi_eth_descriptor) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +877 1910 m +1023 1910 l +1023 1910 l +1026 1911 l +1028 1912 l +1029 1914 l +1030 1917 l +1030 1917 l +1030 2103 l +1030 2103 l +1029 2106 l +1028 2108 l +1026 2109 l +1023 2110 l +1023 2110 l +877 2110 l +877 2110 l +874 2109 l +872 2108 l +871 2106 l +870 2103 l +870 2103 l +870 1917 l +870 1917 l +871 1914 l +872 1912 l +874 1911 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 950 1908 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-28.68 2.484 Td +(xlconcat_0) Tj +ET +Q +q +0.255 0.380 0.624 rg +/GSa0 gs +1 0 0 1 950 2112 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-19.008 -8.616 Td +(Concat) Tj +ET +Q +5 w +0.000 0.000 0.000 RG +860 1930 m +870 1930 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 872 1930 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(In0[7:0]) Tj +ET +Q +860 1950 m +870 1950 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 872 1950 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(In1[0:0]) Tj +ET +Q +860 1970 m +870 1970 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 872 1970 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(In2[0:0]) Tj +ET +Q +860 1990 m +870 1990 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 872 1990 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(In3[0:0]) Tj +ET +Q +860 2010 m +870 2010 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 872 2010 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(In4[0:0]) Tj +ET +Q +860 2030 m +870 2030 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 872 2030 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(In5[0:0]) Tj +ET +Q +860 2050 m +870 2050 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 872 2050 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(In6[0:0]) Tj +ET +Q +860 2070 m +870 2070 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 872 2070 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(In7[0:0]) Tj +ET +Q +860 2090 m +870 2090 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 872 2090 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(In8[0:0]) Tj +ET +Q +1040 2010 m +1030 2010 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1028 2010 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-44.48 -3.59 Td +(dout[15:0]) Tj +ET +Q +1 w +0.255 0.380 0.624 RG +877 1910 m +1023 1910 l +S +1030 1917 m +1030 1916.89 1030 1916.78 1030 1916.67 c +1029.91 1912.89 1026.77 1909.91 1023 1910 c +S +1030 1917 m +1030 2103 l +S +1023 2110 m +1023.11 2110 1023.22 2110 1023.33 2110 c +1027.11 2109.91 1030.09 2106.77 1030 2103 c +S +1023 2110 m +877 2110 l +S +870 2103 m +869.997 2103.11 869.997 2103.22 870 2103.33 c +870.092 2107.11 873.226 2110.09 877 2110 c +S +870 2103 m +870 1917 l +S +877 1910 m +876.889 1910 876.778 1910 876.667 1910 c +872.893 1910.09 869.908 1913.23 870 1917 c +S +q +0.929 0.965 0.996 rg +/GSa0 gs +277 1140 m +423 1140 l +423 1140 l +426 1141 l +428 1142 l +429 1144 l +430 1147 l +430 1147 l +430 1173 l +430 1173 l +429 1176 l +428 1178 l +426 1179 l +423 1180 l +423 1180 l +277 1180 l +277 1180 l +274 1179 l +272 1178 l +271 1176 l +270 1173 l +270 1173 l +270 1147 l +270 1147 l +271 1144 l +272 1142 l +274 1141 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 350 1138 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-23.004 2.484 Td +(xlslice_2) Tj +ET +Q +q +0.255 0.380 0.624 rg +/GSa0 gs +1 0 0 1 350 1182 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-13.002 -8.616 Td +(Slice) Tj +ET +Q +5 w +0.000 0.000 0.000 RG +260 1160 m +270 1160 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 272 1160 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(Din[15:0]) Tj +ET +Q +440 1160 m +430 1160 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 428 1160 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-40.58 -3.59 Td +(Dout[7:0]) Tj +ET +Q +1 w +0.255 0.380 0.624 RG +277 1140 m +423 1140 l +S +430 1147 m +430.003 1146.89 430.003 1146.78 430 1146.67 c +429.908 1142.89 426.774 1139.91 423 1140 c +S +430 1147 m +430 1173 l +S +423 1180 m +423.111 1180 423.222 1180 423.333 1180 c +427.107 1179.91 430.092 1176.77 430 1173 c +S +423 1180 m +277 1180 l +S +270 1173 m +269.997 1173.11 269.997 1173.22 270 1173.33 c +270.092 1177.11 273.226 1180.09 277 1180 c +S +270 1173 m +270 1147 l +S +277 1140 m +276.889 1140 276.778 1140 276.667 1140 c +272.893 1140.09 269.908 1143.23 270 1147 c +S +3 w +0.063 0.133 0.208 RG +-40 20 m +10 20 l +10 1160 l +260 1160 l +S +1 w +-40 40 m +-20 40 l +-20 -140 l +720 -140 l +720 590 l +1210 590 l +1210 -100 l +1150 -100 l +S +-40 -90 m +-10 -90 l +-10 -130 l +700 -130 l +700 600 l +1240 600 l +1240 -160 l +1150 -160 l +S +-40 -120 m +670 -120 l +670 610 l +1250 610 l +1250 -220 l +1150 -220 l +S +-40 100 m +0 100 l +0 -110 l +630 -110 l +630 620 l +1230 620 l +1230 -40 l +1150 -40 l +S +-40 200 m +40 200 l +40 -100 l +690 -100 l +690 570 l +1180 570 l +1180 200 l +1150 200 l +S +-40 140 m +30 140 l +30 -90 l +660 -90 l +660 580 l +1190 580 l +1190 140 l +1150 140 l +S +-40 80 m +20 80 l +20 -80 l +590 -80 l +590 630 l +1220 630 l +1220 80 l +1150 80 l +S +-40 260 m +80 260 l +80 -70 l +570 -70 l +570 640 l +1200 640 l +1200 260 l +1150 260 l +S +-40 120 m +60 120 l +60 360 l +230 360 l +S +-40 380 m +230 380 l +S +230 220 m +110 220 l +110 -60 l +710 -60 l +710 70 l +750 70 l +S +110 180 m +230 180 l +S +-40 180 m +110 180 l +S +110 140 m +230 140 l +S +110 100 m +230 100 l +S +q +0.063 0.133 0.208 rg +/GSa0 gs +108 178 5 5 re +f +Q +q +0.063 0.133 0.208 rg +/GSa0 gs +108 138 5 5 re +f +Q +q +0.063 0.133 0.208 rg +/GSa0 gs +108 98 5 5 re +f +Q +-40 60 m +70 60 l +70 240 l +230 240 l +S +70 120 m +230 120 l +S +70 170 m +210 170 l +210 160 l +230 160 l +S +70 200 m +230 200 l +S +q +0.063 0.133 0.208 rg +/GSa0 gs +68 118 5 5 re +f +Q +q +0.063 0.133 0.208 rg +/GSa0 gs +68 168 5 5 re +f +Q +q +0.063 0.133 0.208 rg +/GSa0 gs +68 198 5 5 re +f +Q +4 w +0.255 0.380 0.624 RG +-40 160 m +90 160 l +90 60 l +230 60 l +S +230 340 m +150 340 l +150 -20 l +620 -20 l +620 550 l +1170 550 l +1170 380 l +1150 380 l +S +470 460 m +650 460 l +650 530 l +1290 530 l +1290 500 l +1580 500 l +S +470 480 m +610 480 l +610 540 l +1330 540 l +1330 520 l +1580 520 l +S +470 500 m +580 500 l +580 560 l +1380 560 l +1380 540 l +1580 540 l +S +190 880 m +120 880 l +120 -40 l +540 -40 l +540 520 l +470 520 l +S +190 840 m +130 840 l +130 -30 l +560 -30 l +560 560 l +470 560 l +S +470 150 m +580 150 l +580 -10 l +750 -10 l +S +1 w +0.063 0.133 0.208 RG +-40 220 m +30 220 l +30 900 l +190 900 l +S +30 560 m +230 560 l +S +q +0.063 0.133 0.208 rg +/GSa0 gs +28 558 5 5 re +f +Q +-40 240 m +0 240 l +0 920 l +190 920 l +S +0 580 m +230 580 l +S +q +0.063 0.133 0.208 rg +/GSa0 gs +-2 578 5 5 re +f +Q +-40 -50 m +50 -50 l +50 940 l +190 940 l +S +50 -50 m +680 -50 l +680 110 l +750 110 l +S +680 50 m +750 50 l +S +680 90 m +750 90 l +S +q +0.063 0.133 0.208 rg +/GSa0 gs +678 48 5 5 re +f +Q +q +0.063 0.133 0.208 rg +/GSa0 gs +678 88 5 5 re +f +Q +50 400 m +230 400 l +S +50 440 m +230 440 l +S +50 480 m +230 480 l +S +50 520 m +230 520 l +S +50 600 m +230 600 l +S +50 640 m +230 640 l +S +50 680 m +230 680 l +S +q +0.063 0.133 0.208 rg +/GSa0 gs +48 -52 5 5 re +f +Q +q +0.063 0.133 0.208 rg +/GSa0 gs +48 398 5 5 re +f +Q +q +0.063 0.133 0.208 rg +/GSa0 gs +48 438 5 5 re +f +Q +q +0.063 0.133 0.208 rg +/GSa0 gs +48 478 5 5 re +f +Q +q +0.063 0.133 0.208 rg +/GSa0 gs +48 518 5 5 re +f +Q +q +0.063 0.133 0.208 rg +/GSa0 gs +48 598 5 5 re +f +Q +q +0.063 0.133 0.208 rg +/GSa0 gs +48 638 5 5 re +f +Q +q +0.063 0.133 0.208 rg +/GSa0 gs +48 678 5 5 re +f +Q +-40 280 m +-20 280 l +-20 960 l +190 960 l +S +-20 420 m +230 420 l +S +-20 460 m +230 460 l +S +-20 500 m +230 500 l +S +-20 540 m +230 540 l +S +-20 620 m +230 620 l +S +-20 660 m +230 660 l +S +-20 700 m +230 700 l +S +q +0.063 0.133 0.208 rg +/GSa0 gs +-22 418 5 5 re +f +Q +q +0.063 0.133 0.208 rg +/GSa0 gs +-22 458 5 5 re +f +Q +q +0.063 0.133 0.208 rg +/GSa0 gs +-22 498 5 5 re +f +Q +q +0.063 0.133 0.208 rg +/GSa0 gs +-22 538 5 5 re +f +Q +q +0.063 0.133 0.208 rg +/GSa0 gs +-22 618 5 5 re +f +Q +q +0.063 0.133 0.208 rg +/GSa0 gs +-22 658 5 5 re +f +Q +q +0.063 0.133 0.208 rg +/GSa0 gs +-22 698 5 5 re +f +Q +1150 -340 m +1380 -340 l +1380 40 l +1580 40 l +S +1150 -320 m +1580 -320 l +S +4 w +0.255 0.380 0.624 RG +510 860 m +600 860 l +600 10 l +750 10 l +S +510 880 m +640 880 l +640 30 l +750 30 l +S +1 w +0.063 0.133 0.208 RG +510 920 m +540 920 l +540 1970 l +860 1970 l +S +4 w +0.255 0.380 0.624 RG +-40 300 m +-10 300 l +-10 800 l +190 800 l +S +3 w +0.063 0.133 0.208 RG +1150 -360 m +1390 -360 l +1390 200 l +1580 200 l +S +4 w +0.255 0.380 0.624 RG +510 840 m +620 840 l +620 650 l +1400 650 l +1400 560 l +1580 560 l +S +1150 -400 m +1400 -400 l +1400 20 l +1580 20 l +S +1 w +0.063 0.133 0.208 RG +1150 400 m +1300 400 l +1300 80 l +1580 80 l +S +1150 420 m +1280 420 l +1280 640 l +1580 640 l +S +1150 440 m +1270 440 l +1270 620 l +1580 620 l +S +1150 460 m +1260 460 l +1260 140 l +1580 140 l +S +1150 480 m +1260 480 l +1260 600 l +1580 600 l +S +4 w +0.255 0.380 0.624 RG +1150 -420 m +1580 -420 l +S +1 w +0.063 0.133 0.208 RG +1150 -80 m +1580 -80 l +S +1150 -60 m +1580 -60 l +S +1150 -140 m +1580 -140 l +S +1150 -120 m +1580 -120 l +S +1150 -200 m +1360 -200 l +1360 360 l +1580 360 l +S +1150 -180 m +1350 -180 l +1350 380 l +1580 380 l +S +1150 -20 m +1340 -20 l +1340 400 l +1580 400 l +S +1150 40 m +1320 40 l +1320 420 l +1580 420 l +S +1150 0 m +1330 0 l +1330 440 l +1580 440 l +S +1150 20 m +1310 20 l +1310 460 l +1580 460 l +S +1150 220 m +1580 220 l +S +1150 240 m +1580 240 l +S +1150 160 m +1580 160 l +S +1150 180 m +1580 180 l +S +1150 100 m +1580 100 l +S +1150 120 m +1580 120 l +S +1150 280 m +1580 280 l +S +1150 340 m +1580 340 l +S +1150 300 m +1580 300 l +S +1150 320 m +1580 320 l +S +4 w +0.255 0.380 0.624 RG +1150 360 m +1290 360 l +1290 480 l +1580 480 l +S +1 w +0.063 0.133 0.208 RG +1150 -280 m +1580 -280 l +S +1150 -260 m +1580 -260 l +S +1150 -300 m +1370 -300 l +1370 260 l +1580 260 l +S +510 900 m +680 900 l +680 1950 l +860 1950 l +S +4 w +0.255 0.380 0.624 RG +-40 320 m +100 320 l +100 80 l +230 80 l +S +190 860 m +140 860 l +140 -10 l +550 -10 l +550 580 l +470 580 l +S +190 820 m +160 820 l +160 0 l +530 0 l +530 540 l +470 540 l +S +3 w +0.063 0.133 0.208 RG +750 130 m +730 130 l +730 660 l +1170 660 l +1170 2010 l +1040 2010 l +S +440 1160 m +590 1160 l +590 1930 l +860 1930 l +S +endstream +endobj +3 0 obj +<< + /Type /Pages + /Kids + [ + 10 0 R + ] + /Count 1 + /ProcSet [ /PDF /Text /ImageB /ImageC ] +>> +endobj +6 0 obj +<< + /GS << /Type /ExtGState + /LC 0 + /LJ 0 + /ML 4.0 + /ca 1.0 + /CA 1.0 + /AIS false + /SMask /None + >> + /GSa0 << /Type /ExtGState /ca 1 >> + /GSA0 << /Type /ExtGState /CA 1 >> +>> +endobj +23 0 obj +<< + /Title (axi_interconnect_0 axi_interconnect_0_imp) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 159 421 226 546] + /Parent 22 0 R + /Next 24 0 R +>> +endobj +24 0 obj +<< + /Title (axi_interconnect_hp0 axi_interconnect_hp0_imp) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 159 550 226 624] + /Parent 22 0 R + /Prev 23 0 R + /Next 25 0 R +>> +endobj +25 0 obj +<< + /Title (dma dma_imp) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 148 352 238 417] + /Parent 22 0 R + /Prev 24 0 R + /Next 26 0 R +>> +endobj +26 0 obj +<< + /Title (processing_system7_0 e320_ps_bd_processing_system7_0_0) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 305 485 416 756] + /Parent 22 0 R + /Prev 25 0 R + /Next 27 0 R +>> +endobj +27 0 obj +<< + /Title (xlconcat_0 e320_ps_bd_xlconcat_0_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 335 35 386 99] + /Parent 22 0 R + /Prev 26 0 R + /Next 28 0 R +>> +endobj +28 0 obj +<< + /Title (xlslice_2 e320_ps_bd_xlslice_2_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 168 295 218 314] + /Parent 22 0 R + /Prev 27 0 R +>> +endobj +22 0 obj +<< + /Title (instances) + /C [0.0 0.4 0.0] + /F 1 + /Parent 21 0 R + /First 23 0 R + /Last 28 0 R + /Count 6 + /Next 29 0 R +>> +endobj +30 0 obj +<< + /Title (DDR output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 620 551 626] + /Parent 29 0 R + /Next 31 0 R +>> +endobj +31 0 obj +<< + /Title (DDR_VRN inout) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 615 560 620] + /Parent 29 0 R + /Prev 30 0 R + /Next 32 0 R +>> +endobj +32 0 obj +<< + /Title (DDR_VRP inout) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 716 560 720] + /Parent 29 0 R + /Prev 31 0 R + /Next 33 0 R +>> +endobj +33 0 obj +<< + /Title (FCLK_CLK0 output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 604 562 609] + /Parent 29 0 R + /Prev 32 0 R + /Next 34 0 R +>> +endobj +34 0 obj +<< + /Title (FCLK_CLK1 output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 448 562 452] + /Parent 29 0 R + /Prev 33 0 R + /Next 35 0 R +>> +endobj +35 0 obj +<< + /Title (FCLK_CLK2 output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 453 562 458] + /Parent 29 0 R + /Prev 34 0 R + /Next 36 0 R +>> +endobj +36 0 obj +<< + /Title (FCLK_CLK3 output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 587 562 592] + /Parent 29 0 R + /Prev 35 0 R + /Next 37 0 R +>> +endobj +37 0 obj +<< + /Title (FCLK_RESET0_N output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 459 571 463] + /Parent 29 0 R + /Prev 36 0 R + /Next 38 0 R +>> +endobj +38 0 obj +<< + /Title (GPIO_0 output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 743 556 749] + /Parent 29 0 R + /Prev 37 0 R + /Next 39 0 R +>> +endobj +39 0 obj +<< + /Title (PS_CLK inout) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 704 557 710] + /Parent 29 0 R + /Prev 38 0 R + /Next 40 0 R +>> +endobj +40 0 obj +<< + /Title (PS_PORB inout) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 699 560 704] + /Parent 29 0 R + /Prev 39 0 R + /Next 41 0 R +>> +endobj +41 0 obj +<< + /Title (PS_SRSTB inout) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 554 561 558] + /Parent 29 0 R + /Prev 40 0 R + /Next 42 0 R +>> +endobj +42 0 obj +<< + /Title (SPI0_MISO_I input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 57 615 84 620] + /Parent 29 0 R + /Prev 41 0 R + /Next 43 0 R +>> +endobj +43 0 obj +<< + /Title (SPI0_MISO_O output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 649 566 653] + /Parent 29 0 R + /Prev 42 0 R + /Next 44 0 R +>> +endobj +44 0 obj +<< + /Title (SPI0_MISO_T output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 643 565 648] + /Parent 29 0 R + /Prev 43 0 R + /Next 45 0 R +>> +endobj +45 0 obj +<< + /Title (SPI0_MOSI_I input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 57 652 84 656] + /Parent 29 0 R + /Prev 44 0 R + /Next 46 0 R +>> +endobj +46 0 obj +<< + /Title (SPI0_MOSI_O output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 666 566 670] + /Parent 29 0 R + /Prev 45 0 R + /Next 47 0 R +>> +endobj +47 0 obj +<< + /Title (SPI0_MOSI_T output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 660 565 665] + /Parent 29 0 R + /Prev 46 0 R + /Next 48 0 R +>> +endobj +48 0 obj +<< + /Title (SPI0_SCLK_I input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 56 660 84 665] + /Parent 29 0 R + /Prev 47 0 R + /Next 49 0 R +>> +endobj +49 0 obj +<< + /Title (SPI0_SCLK_O output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 526 566 530] + /Parent 29 0 R + /Prev 48 0 R + /Next 50 0 R +>> +endobj +50 0 obj +<< + /Title (SPI0_SCLK_T output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 520 565 525] + /Parent 29 0 R + /Prev 49 0 R + /Next 51 0 R +>> +endobj +51 0 obj +<< + /Title (SPI0_SS1_O output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 504 563 508] + /Parent 29 0 R + /Prev 50 0 R + /Next 52 0 R +>> +endobj +52 0 obj +<< + /Title (SPI0_SS2_O output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 498 563 503] + /Parent 29 0 R + /Prev 51 0 R + /Next 53 0 R +>> +endobj +53 0 obj +<< + /Title (SPI0_SS_I input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 61 599 84 603] + /Parent 29 0 R + /Prev 52 0 R + /Next 54 0 R +>> +endobj +54 0 obj +<< + /Title (SPI0_SS_O output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 515 561 519] + /Parent 29 0 R + /Prev 53 0 R + /Next 55 0 R +>> +endobj +55 0 obj +<< + /Title (SPI0_SS_T output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 509 561 514] + /Parent 29 0 R + /Prev 54 0 R + /Next 56 0 R +>> +endobj +56 0 obj +<< + /Title (SPI1_MISO_I input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 57 571 84 575] + /Parent 29 0 R + /Prev 55 0 R + /Next 57 0 R +>> +endobj +57 0 obj +<< + /Title (SPI1_MISO_O output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 565 566 570] + /Parent 29 0 R + /Prev 56 0 R + /Next 58 0 R +>> +endobj +58 0 obj +<< + /Title (SPI1_MISO_T output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 560 565 564] + /Parent 29 0 R + /Prev 57 0 R + /Next 59 0 R +>> +endobj +59 0 obj +<< + /Title (SPI1_MOSI_I input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 57 587 84 592] + /Parent 29 0 R + /Prev 58 0 R + /Next 60 0 R +>> +endobj +60 0 obj +<< + /Title (SPI1_MOSI_O output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 582 566 586] + /Parent 29 0 R + /Prev 59 0 R + /Next 61 0 R +>> +endobj +61 0 obj +<< + /Title (SPI1_MOSI_T output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 576 565 581] + /Parent 29 0 R + /Prev 60 0 R + /Next 62 0 R +>> +endobj +62 0 obj +<< + /Title (SPI1_SCLK_I input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 56 604 84 609] + /Parent 29 0 R + /Prev 61 0 R + /Next 63 0 R +>> +endobj +63 0 obj +<< + /Title (SPI1_SCLK_O output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 599 566 603] + /Parent 29 0 R + /Prev 62 0 R + /Next 64 0 R +>> +endobj +64 0 obj +<< + /Title (SPI1_SCLK_T output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 593 565 598] + /Parent 29 0 R + /Prev 63 0 R + /Next 65 0 R +>> +endobj +65 0 obj +<< + /Title (SPI1_SS1_O output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 543 563 547] + /Parent 29 0 R + /Prev 64 0 R + /Next 66 0 R +>> +endobj +66 0 obj +<< + /Title (SPI1_SS2_O output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 537 563 542] + /Parent 29 0 R + /Prev 65 0 R + /Next 67 0 R +>> +endobj +67 0 obj +<< + /Title (SPI1_SS_I input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 61 554 84 558] + /Parent 29 0 R + /Prev 66 0 R + /Next 68 0 R +>> +endobj +68 0 obj +<< + /Title (SPI1_SS_O output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 548 561 553] + /Parent 29 0 R + /Prev 67 0 R + /Next 69 0 R +>> +endobj +69 0 obj +<< + /Title (SPI1_SS_T output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 532 561 536] + /Parent 29 0 R + /Prev 68 0 R + /Next 70 0 R +>> +endobj +70 0 obj +<< + /Title (S_AXI_GP0_ACLK input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 48 593 84 598] + /Parent 29 0 R + /Prev 69 0 R + /Next 71 0 R +>> +endobj +71 0 obj +<< + /Title (S_AXI_GP0_ARESETN input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 41 520 84 525] + /Parent 29 0 R + /Prev 70 0 R + /Next 72 0 R +>> +endobj +72 0 obj +<< + /Title (S_AXI_HP0 input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 59 581 85 587] + /Parent 29 0 R + /Prev 71 0 R + /Next 73 0 R +>> +endobj +73 0 obj +<< + /Title (S_AXI_HP0_ACLK input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 48 576 85 581] + /Parent 29 0 R + /Prev 72 0 R + /Next 74 0 R +>> +endobj +74 0 obj +<< + /Title (S_AXI_HP0_ARESETN input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 41 610 84 614] + /Parent 29 0 R + /Prev 73 0 R + /Next 75 0 R +>> +endobj +75 0 obj +<< + /Title (USBIND_0 output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 492 560 497] + /Parent 29 0 R + /Prev 74 0 R + /Next 76 0 R +>> +endobj +76 0 obj +<< + /Title (bus_clk input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 66 565 84 570] + /Parent 29 0 R + /Prev 75 0 R + /Next 77 0 R +>> +endobj +77 0 obj +<< + /Title (bus_rstn input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 64 560 84 564] + /Parent 29 0 R + /Prev 76 0 R + /Next 78 0 R +>> +endobj +78 0 obj +<< + /Title (clk40 input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 69 641 84 645] + /Parent 29 0 R + /Prev 77 0 R + /Next 79 0 R +>> +endobj +79 0 obj +<< + /Title (clk40_rstn input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 62 548 84 553] + /Parent 29 0 R + /Prev 78 0 R + /Next 80 0 R +>> +endobj +80 0 obj +<< + /Title (i_cvita_dma input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 59 542 85 548] + /Parent 29 0 R + /Prev 79 0 R + /Next 81 0 R +>> +endobj +81 0 obj +<< + /Title (m_axi_eth_dma output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 486 567 492] + /Parent 29 0 R + /Prev 80 0 R + /Next 82 0 R +>> +endobj +82 0 obj +<< + /Title (m_axi_net output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 481 559 486] + /Parent 29 0 R + /Prev 81 0 R + /Next 83 0 R +>> +endobj +83 0 obj +<< + /Title (m_axi_xbar output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 475 561 481] + /Parent 29 0 R + /Prev 82 0 R + /Next 84 0 R +>> +endobj +84 0 obj +<< + /Title (o_cvita_dma output) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 470 563 475] + /Parent 29 0 R + /Prev 83 0 R + /Next 85 0 R +>> +endobj +85 0 obj +<< + /Title (s_axi_eth_descriptor input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 46 537 85 542] + /Parent 29 0 R + /Prev 84 0 R +>> +endobj +29 0 obj +<< + /Title (ports) + /C [0.0 0.4 0.0] + /F 1 + /Parent 21 0 R + /First 30 0 R + /Last 85 0 R + /Count 56 + /Prev 22 0 R + /Next 86 0 R +>> +endobj +87 0 obj +<< + /Title (IRQ_F2P input) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 55 620 85 626] + /Parent 86 0 R + /Next 88 0 R +>> +endobj +88 0 obj +<< + /Title (MIO inout) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 536 570 559 576] + /Parent 86 0 R + /Prev 87 0 R +>> +endobj +86 0 obj +<< + /Title (portBuses) + /C [0.0 0.4 0.0] + /F 1 + /Parent 21 0 R + /First 87 0 R + /Last 88 0 R + /Count 2 + /Prev 29 0 R + /Next 89 0 R +>> +endobj +90 0 obj +<< + /Title (IRQ_F2P_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 83 304 169 624] + /Parent 89 0 R + /Next 91 0 R +>> +endobj +91 0 obj +<< + /Title (S00_AXI_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 136 474 423 636] + /Parent 89 0 R + /Prev 90 0 R + /Next 92 0 R +>> +endobj +92 0 obj +<< + /Title (SPI0_MISO_I_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 84 464 433 668] + /Parent 89 0 R + /Prev 91 0 R + /Next 93 0 R +>> +endobj +93 0 obj +<< + /Title (SPI0_MOSI_I_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 84 461 442 674] + /Parent 89 0 R + /Prev 92 0 R + /Next 94 0 R +>> +endobj +94 0 obj +<< + /Title (SPI0_SCLK_I_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 84 458 445 691] + /Parent 89 0 R + /Prev 93 0 R + /Next 95 0 R +>> +endobj +95 0 obj +<< + /Title (SPI0_SS_I_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 84 455 439 660] + /Parent 89 0 R + /Prev 94 0 R + /Next 96 0 R +>> +endobj +96 0 obj +<< + /Title (SPI1_MISO_I_0_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 84 469 425 657] + /Parent 89 0 R + /Prev 95 0 R + /Next 97 0 R +>> +endobj +97 0 obj +<< + /Title (SPI1_MOSI_I_0_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 84 466 428 654] + /Parent 89 0 R + /Prev 96 0 R + /Next 98 0 R +>> +endobj +98 0 obj +<< + /Title (SPI1_SCLK_I_0_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 84 453 436 651] + /Parent 89 0 R + /Prev 97 0 R + /Next 99 0 R +>> +endobj +99 0 obj +<< + /Title (SPI1_SS_I_0_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 84 450 431 649] + /Parent 89 0 R + /Prev 98 0 R + /Next 100 0 R +>> +endobj +100 0 obj +<< + /Title (S_AXI_GP0_ACLK_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 84 528 160 596] + /Parent 89 0 R + /Prev 99 0 R + /Next 101 0 R +>> +endobj +101 0 obj +<< + /Title (S_AXI_GP0_ARESETN_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 84 523 159 523] + /Parent 89 0 R + /Prev 100 0 R + /Next 102 0 R +>> +endobj +102 0 obj +<< + /Title (S_AXI_HP0_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 83 583 160 613] + /Parent 89 0 R + /Prev 101 0 R + /Next 103 0 R +>> +endobj +103 0 obj +<< + /Title (S_AXI_HP0_ACLK_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 84 567 305 646] + /Parent 89 0 R + /Prev 102 0 R + /Next 104 0 R +>> +endobj +104 0 obj +<< + /Title (S_AXI_HP0_ARESETN_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 84 561 160 612] + /Parent 89 0 R + /Prev 103 0 R + /Next 105 0 R +>> +endobj +105 0 obj +<< + /Title (axi_interconnect_0_M00_AXI) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 225 480 538 501] + /Parent 89 0 R + /Prev 104 0 R + /Next 106 0 R +>> +endobj +106 0 obj +<< + /Title (axi_interconnect_0_M01_AXI) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 225 477 538 496] + /Parent 89 0 R + /Prev 105 0 R + /Next 107 0 R +>> +endobj +107 0 obj +<< + /Title (axi_interconnect_0_M02_AXI) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 225 471 538 490] + /Parent 89 0 R + /Prev 106 0 R + /Next 108 0 R +>> +endobj +108 0 obj +<< + /Title (axi_interconnect_0_M03_AXI) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 127 382 247 641] + /Parent 89 0 R + /Prev 107 0 R + /Next 109 0 R +>> +endobj +109 0 obj +<< + /Title (axi_interconnect_0_M05_AXI) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 130 393 253 638] + /Parent 89 0 R + /Prev 108 0 R + /Next 110 0 R +>> +endobj +110 0 obj +<< + /Title (axi_protocol_converter_hp0_M_AXI) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 225 586 306 633] + /Parent 89 0 R + /Prev 109 0 R + /Next 111 0 R +>> +endobj +111 0 obj +<< + /Title (bus_clk) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 84 377 159 568] + /Parent 89 0 R + /Prev 110 0 R + /Next 112 0 R +>> +endobj +112 0 obj +<< + /Title (bus_rstn) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 84 371 159 562] + /Parent 89 0 R + /Prev 111 0 R + /Next 113 0 R +>> +endobj +113 0 obj +<< + /Title (clk40) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 84 366 305 643] + /Parent 89 0 R + /Prev 112 0 R + /Next 114 0 R +>> +endobj +114 0 obj +<< + /Title (clk40_rstn) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 84 360 159 551] + /Parent 89 0 R + /Prev 113 0 R + /Next 115 0 R +>> +endobj +115 0 obj +<< + /Title (ddr_vrn) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 617 537 724] + /Parent 89 0 R + /Prev 114 0 R + /Next 116 0 R +>> +endobj +116 0 obj +<< + /Title (ddr_vrp) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 718 537 718] + /Parent 89 0 R + /Prev 115 0 R + /Next 117 0 R +>> +endobj +117 0 obj +<< + /Title (dma_M_AXI_RX_DMA) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 236 387 306 627] + /Parent 89 0 R + /Prev 116 0 R + /Next 118 0 R +>> +endobj +118 0 obj +<< + /Title (dma_M_AXI_TX_DMA) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 236 382 306 622] + /Parent 89 0 R + /Prev 117 0 R + /Next 119 0 R +>> +endobj +119 0 obj +<< + /Title (dma_tx_irq) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 237 78 336 372] + /Parent 89 0 R + /Prev 118 0 R + /Next 120 0 R +>> +endobj +120 0 obj +<< + /Title (i_cvita_dma_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 83 404 149 546] + /Parent 89 0 R + /Prev 119 0 R + /Next 121 0 R +>> +endobj +121 0 obj +<< + /Title (mio) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 572 537 730] + /Parent 89 0 R + /Prev 120 0 R + /Next 122 0 R +>> +endobj +122 0 obj +<< + /Title (o_cvita_dma_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 236 393 538 473] + /Parent 89 0 R + /Prev 121 0 R + /Next 123 0 R +>> +endobj +123 0 obj +<< + /Title (processing_system7_0_DDR) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 415 622 538 742] + /Parent 89 0 R + /Prev 122 0 R + /Next 124 0 R +>> +endobj +124 0 obj +<< + /Title (processing_system7_0_FCLK_CLK0) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 517 537 607] + /Parent 89 0 R + /Prev 123 0 R + /Next 125 0 R +>> +endobj +125 0 obj +<< + /Title (processing_system7_0_FCLK_CLK1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 450 537 512] + /Parent 89 0 R + /Prev 124 0 R + /Next 126 0 R +>> +endobj +126 0 obj +<< + /Title (processing_system7_0_FCLK_CLK2) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 455 537 506] + /Parent 89 0 R + /Prev 125 0 R + /Next 127 0 R +>> +endobj +127 0 obj +<< + /Title (processing_system7_0_FCLK_CLK3) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 500 537 590] + /Parent 89 0 R + /Prev 126 0 R + /Next 128 0 R +>> +endobj +128 0 obj +<< + /Title (processing_system7_0_FCLK_RESET0_N) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 461 537 495] + /Parent 89 0 R + /Prev 127 0 R + /Next 129 0 R +>> +endobj +129 0 obj +<< + /Title (processing_system7_0_GPIO_0) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 746 537 746] + /Parent 89 0 R + /Prev 128 0 R + /Next 130 0 R +>> +endobj +130 0 obj +<< + /Title (processing_system7_0_SPI0_MISO_O) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 651 537 651] + /Parent 89 0 R + /Prev 129 0 R + /Next 131 0 R +>> +endobj +131 0 obj +<< + /Title (processing_system7_0_SPI0_MISO_T) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 646 537 646] + /Parent 89 0 R + /Prev 130 0 R + /Next 132 0 R +>> +endobj +132 0 obj +<< + /Title (processing_system7_0_SPI0_MOSI_O) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 668 537 668] + /Parent 89 0 R + /Prev 131 0 R + /Next 133 0 R +>> +endobj +133 0 obj +<< + /Title (processing_system7_0_SPI0_MOSI_T) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 662 537 662] + /Parent 89 0 R + /Prev 132 0 R + /Next 134 0 R +>> +endobj +134 0 obj +<< + /Title (processing_system7_0_SPI0_SCLK_O) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 528 537 685] + /Parent 89 0 R + /Prev 133 0 R + /Next 135 0 R +>> +endobj +135 0 obj +<< + /Title (processing_system7_0_SPI0_SCLK_T) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 522 537 679] + /Parent 89 0 R + /Prev 134 0 R + /Next 136 0 R +>> +endobj +136 0 obj +<< + /Title (processing_system7_0_SPI0_SS1_O) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 506 537 629] + /Parent 89 0 R + /Prev 135 0 R + /Next 137 0 R +>> +endobj +137 0 obj +<< + /Title (processing_system7_0_SPI0_SS2_O) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 500 537 624] + /Parent 89 0 R + /Prev 136 0 R + /Next 138 0 R +>> +endobj +138 0 obj +<< + /Title (processing_system7_0_SPI0_SS_O) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 517 537 635] + /Parent 89 0 R + /Prev 137 0 R + /Next 139 0 R +>> +endobj +139 0 obj +<< + /Title (processing_system7_0_SPI0_SS_T) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 511 537 618] + /Parent 89 0 R + /Prev 138 0 R + /Next 140 0 R +>> +endobj +140 0 obj +<< + /Title (processing_system7_0_SPI1_MISO_O) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 567 537 567] + /Parent 89 0 R + /Prev 139 0 R + /Next 141 0 R +>> +endobj +141 0 obj +<< + /Title (processing_system7_0_SPI1_MISO_T) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 562 537 562] + /Parent 89 0 R + /Prev 140 0 R + /Next 142 0 R +>> +endobj +142 0 obj +<< + /Title (processing_system7_0_SPI1_MOSI_O) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 584 537 584] + /Parent 89 0 R + /Prev 141 0 R + /Next 143 0 R +>> +endobj +143 0 obj +<< + /Title (processing_system7_0_SPI1_MOSI_T) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 579 537 579] + /Parent 89 0 R + /Prev 142 0 R + /Next 144 0 R +>> +endobj +144 0 obj +<< + /Title (processing_system7_0_SPI1_SCLK_O) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 601 537 601] + /Parent 89 0 R + /Prev 143 0 R + /Next 145 0 R +>> +endobj +145 0 obj +<< + /Title (processing_system7_0_SPI1_SCLK_T) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 595 537 595] + /Parent 89 0 R + /Prev 144 0 R + /Next 146 0 R +>> +endobj +146 0 obj +<< + /Title (processing_system7_0_SPI1_SS1_O) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 545 537 545] + /Parent 89 0 R + /Prev 145 0 R + /Next 147 0 R +>> +endobj +147 0 obj +<< + /Title (processing_system7_0_SPI1_SS2_O) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 539 537 539] + /Parent 89 0 R + /Prev 146 0 R + /Next 148 0 R +>> +endobj +148 0 obj +<< + /Title (processing_system7_0_SPI1_SS_O) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 551 537 551] + /Parent 89 0 R + /Prev 147 0 R + /Next 149 0 R +>> +endobj +149 0 obj +<< + /Title (processing_system7_0_SPI1_SS_T) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 534 537 534] + /Parent 89 0 R + /Prev 148 0 R + /Next 150 0 R +>> +endobj +150 0 obj +<< + /Title (processing_system7_0_USBIND_0) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 415 494 538 529] + /Parent 89 0 R + /Prev 149 0 R + /Next 151 0 R +>> +endobj +151 0 obj +<< + /Title (ps_clk) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 707 537 707] + /Parent 89 0 R + /Prev 150 0 R + /Next 152 0 R +>> +endobj +152 0 obj +<< + /Title (ps_porb) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 701 537 701] + /Parent 89 0 R + /Prev 151 0 R + /Next 153 0 R +>> +endobj +153 0 obj +<< + /Title (ps_srstb) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 416 556 537 713] + /Parent 89 0 R + /Prev 152 0 R + /Next 154 0 R +>> +endobj +154 0 obj +<< + /Title (rx_dma_irq) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 237 84 336 378] + /Parent 89 0 R + /Prev 153 0 R + /Next 155 0 R +>> +endobj +155 0 obj +<< + /Title (s_axi_eth_descriptor_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 83 538 160 608] + /Parent 89 0 R + /Prev 154 0 R + /Next 156 0 R +>> +endobj +156 0 obj +<< + /Title (s_axi_regfile_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 133 387 250 633] + /Parent 89 0 R + /Prev 155 0 R + /Next 157 0 R +>> +endobj +157 0 obj +<< + /Title (s_axi_rx_dmac_1) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 139 399 244 630] + /Parent 89 0 R + /Prev 156 0 R + /Next 158 0 R +>> +endobj +158 0 obj +<< + /Title (xlconcat_0_dout) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 298 66 423 593] + /Parent 89 0 R + /Prev 157 0 R + /Next 159 0 R +>> +endobj +159 0 obj +<< + /Title (xlslice_2_Dout) + /C [0.0 0.0 0.4] + /Dest [10 0 R /FitR 217 89 336 306] + /Parent 89 0 R + /Prev 158 0 R +>> +endobj +89 0 obj +<< + /Title (nets) + /C [0.0 0.4 0.0] + /F 1 + /Parent 21 0 R + /First 90 0 R + /Last 159 0 R + /Count 70 + /Prev 86 0 R + /Next 160 0 R +>> +endobj +160 0 obj +<< + /Title (netBundles) + /C [0.0 0.4 0.0] + /F 1 + /Parent 21 0 R + /First 0 0 R + /Last 0 0 R + /Count 0 + /Prev 89 0 R +>> +endobj +21 0 obj +<< + /Title (Nlview page 1) + /C [0.4 0.0 0.0] + /Dest [10 0 R /Fit] + /Parent 7 0 R + /First 22 0 R + /Last 160 0 R + /Count 5 +>> +endobj +8 0 obj +<< +>> +endobj +9 0 obj +<< + /Im0 12 0 R + /Im1 13 0 R + /Im2 14 0 R + /Im3 15 0 R + /Im4 16 0 R + /Im5 17 0 R + /Im6 18 0 R + /Im7 19 0 R + /Im8 20 0 R +>> +endobj +161 0 obj +<< + /Type /XObject + /Subtype /Image + /ColorSpace /DeviceGray + /BitsPerComponent 8 + /Width 48 + /Height 60 + /Length 2880 +>> +stream +ÿÿÿÿÿÿÿÿÿÿÿ +endobj +12 0 obj +<< + /Type /XObject + /Subtype /Image + /ColorSpace /DeviceRGB + /BitsPerComponent 8 + /Width 48 + /Height 60 + /SMask 161 0 R + /Length 8640 +>> +stream +.Oƒ.Oƒ.Oƒ.Oƒ.Oƒ.Oƒ.Oƒ.Oƒ.Oƒ.Oƒ.Oƒ +endobj +162 0 obj +<< + /Type /XObject + /Subtype /Image + /ColorSpace /DeviceGray + /BitsPerComponent 8 + /Width 44 + /Height 44 + /Length 1936 +>> +stream + +endobj +13 0 obj +<< + /Type /XObject + /Subtype /Image + /ColorSpace /DeviceRGB + /BitsPerComponent 8 + /Width 44 + /Height 44 + /SMask 162 0 R + /Length 5808 +>> +stream + +endobj +163 0 obj +<< + /Type /XObject + /Subtype /Image + /ColorSpace /DeviceGray + /BitsPerComponent 8 + /Width 16 + /Height 16 + /Length 256 +>> +stream + + +endobj +14 0 obj +<< + /Type /XObject + /Subtype /Image + /ColorSpace /DeviceRGB + /BitsPerComponent 8 + /Width 16 + /Height 16 + /SMask 163 0 R + /Length 768 +>> +stream + +endobj +164 0 obj +<< + /Type /XObject + /Subtype /Image + /ColorSpace /DeviceGray + /BitsPerComponent 8 + /Width 10 + /Height 18 + /Length 180 +>> +stream + +endobj +15 0 obj +<< + /Type /XObject + /Subtype /Image + /ColorSpace /DeviceRGB + /BitsPerComponent 8 + /Width 10 + /Height 18 + /SMask 164 0 R + /Length 540 +>> +stream + +endobj +165 0 obj +<< + /Type /XObject + /Subtype /Image + /ColorSpace /DeviceGray + /BitsPerComponent 8 + /Width 10 + /Height 18 + /Length 180 +>> +stream +ÿÿ +endobj +16 0 obj +<< + /Type /XObject + /Subtype /Image + /ColorSpace /DeviceRGB + /BitsPerComponent 8 + /Width 10 + /Height 18 + /SMask 165 0 R + /Length 540 +>> +stream +?nž?nž +endobj +166 0 obj +<< + /Type /XObject + /Subtype /Image + /ColorSpace /DeviceGray + /BitsPerComponent 8 + /Width 10 + /Height 18 + /Length 180 +>> +stream +ÿÿ +endobj +17 0 obj +<< + /Type /XObject + /Subtype /Image + /ColorSpace /DeviceRGB + /BitsPerComponent 8 + /Width 10 + /Height 18 + /SMask 166 0 R + /Length 540 +>> +stream +Fl“?nž +endobj +167 0 obj +<< + /Type /XObject + /Subtype /Image + /ColorSpace /DeviceGray + /BitsPerComponent 8 + /Width 10 + /Height 18 + /Length 180 +>> +stream + +endobj +18 0 obj +<< + /Type /XObject + /Subtype /Image + /ColorSpace /DeviceRGB + /BitsPerComponent 8 + /Width 10 + /Height 18 + /SMask 167 0 R + /Length 540 +>> +stream + +endobj +168 0 obj +<< + /Type /XObject + /Subtype /Image + /ColorSpace /DeviceGray + /BitsPerComponent 8 + /Width 100 + /Height 31 + /Length 3100 +>> +stream + +endobj +19 0 obj +<< + /Type /XObject + /Subtype /Image + /ColorSpace /DeviceRGB + /BitsPerComponent 8 + /Width 100 + /Height 31 + /SMask 168 0 R + /Length 9300 +>> +stream + +endobj +169 0 obj +<< + /Type /XObject + /Subtype /Image + /ColorSpace /DeviceGray + /BitsPerComponent 8 + /Width 16 + /Height 16 + /Length 256 +>> +stream + + +endobj +20 0 obj +<< + /Type /XObject + /Subtype /Image + /ColorSpace /DeviceRGB + /BitsPerComponent 8 + /Width 16 + /Height 16 + /SMask 169 0 R + /Length 768 +>> +stream + +endobj +7 0 obj +<< + /Type /Outline + /First 21 0 R + /Last 21 0 R + /Count 1 +>> +endobj +xref +0 170 +0000000000 65535 f +0000000009 00000 n +0000000211 00000 n +0000054624 00000 n +0000000361 00000 n +0000000488 00000 n +0000054743 00000 n +0000118677 00000 n +0000078858 00000 n +0000078879 00000 n +0000000698 00000 n +0000000839 00000 n +0000082069 00000 n +0000092986 00000 n +0000099390 00000 n +0000100677 00000 n +0000101736 00000 n +0000102795 00000 n +0000103854 00000 n +0000107835 00000 n +0000117732 00000 n +0000078699 00000 n +0000056096 00000 n +0000055009 00000 n +0000055184 00000 n +0000055380 00000 n +0000055542 00000 n +0000055747 00000 n +0000055930 00000 n +0000065576 00000 n +0000056256 00000 n +0000056400 00000 n +0000056564 00000 n +0000056728 00000 n +0000056895 00000 n +0000057062 00000 n +0000057229 00000 n +0000057396 00000 n +0000057567 00000 n +0000057731 00000 n +0000057894 00000 n +0000058058 00000 n +0000058223 00000 n +0000058389 00000 n +0000058558 00000 n +0000058727 00000 n +0000058893 00000 n +0000059062 00000 n +0000059231 00000 n +0000059397 00000 n +0000059566 00000 n +0000059735 00000 n +0000059903 00000 n +0000060071 00000 n +0000060235 00000 n +0000060402 00000 n +0000060569 00000 n +0000060735 00000 n +0000060904 00000 n +0000061073 00000 n +0000061239 00000 n +0000061408 00000 n +0000061577 00000 n +0000061743 00000 n +0000061912 00000 n +0000062081 00000 n +0000062249 00000 n +0000062417 00000 n +0000062581 00000 n +0000062748 00000 n +0000062915 00000 n +0000063084 00000 n +0000063256 00000 n +0000063420 00000 n +0000063589 00000 n +0000063761 00000 n +0000063927 00000 n +0000064089 00000 n +0000064252 00000 n +0000064412 00000 n +0000064577 00000 n +0000064743 00000 n +0000064914 00000 n +0000065081 00000 n +0000065249 00000 n +0000065418 00000 n +0000066038 00000 n +0000065750 00000 n +0000065895 00000 n +0000078364 00000 n +0000066215 00000 n +0000066357 00000 n +0000066517 00000 n +0000066680 00000 n +0000066843 00000 n +0000067006 00000 n +0000067167 00000 n +0000067332 00000 n +0000067497 00000 n +0000067662 00000 n +0000067826 00000 n +0000067994 00000 n +0000068166 00000 n +0000068330 00000 n +0000068499 00000 n +0000068671 00000 n +0000068851 00000 n +0000069031 00000 n +0000069211 00000 n +0000069391 00000 n +0000069571 00000 n +0000069757 00000 n +0000069917 00000 n +0000070078 00000 n +0000070236 00000 n +0000070399 00000 n +0000070560 00000 n +0000070721 00000 n +0000070891 00000 n +0000071061 00000 n +0000071224 00000 n +0000071390 00000 n +0000071547 00000 n +0000071714 00000 n +0000071892 00000 n +0000072076 00000 n +0000072260 00000 n +0000072444 00000 n +0000072628 00000 n +0000072816 00000 n +0000072997 00000 n +0000073183 00000 n +0000073369 00000 n +0000073555 00000 n +0000073741 00000 n +0000073927 00000 n +0000074113 00000 n +0000074298 00000 n +0000074483 00000 n +0000074667 00000 n +0000074851 00000 n +0000075037 00000 n +0000075223 00000 n +0000075409 00000 n +0000075595 00000 n +0000075781 00000 n +0000075967 00000 n +0000076152 00000 n +0000076337 00000 n +0000076521 00000 n +0000076705 00000 n +0000076888 00000 n +0000077048 00000 n +0000077209 00000 n +0000077371 00000 n +0000077534 00000 n +0000077709 00000 n +0000077878 00000 n +0000078047 00000 n +0000078215 00000 n +0000078539 00000 n +0000079026 00000 n +0000090887 00000 n +0000098972 00000 n +0000100335 00000 n +0000101394 00000 n +0000102453 00000 n +0000103512 00000 n +0000104571 00000 n +0000117314 00000 n +trailer +<< + /Size 170 + /Info 1 0 R + /Root 2 0 R +>> +startxref +118759 +%%EOF diff --git a/fpga/usrp3/top/e320/ip/e320_ps_bd/e320_ps_bd.tcl b/fpga/usrp3/top/e320/ip/e320_ps_bd/e320_ps_bd.tcl new file mode 100644 index 000000000..04ba4accd --- /dev/null +++ b/fpga/usrp3/top/e320/ip/e320_ps_bd/e320_ps_bd.tcl @@ -0,0 +1,823 @@ +# CHANGE DESIGN NAME HERE +set design_name e320_ps_bd + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +create_bd_design $design_name +current_bd_design $design_name + +if { $nRet != 0 } { + puts $errMsg + return $nRet +} + +set scriptDir [file dirname [info script]] + +################################################################## +# DESIGN PROCs +################################################################## +source "$scriptDir/chdr_dma_top.tcl" + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set GPIO_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_0 ] + set m_axis_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma ] + set s_axis_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma ] + set_property -dict [ list \ + CONFIG.HAS_TLAST 1 \ + CONFIG.TDATA_NUM_BYTES 8 \ + CONFIG.TDEST_WIDTH 4 \ + ] $s_axis_dma + set m_axi_eth_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_eth_dma ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_eth_dma + set m_axi_net [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_net ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_WSTRB {0} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_net + set m_axi_xbar [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_xbar ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_WSTRB {0} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_xbar + set s_axi_eth_descriptor [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_eth_descriptor ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {5} \ + CONFIG.MAX_BURST_LENGTH {16} \ + CONFIG.NUM_READ_OUTSTANDING {8} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {8} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $s_axi_eth_descriptor + set S_AXI_HP0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_HP0 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {64} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {5} \ + CONFIG.MAX_BURST_LENGTH {16} \ + CONFIG.NUM_READ_OUTSTANDING {8} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {8} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $S_AXI_HP0 + set USBIND_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:usbctrl_rtl:1.0 USBIND_0 ] + + # Create ports + set DDR_VRN [ create_bd_port -dir IO DDR_VRN ] + set DDR_VRP [ create_bd_port -dir IO DDR_VRP ] + set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ] + set FCLK_CLK1 [ create_bd_port -dir O -type clk FCLK_CLK1 ] + set FCLK_CLK2 [ create_bd_port -dir O -type clk FCLK_CLK2 ] + set FCLK_CLK3 [ create_bd_port -dir O -type clk FCLK_CLK3 ] + set FCLK_RESET0_N [ create_bd_port -dir O -type rst FCLK_RESET0_N ] + set IRQ_F2P [ create_bd_port -dir I -from 15 -to 0 -type intr IRQ_F2P ] + set_property -dict [ list \ + CONFIG.PortWidth {16} \ + CONFIG.SENSITIVITY {EDGE_RISING} \ + ] $IRQ_F2P + set MIO [ create_bd_port -dir IO -from 53 -to 0 MIO ] + set PS_CLK [ create_bd_port -dir IO PS_CLK ] + set PS_PORB [ create_bd_port -dir IO PS_PORB ] + set PS_SRSTB [ create_bd_port -dir IO PS_SRSTB ] + set SPI0_MISO_I [ create_bd_port -dir I SPI0_MISO_I ] + set SPI0_MISO_O [ create_bd_port -dir O SPI0_MISO_O ] + set SPI0_MISO_T [ create_bd_port -dir O SPI0_MISO_T ] + set SPI0_MOSI_I [ create_bd_port -dir I SPI0_MOSI_I ] + set SPI0_MOSI_O [ create_bd_port -dir O SPI0_MOSI_O ] + set SPI0_MOSI_T [ create_bd_port -dir O SPI0_MOSI_T ] + set SPI0_SCLK_I [ create_bd_port -dir I SPI0_SCLK_I ] + set SPI0_SCLK_O [ create_bd_port -dir O SPI0_SCLK_O ] + set SPI0_SCLK_T [ create_bd_port -dir O SPI0_SCLK_T ] + set SPI0_SS1_O [ create_bd_port -dir O SPI0_SS1_O ] + set SPI0_SS2_O [ create_bd_port -dir O SPI0_SS2_O ] + set SPI0_SS_I [ create_bd_port -dir I SPI0_SS_I ] + set SPI0_SS_O [ create_bd_port -dir O SPI0_SS_O ] + set SPI0_SS_T [ create_bd_port -dir O SPI0_SS_T ] + set SPI1_MISO_I [ create_bd_port -dir I SPI1_MISO_I ] + set SPI1_MISO_O [ create_bd_port -dir O SPI1_MISO_O ] + set SPI1_MISO_T [ create_bd_port -dir O SPI1_MISO_T ] + set SPI1_MOSI_I [ create_bd_port -dir I SPI1_MOSI_I ] + set SPI1_MOSI_O [ create_bd_port -dir O SPI1_MOSI_O ] + set SPI1_MOSI_T [ create_bd_port -dir O SPI1_MOSI_T ] + set SPI1_SCLK_I [ create_bd_port -dir I SPI1_SCLK_I ] + set SPI1_SCLK_O [ create_bd_port -dir O SPI1_SCLK_O ] + set SPI1_SCLK_T [ create_bd_port -dir O SPI1_SCLK_T ] + set SPI1_SS1_O [ create_bd_port -dir O SPI1_SS1_O ] + set SPI1_SS2_O [ create_bd_port -dir O SPI1_SS2_O ] + set SPI1_SS_I [ create_bd_port -dir I SPI1_SS_I ] + set SPI1_SS_O [ create_bd_port -dir O SPI1_SS_O ] + set SPI1_SS_T [ create_bd_port -dir O SPI1_SS_T ] + set S_AXI_GP0_ACLK [ create_bd_port -dir I -type clk S_AXI_GP0_ACLK ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_RESET {S_AXI_GP0_ARESETN} \ + CONFIG.FREQ_HZ {40000000} \ + ] $S_AXI_GP0_ACLK + set S_AXI_GP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_GP0_ARESETN ] + set S_AXI_HP0_ACLK [ create_bd_port -dir I -type clk S_AXI_HP0_ACLK ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {40000000} \ + ] $S_AXI_HP0_ACLK + set S_AXI_HP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_HP0_ARESETN ] + set bus_clk [ create_bd_port -dir I -type clk bus_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {m_axis_dma:s_axis_dma} \ + CONFIG.ASSOCIATED_RESET {bus_rstn} \ + CONFIG.FREQ_HZ {200000000} \ + ] $bus_clk + set bus_rstn [ create_bd_port -dir I -type rst bus_rstn ] + set clk40 [ create_bd_port -dir I -type clk clk40 ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {m_axi_net:m_axi_xbar:m_axi_eth_dma} \ + CONFIG.ASSOCIATED_RESET {clk40_rstn} \ + CONFIG.FREQ_HZ {40000000} \ + ] $clk40 + set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] + # Create instance: axi_interconnect_hp0, and set properties + set axi_interconnect_hp0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_hp0 ] + set_property -dict [ list \ + CONFIG.ENABLE_ADVANCED_OPTIONS {0} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {2} \ + ] $axi_interconnect_hp0 + + + # Create instance: axi_interconnect_0, and set properties + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.ENABLE_ADVANCED_OPTIONS {0} \ + CONFIG.NUM_MI {6} \ + ] $axi_interconnect_0 + + # Create instance: dma + create_hier_cell_dma [current_bd_instance .] dma 6 + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] + set_property -dict [ list \ + CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {1000.000000} \ + CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \ + CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ + CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {40.000000} \ + CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {1000} \ + CONFIG.PCW_ARMPLL_CTRL_FBDIV {60} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_CLK0_FREQ {100000000} \ + CONFIG.PCW_CLK1_FREQ {40000000} \ + CONFIG.PCW_CLK2_FREQ {166666672} \ + CONFIG.PCW_CLK3_FREQ {200000000} \ + CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {2000.000} \ + CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \ + CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \ + CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \ + CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \ + CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ + CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ + CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ + CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {16} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ + CONFIG.PCW_ENET0_RESET_ENABLE {1} \ + CONFIG.PCW_ENET0_RESET_IO {MIO 3} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET1_RESET_ENABLE {0} \ + CONFIG.PCW_ENET_RESET_ENABLE {1} \ + CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ + CONFIG.PCW_EN_CLK1_PORT {1} \ + CONFIG.PCW_EN_CLK2_PORT {1} \ + CONFIG.PCW_EN_CLK3_PORT {1} \ + CONFIG.PCW_EN_EMIO_ENET0 {0} \ + CONFIG.PCW_EN_EMIO_GPIO {1} \ + CONFIG.PCW_EN_EMIO_I2C1 {0} \ + CONFIG.PCW_EN_EMIO_PJTAG {0} \ + CONFIG.PCW_EN_EMIO_SPI0 {1} \ + CONFIG.PCW_EN_EMIO_SPI1 {1} \ + CONFIG.PCW_EN_EMIO_UART0 {0} \ + CONFIG.PCW_EN_ENET0 {1} \ + CONFIG.PCW_EN_GPIO {1} \ + CONFIG.PCW_EN_I2C0 {1} \ + CONFIG.PCW_EN_I2C1 {1} \ + CONFIG.PCW_EN_PJTAG {1} \ + CONFIG.PCW_EN_RST1_PORT {0} \ + CONFIG.PCW_EN_RST2_PORT {0} \ + CONFIG.PCW_EN_RST3_PORT {0} \ + CONFIG.PCW_EN_SDIO0 {1} \ + CONFIG.PCW_EN_SPI0 {1} \ + CONFIG.PCW_EN_SPI1 {1} \ + CONFIG.PCW_EN_UART0 {1} \ + CONFIG.PCW_EN_UART1 {1} \ + CONFIG.PCW_EN_USB0 {1} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {10} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {5} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {4} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {3} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {2} \ + CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \ + CONFIG.PCW_FCLK_CLK2_BUF {TRUE} \ + CONFIG.PCW_FCLK_CLK3_BUF {TRUE} \ + CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {40} \ + CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {166.6667} \ + CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {200} \ + CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK2_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK3_ENABLE {1} \ + CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \ + CONFIG.PCW_GPIO_EMIO_GPIO_IO {64} \ + CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ + CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ + CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ + CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \ + CONFIG.PCW_I2C0_I2C0_IO {MIO 14 .. 15} \ + CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_I2C0_RESET_ENABLE {0} \ + CONFIG.PCW_I2C0_RESET_IO {<Select>} \ + CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \ + CONFIG.PCW_I2C1_I2C1_IO {MIO 48 .. 49} \ + CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_I2C1_RESET_ENABLE {0} \ + CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_I2C_RESET_ENABLE {0} \ + CONFIG.PCW_I2C_RESET_SELECT {<Select>} \ + CONFIG.PCW_IOPLL_CTRL_FBDIV {60} \ + CONFIG.PCW_IO_IO_PLL_FREQMHZ {2000.000} \ + CONFIG.PCW_IRQ_F2P_INTR {1} \ + CONFIG.PCW_MIO_0_DIRECTION {inout} \ + CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_0_PULLUP {enabled} \ + CONFIG.PCW_MIO_0_SLEW {slow} \ + CONFIG.PCW_MIO_10_DIRECTION {in} \ + CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_10_PULLUP {enabled} \ + CONFIG.PCW_MIO_10_SLEW {slow} \ + CONFIG.PCW_MIO_11_DIRECTION {out} \ + CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_11_PULLUP {enabled} \ + CONFIG.PCW_MIO_11_SLEW {slow} \ + CONFIG.PCW_MIO_12_DIRECTION {in} \ + CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_12_PULLUP {enabled} \ + CONFIG.PCW_MIO_12_SLEW {slow} \ + CONFIG.PCW_MIO_13_DIRECTION {in} \ + CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_13_PULLUP {enabled} \ + CONFIG.PCW_MIO_13_SLEW {slow} \ + CONFIG.PCW_MIO_14_DIRECTION {inout} \ + CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_14_PULLUP {enabled} \ + CONFIG.PCW_MIO_14_SLEW {slow} \ + CONFIG.PCW_MIO_15_DIRECTION {inout} \ + CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_15_PULLUP {enabled} \ + CONFIG.PCW_MIO_15_SLEW {slow} \ + CONFIG.PCW_MIO_16_DIRECTION {out} \ + CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_16_PULLUP {disabled} \ + CONFIG.PCW_MIO_16_SLEW {fast} \ + CONFIG.PCW_MIO_17_DIRECTION {out} \ + CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_17_PULLUP {disabled} \ + CONFIG.PCW_MIO_17_SLEW {fast} \ + CONFIG.PCW_MIO_18_DIRECTION {out} \ + CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_18_PULLUP {disabled} \ + CONFIG.PCW_MIO_18_SLEW {fast} \ + CONFIG.PCW_MIO_19_DIRECTION {out} \ + CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_19_PULLUP {disabled} \ + CONFIG.PCW_MIO_19_SLEW {fast} \ + CONFIG.PCW_MIO_1_DIRECTION {inout} \ + CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_1_PULLUP {enabled} \ + CONFIG.PCW_MIO_1_SLEW {slow} \ + CONFIG.PCW_MIO_20_DIRECTION {out} \ + CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_20_PULLUP {disabled} \ + CONFIG.PCW_MIO_20_SLEW {fast} \ + CONFIG.PCW_MIO_21_DIRECTION {out} \ + CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_21_PULLUP {disabled} \ + CONFIG.PCW_MIO_21_SLEW {fast} \ + CONFIG.PCW_MIO_22_DIRECTION {in} \ + CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_22_PULLUP {disabled} \ + CONFIG.PCW_MIO_22_SLEW {fast} \ + CONFIG.PCW_MIO_23_DIRECTION {in} \ + CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_23_PULLUP {disabled} \ + CONFIG.PCW_MIO_23_SLEW {fast} \ + CONFIG.PCW_MIO_24_DIRECTION {in} \ + CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_24_PULLUP {disabled} \ + CONFIG.PCW_MIO_24_SLEW {fast} \ + CONFIG.PCW_MIO_25_DIRECTION {in} \ + CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_25_PULLUP {disabled} \ + CONFIG.PCW_MIO_25_SLEW {fast} \ + CONFIG.PCW_MIO_26_DIRECTION {in} \ + CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_26_PULLUP {disabled} \ + CONFIG.PCW_MIO_26_SLEW {fast} \ + CONFIG.PCW_MIO_27_DIRECTION {in} \ + CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_27_PULLUP {disabled} \ + CONFIG.PCW_MIO_27_SLEW {fast} \ + CONFIG.PCW_MIO_28_DIRECTION {inout} \ + CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_28_PULLUP {enabled} \ + CONFIG.PCW_MIO_28_SLEW {slow} \ + CONFIG.PCW_MIO_29_DIRECTION {in} \ + CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_29_PULLUP {enabled} \ + CONFIG.PCW_MIO_29_SLEW {slow} \ + CONFIG.PCW_MIO_2_DIRECTION {inout} \ + CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_2_PULLUP {disabled} \ + CONFIG.PCW_MIO_2_SLEW {slow} \ + CONFIG.PCW_MIO_30_DIRECTION {out} \ + CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_30_PULLUP {enabled} \ + CONFIG.PCW_MIO_30_SLEW {slow} \ + CONFIG.PCW_MIO_31_DIRECTION {in} \ + CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_31_PULLUP {enabled} \ + CONFIG.PCW_MIO_31_SLEW {slow} \ + CONFIG.PCW_MIO_32_DIRECTION {inout} \ + CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_32_PULLUP {enabled} \ + CONFIG.PCW_MIO_32_SLEW {slow} \ + CONFIG.PCW_MIO_33_DIRECTION {inout} \ + CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_33_PULLUP {enabled} \ + CONFIG.PCW_MIO_33_SLEW {slow} \ + CONFIG.PCW_MIO_34_DIRECTION {inout} \ + CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_34_PULLUP {enabled} \ + CONFIG.PCW_MIO_34_SLEW {slow} \ + CONFIG.PCW_MIO_35_DIRECTION {inout} \ + CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_35_PULLUP {enabled} \ + CONFIG.PCW_MIO_35_SLEW {slow} \ + CONFIG.PCW_MIO_36_DIRECTION {in} \ + CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_36_PULLUP {enabled} \ + CONFIG.PCW_MIO_36_SLEW {slow} \ + CONFIG.PCW_MIO_37_DIRECTION {inout} \ + CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_37_PULLUP {enabled} \ + CONFIG.PCW_MIO_37_SLEW {slow} \ + CONFIG.PCW_MIO_38_DIRECTION {inout} \ + CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_38_PULLUP {enabled} \ + CONFIG.PCW_MIO_38_SLEW {slow} \ + CONFIG.PCW_MIO_39_DIRECTION {inout} \ + CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_39_PULLUP {enabled} \ + CONFIG.PCW_MIO_39_SLEW {slow} \ + CONFIG.PCW_MIO_3_DIRECTION {out} \ + CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_3_PULLUP {disabled} \ + CONFIG.PCW_MIO_3_SLEW {slow} \ + CONFIG.PCW_MIO_40_DIRECTION {inout} \ + CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_40_PULLUP {enabled} \ + CONFIG.PCW_MIO_40_SLEW {slow} \ + CONFIG.PCW_MIO_41_DIRECTION {inout} \ + CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_41_PULLUP {enabled} \ + CONFIG.PCW_MIO_41_SLEW {slow} \ + CONFIG.PCW_MIO_42_DIRECTION {inout} \ + CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_42_PULLUP {enabled} \ + CONFIG.PCW_MIO_42_SLEW {slow} \ + CONFIG.PCW_MIO_43_DIRECTION {inout} \ + CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_43_PULLUP {enabled} \ + CONFIG.PCW_MIO_43_SLEW {slow} \ + CONFIG.PCW_MIO_44_DIRECTION {inout} \ + CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_44_PULLUP {enabled} \ + CONFIG.PCW_MIO_44_SLEW {slow} \ + CONFIG.PCW_MIO_45_DIRECTION {inout} \ + CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_45_PULLUP {enabled} \ + CONFIG.PCW_MIO_45_SLEW {slow} \ + CONFIG.PCW_MIO_46_DIRECTION {in} \ + CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_46_PULLUP {enabled} \ + CONFIG.PCW_MIO_46_SLEW {slow} \ + CONFIG.PCW_MIO_47_DIRECTION {out} \ + CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_47_PULLUP {enabled} \ + CONFIG.PCW_MIO_47_SLEW {slow} \ + CONFIG.PCW_MIO_48_DIRECTION {inout} \ + CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_48_PULLUP {enabled} \ + CONFIG.PCW_MIO_48_SLEW {slow} \ + CONFIG.PCW_MIO_49_DIRECTION {inout} \ + CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_49_PULLUP {enabled} \ + CONFIG.PCW_MIO_49_SLEW {slow} \ + CONFIG.PCW_MIO_4_DIRECTION {out} \ + CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_4_PULLUP {disabled} \ + CONFIG.PCW_MIO_4_SLEW {slow} \ + CONFIG.PCW_MIO_50_DIRECTION {inout} \ + CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_50_PULLUP {enabled} \ + CONFIG.PCW_MIO_50_SLEW {slow} \ + CONFIG.PCW_MIO_51_DIRECTION {inout} \ + CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_51_PULLUP {enabled} \ + CONFIG.PCW_MIO_51_SLEW {slow} \ + CONFIG.PCW_MIO_52_DIRECTION {out} \ + CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_52_PULLUP {enabled} \ + CONFIG.PCW_MIO_52_SLEW {slow} \ + CONFIG.PCW_MIO_53_DIRECTION {inout} \ + CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_53_PULLUP {enabled} \ + CONFIG.PCW_MIO_53_SLEW {slow} \ + CONFIG.PCW_MIO_5_DIRECTION {inout} \ + CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_5_PULLUP {disabled} \ + CONFIG.PCW_MIO_5_SLEW {slow} \ + CONFIG.PCW_MIO_6_DIRECTION {inout} \ + CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_6_PULLUP {disabled} \ + CONFIG.PCW_MIO_6_SLEW {slow} \ + CONFIG.PCW_MIO_7_DIRECTION {out} \ + CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_7_PULLUP {disabled} \ + CONFIG.PCW_MIO_7_SLEW {slow} \ + CONFIG.PCW_MIO_8_DIRECTION {out} \ + CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_8_PULLUP {disabled} \ + CONFIG.PCW_MIO_8_SLEW {slow} \ + CONFIG.PCW_MIO_9_DIRECTION {in} \ + CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_9_PULLUP {enabled} \ + CONFIG.PCW_MIO_9_SLEW {slow} \ + CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#ENET Reset#USB Reset#GPIO#GPIO#GPIO#UART 1#UART 1#PJTAG#PJTAG#PJTAG#PJTAG#I2C 0#I2C 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#UART 0#UART 0#I2C 1#I2C 1#GPIO#GPIO#Enet 0#Enet 0} \ + CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#reset#reset#gpio[5]#gpio[6]#gpio[7]#tx#rx#tdi#tdo#tck#tms#scl#sda#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#rx#tx#scl#sda#gpio[50]#gpio[51]#mdc#mdio} \ + CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {10} \ + CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_PJTAG_PJTAG_IO {MIO 10 .. 13} \ + CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \ + CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ + CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \ + CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ + CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \ + CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ + CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \ + CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ + CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_SPI0_GRP_SS0_ENABLE {1} \ + CONFIG.PCW_SPI0_GRP_SS0_IO {EMIO} \ + CONFIG.PCW_SPI0_GRP_SS1_ENABLE {1} \ + CONFIG.PCW_SPI0_GRP_SS1_IO {EMIO} \ + CONFIG.PCW_SPI0_GRP_SS2_ENABLE {1} \ + CONFIG.PCW_SPI0_GRP_SS2_IO {EMIO} \ + CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SPI0_SPI0_IO {EMIO} \ + CONFIG.PCW_SPI1_GRP_SS0_ENABLE {1} \ + CONFIG.PCW_SPI1_GRP_SS0_IO {EMIO} \ + CONFIG.PCW_SPI1_GRP_SS1_ENABLE {1} \ + CONFIG.PCW_SPI1_GRP_SS1_IO {EMIO} \ + CONFIG.PCW_SPI1_GRP_SS2_ENABLE {1} \ + CONFIG.PCW_SPI1_GRP_SS2_IO {EMIO} \ + CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SPI1_SPI1_IO {EMIO} \ + CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {12} \ + CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \ + CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \ + CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \ + CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_UART0_UART0_IO {MIO 46 .. 47} \ + CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ + CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_UART1_UART1_IO {MIO 8 .. 9} \ + CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {20} \ + CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ + CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \ + CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.096} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.102} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.100} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.090} \ + CONFIG.PCW_UIPARAM_DDR_CL {7} \ + CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \ + CONFIG.PCW_UIPARAM_DDR_CWL {6} \ + CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.054} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.040} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.041} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.010} \ + CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ + CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \ + CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ + CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ + CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ + CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \ + CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \ + CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \ + CONFIG.PCW_UIPARAM_DDR_T_RP {7} \ + CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_USB0_RESET_ENABLE {1} \ + CONFIG.PCW_USB0_RESET_IO {MIO 4} \ + CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \ + CONFIG.PCW_USB1_RESET_ENABLE {0} \ + CONFIG.PCW_USB_RESET_ENABLE {1} \ + CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ + CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ + CONFIG.PCW_USE_HIGH_OCM {1} \ + CONFIG.PCW_USE_PS_SLCR_REGISTERS {1} \ + CONFIG.PCW_USE_S_AXI_GP0 {0} \ + CONFIG.PCW_USE_S_AXI_GP1 {0} \ + CONFIG.PCW_USE_S_AXI_HP0 {1} \ + CONFIG.PCW_USE_S_AXI_HP1 {1} \ + CONFIG.PCW_USE_S_AXI_HP2 {1} \ + CONFIG.PCW_USE_S_AXI_HP3 {0} \ + ] $processing_system7_0 + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ + CONFIG.IN0_WIDTH {8} \ + CONFIG.NUM_PORTS {9} \ + ] $xlconcat_0 + + # Create instance: xlslice_2, and set properties + set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {16} \ + CONFIG.DOUT_WIDTH {8} \ + ] $xlslice_2 + + # Create interface connections + connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0] + connect_bd_intf_net -intf_net s_axi_eth_descriptor_1 [get_bd_intf_ports s_axi_eth_descriptor] [get_bd_intf_pins axi_interconnect_hp0/S01_AXI] + connect_bd_intf_net -intf_net S_AXI_HP0_1 [get_bd_intf_ports S_AXI_HP0] [get_bd_intf_pins axi_interconnect_hp0/S00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports m_axi_eth_dma] [get_bd_intf_pins axi_interconnect_0/M00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports m_axi_net] [get_bd_intf_pins axi_interconnect_0/M01_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_ports m_axi_xbar] [get_bd_intf_pins axi_interconnect_0/M02_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins axi_interconnect_0/M05_AXI] [get_bd_intf_pins dma/s_axi_tx_dmac] + connect_bd_intf_net -intf_net axi_protocol_converter_hp0_M_AXI [get_bd_intf_pins axi_interconnect_hp0/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0] + connect_bd_intf_net -intf_net dma_M_AXI_RX_DMA [get_bd_intf_pins dma/M_AXI_RX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP1] + connect_bd_intf_net -intf_net dma_M_AXI_TX_DMA [get_bd_intf_pins dma/M_AXI_TX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP2] + connect_bd_intf_net -intf_net s_axis_dma_1 [get_bd_intf_ports s_axis_dma] [get_bd_intf_pins dma/s_axis_dma] + connect_bd_intf_net -intf_net m_axis_dma_1 [get_bd_intf_ports m_axis_dma] [get_bd_intf_pins dma/m_axis_dma] + connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] + connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_0] [get_bd_intf_pins processing_system7_0/GPIO_0] + connect_bd_intf_net -intf_net processing_system7_0_USBIND_0 [get_bd_intf_ports USBIND_0] [get_bd_intf_pins processing_system7_0/USBIND_0] + connect_bd_intf_net -intf_net s_axi_regfile_1 [get_bd_intf_pins axi_interconnect_0/M03_AXI] [get_bd_intf_pins dma/s_axi_regfile] + connect_bd_intf_net -intf_net s_axi_rx_dmac_1 [get_bd_intf_pins axi_interconnect_0/M04_AXI] [get_bd_intf_pins dma/s_axi_rx_dmac] + + # Create port connections + connect_bd_net -net IRQ_F2P_1 [get_bd_ports IRQ_F2P] [get_bd_pins xlslice_2/Din] + connect_bd_net -net SPI0_MISO_I_1 [get_bd_ports SPI0_MISO_I] [get_bd_pins processing_system7_0/SPI0_MISO_I] + connect_bd_net -net SPI0_MOSI_I_1 [get_bd_ports SPI0_MOSI_I] [get_bd_pins processing_system7_0/SPI0_MOSI_I] + connect_bd_net -net SPI0_SCLK_I_1 [get_bd_ports SPI0_SCLK_I] [get_bd_pins processing_system7_0/SPI0_SCLK_I] + connect_bd_net -net SPI0_SS_I_1 [get_bd_ports SPI0_SS_I] [get_bd_pins processing_system7_0/SPI0_SS_I] + connect_bd_net -net SPI1_MISO_I_0_1 [get_bd_ports SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MISO_I] + connect_bd_net -net SPI1_MOSI_I_0_1 [get_bd_ports SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] + connect_bd_net -net SPI1_SCLK_I_0_1 [get_bd_ports SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] + connect_bd_net -net SPI1_SS_I_0_1 [get_bd_ports SPI1_SS_I] [get_bd_pins processing_system7_0/SPI1_SS_I] + connect_bd_net -net S_AXI_GP0_ACLK_1 [get_bd_ports S_AXI_GP0_ACLK] [get_bd_pins axi_interconnect_0/ACLK] + connect_bd_net -net S_AXI_GP0_ARESETN_1 [get_bd_ports S_AXI_GP0_ARESETN] [get_bd_pins axi_interconnect_0/ARESETN] + connect_bd_net -net S_AXI_HP0_ACLK_1 [get_bd_ports S_AXI_HP0_ACLK] [get_bd_pins axi_interconnect_hp0/ACLK] [get_bd_pins axi_interconnect_hp0/M00_ACLK] [get_bd_pins axi_interconnect_hp0/S00_ACLK] [get_bd_pins axi_interconnect_hp0/S01_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] + connect_bd_net -net S_AXI_HP0_ARESETN_1 [get_bd_ports S_AXI_HP0_ARESETN] [get_bd_pins axi_interconnect_hp0/ARESETN] [get_bd_pins axi_interconnect_hp0/M00_ARESETN] [get_bd_pins axi_interconnect_hp0/S00_ARESETN] [get_bd_pins axi_interconnect_hp0/S01_ARESETN] + connect_bd_net -net bus_clk [get_bd_ports bus_clk] [get_bd_pins dma/bus_clk] + connect_bd_net -net bus_rstn [get_bd_ports bus_rstn] [get_bd_pins dma/bus_rstn] + connect_bd_net -net clk40 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins dma/clk40] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] + connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins dma/clk40_rstn] + connect_bd_net -net ddr_vrn [get_bd_ports DDR_VRN] [get_bd_pins processing_system7_0/DDR_VRN] + connect_bd_net -net ddr_vrp [get_bd_ports DDR_VRP] [get_bd_pins processing_system7_0/DDR_VRP] + connect_bd_net -net dma_tx_irq [get_bd_pins dma/tx_irq] [get_bd_pins xlconcat_0/In2] + connect_bd_net -net mio [get_bd_ports MIO] [get_bd_pins processing_system7_0/MIO] + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FCLK_CLK0] [get_bd_pins processing_system7_0/FCLK_CLK0] + connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_ports FCLK_CLK1] [get_bd_pins processing_system7_0/FCLK_CLK1] + connect_bd_net -net processing_system7_0_FCLK_CLK2 [get_bd_ports FCLK_CLK2] [get_bd_pins processing_system7_0/FCLK_CLK2] + connect_bd_net -net processing_system7_0_FCLK_CLK3 [get_bd_ports FCLK_CLK3] [get_bd_pins processing_system7_0/FCLK_CLK3] + connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_ports FCLK_RESET0_N] [get_bd_pins processing_system7_0/FCLK_RESET0_N] + connect_bd_net -net processing_system7_0_SPI0_MISO_O [get_bd_ports SPI0_MISO_O] [get_bd_pins processing_system7_0/SPI0_MISO_O] + connect_bd_net -net processing_system7_0_SPI0_MISO_T [get_bd_ports SPI0_MISO_T] [get_bd_pins processing_system7_0/SPI0_MISO_T] + connect_bd_net -net processing_system7_0_SPI0_MOSI_O [get_bd_ports SPI0_MOSI_O] [get_bd_pins processing_system7_0/SPI0_MOSI_O] + connect_bd_net -net processing_system7_0_SPI0_MOSI_T [get_bd_ports SPI0_MOSI_T] [get_bd_pins processing_system7_0/SPI0_MOSI_T] + connect_bd_net -net processing_system7_0_SPI0_SCLK_O [get_bd_ports SPI0_SCLK_O] [get_bd_pins processing_system7_0/SPI0_SCLK_O] + connect_bd_net -net processing_system7_0_SPI0_SCLK_T [get_bd_ports SPI0_SCLK_T] [get_bd_pins processing_system7_0/SPI0_SCLK_T] + connect_bd_net -net processing_system7_0_SPI0_SS1_O [get_bd_ports SPI0_SS1_O] [get_bd_pins processing_system7_0/SPI0_SS1_O] + connect_bd_net -net processing_system7_0_SPI0_SS2_O [get_bd_ports SPI0_SS2_O] [get_bd_pins processing_system7_0/SPI0_SS2_O] + connect_bd_net -net processing_system7_0_SPI0_SS_O [get_bd_ports SPI0_SS_O] [get_bd_pins processing_system7_0/SPI0_SS_O] + connect_bd_net -net processing_system7_0_SPI0_SS_T [get_bd_ports SPI0_SS_T] [get_bd_pins processing_system7_0/SPI0_SS_T] + connect_bd_net -net processing_system7_0_SPI1_MISO_O [get_bd_ports SPI1_MISO_O] [get_bd_pins processing_system7_0/SPI1_MISO_O] + connect_bd_net -net processing_system7_0_SPI1_MISO_T [get_bd_ports SPI1_MISO_T] [get_bd_pins processing_system7_0/SPI1_MISO_T] + connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports SPI1_MOSI_O] [get_bd_pins processing_system7_0/SPI1_MOSI_O] + connect_bd_net -net processing_system7_0_SPI1_MOSI_T [get_bd_ports SPI1_MOSI_T] [get_bd_pins processing_system7_0/SPI1_MOSI_T] + connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports SPI1_SCLK_O] [get_bd_pins processing_system7_0/SPI1_SCLK_O] + connect_bd_net -net processing_system7_0_SPI1_SCLK_T [get_bd_ports SPI1_SCLK_T] [get_bd_pins processing_system7_0/SPI1_SCLK_T] + connect_bd_net -net processing_system7_0_SPI1_SS1_O [get_bd_ports SPI1_SS1_O] [get_bd_pins processing_system7_0/SPI1_SS1_O] + connect_bd_net -net processing_system7_0_SPI1_SS2_O [get_bd_ports SPI1_SS2_O] [get_bd_pins processing_system7_0/SPI1_SS2_O] + connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports SPI1_SS_O] [get_bd_pins processing_system7_0/SPI1_SS_O] + connect_bd_net -net processing_system7_0_SPI1_SS_T [get_bd_ports SPI1_SS_T] [get_bd_pins processing_system7_0/SPI1_SS_T] + connect_bd_net -net ps_clk [get_bd_ports PS_CLK] [get_bd_pins processing_system7_0/PS_CLK] + connect_bd_net -net ps_porb [get_bd_ports PS_PORB] [get_bd_pins processing_system7_0/PS_PORB] + connect_bd_net -net ps_srstb [get_bd_ports PS_SRSTB] [get_bd_pins processing_system7_0/PS_SRSTB] + connect_bd_net -net rx_dma_irq [get_bd_pins dma/rx_irq] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins xlconcat_0/dout] + connect_bd_net -net xlslice_2_Dout [get_bd_pins xlconcat_0/In0] [get_bd_pins xlslice_2/Dout] + + # Create address segments + create_bd_addr_seg -range 0x00004000 -offset 0x40000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_eth_dma/Reg] SEG_m_axi_eth_dma_Reg + create_bd_addr_seg -range 0x00004000 -offset 0x40004000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_net/Reg] SEG_m_axi_net_Reg + create_bd_addr_seg -range 0x00004000 -offset 0x40010000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_xbar/Reg] SEG_m_axi_xbar_Reg + create_bd_addr_seg -range 0x00001000 -offset 0x42080000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/axi_regfile_0/S_AXI/regs] SEG_axi_regfile_0_regs + create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma0/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite + create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma1/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite4 + create_bd_addr_seg -range 0x00010000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma2/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite6 + create_bd_addr_seg -range 0x00010000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma3/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite8 + create_bd_addr_seg -range 0x00010000 -offset 0x43C40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma4/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite10 + create_bd_addr_seg -range 0x00010000 -offset 0x43C50000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma5/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite12 + create_bd_addr_seg -range 0x00010000 -offset 0x43CA0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_0/s_axi/axi_lite] SEG_axi_tx_dmac_0_axi_lite + create_bd_addr_seg -range 0x00010000 -offset 0x43CB0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_1/s_axi/axi_lite] SEG_axi_tx_dmac_1_axi_lite + create_bd_addr_seg -range 0x00010000 -offset 0x43CC0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_2/s_axi/axi_lite] SEG_axi_tx_dmac_2_axi_lite + create_bd_addr_seg -range 0x00010000 -offset 0x43CD0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_3/s_axi/axi_lite] SEG_axi_tx_dmac_3_axi_lite + create_bd_addr_seg -range 0x00010000 -offset 0x43CE0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_4/s_axi/axi_lite] SEG_axi_tx_dmac_4_axi_lite + create_bd_addr_seg -range 0x00010000 -offset 0x43CF0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_5/s_axi/axi_lite] SEG_axi_tx_dmac_5_axi_lite + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_0/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_1/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_2/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_3/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_4/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_5/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma0/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma1/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma2/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma3/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma4/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma5/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_eth_descriptor] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_GP0_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces S_AXI_HP0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + + + # Restore current instance + current_bd_instance $oldCurInst + + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/fpga/usrp3/top/e320/ip/e320_ps_bd/ps7_init.c b/fpga/usrp3/top/e320/ip/e320_ps_bd/ps7_init.c new file mode 100644 index 000000000..1ad91d83a --- /dev/null +++ b/fpga/usrp3/top/e320/ip/e320_ps_bd/ps7_init.c @@ -0,0 +1,13335 @@ +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xc + // .. ==> 0XF8000158[13:8] = 0x0000000CU + // .. ==> MASK : 0x00003F00U VAL : 0x00000C00U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x5 + // .. .. ==> 0XF8000180[25:20] = 0x00000005U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000190[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x3 + // .. .. ==> 0XF8000190[25:20] = 0x00000003U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF80001A0[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF800612C[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0x7a + // .. .. ==> 0XF800612C[19:10] = 0x0000007AU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006130[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006130[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006134[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006134[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1 + // .. .. ==> 0XF8006138[9:0] = 0x00000001U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000001U + // .. .. reg_phy_gatelvl_init_ratio = 0x78 + // .. .. ==> 0XF8006138[19:10] = 0x00000078U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006154[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF8006158[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF800615C[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x81 + // .. .. ==> 0XF8006160[9:0] = 0x00000081U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000081U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcf + // .. .. ==> 0XF8006168[10:0] = 0x000000CFU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CFU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF800616C[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF8006170[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcd + // .. .. ==> 0XF8006174[10:0] = 0x000000CDU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CDU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF800617C[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006180[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006184[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc1 + // .. .. ==> 0XF8006188[9:0] = 0x000000C1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000728[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF800072C[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000730[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000730[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000734[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000734[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007B8[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007BC[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. .. START: AFI2 SECURE REGISTER + // .. .. FINISH: AFI2 SECURE REGISTER + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xc + // .. ==> 0XF8000158[13:8] = 0x0000000CU + // .. ==> MASK : 0x00003F00U VAL : 0x00000C00U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x5 + // .. .. ==> 0XF8000180[25:20] = 0x00000005U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000190[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x3 + // .. .. ==> 0XF8000190[25:20] = 0x00000003U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF80001A0[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF800612C[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0x7a + // .. .. ==> 0XF800612C[19:10] = 0x0000007AU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006130[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006130[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006134[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006134[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1 + // .. .. ==> 0XF8006138[9:0] = 0x00000001U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000001U + // .. .. reg_phy_gatelvl_init_ratio = 0x78 + // .. .. ==> 0XF8006138[19:10] = 0x00000078U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006154[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF8006158[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF800615C[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x81 + // .. .. ==> 0XF8006160[9:0] = 0x00000081U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000081U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcf + // .. .. ==> 0XF8006168[10:0] = 0x000000CFU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CFU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF800616C[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF8006170[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcd + // .. .. ==> 0XF8006174[10:0] = 0x000000CDU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CDU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF800617C[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006180[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006184[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc1 + // .. .. ==> 0XF8006188[9:0] = 0x000000C1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000728[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF800072C[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000730[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000730[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000734[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000734[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007B8[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007BC[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xc + // .. ==> 0XF8000158[13:8] = 0x0000000CU + // .. ==> MASK : 0x00003F00U VAL : 0x00000C00U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x5 + // .. .. ==> 0XF8000180[25:20] = 0x00000005U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000190[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x3 + // .. .. ==> 0XF8000190[25:20] = 0x00000003U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF80001A0[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF800612C[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0x7a + // .. .. ==> 0XF800612C[19:10] = 0x0000007AU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006130[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006130[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006134[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006134[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1 + // .. .. ==> 0XF8006138[9:0] = 0x00000001U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000001U + // .. .. reg_phy_gatelvl_init_ratio = 0x78 + // .. .. ==> 0XF8006138[19:10] = 0x00000078U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006154[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF8006158[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF800615C[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x81 + // .. .. ==> 0XF8006160[9:0] = 0x00000081U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000081U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcf + // .. .. ==> 0XF8006168[10:0] = 0x000000CFU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CFU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF800616C[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF8006170[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcd + // .. .. ==> 0XF8006174[10:0] = 0x000000CDU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CDU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF800617C[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006180[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006184[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc1 + // .. .. ==> 0XF8006188[9:0] = 0x000000C1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000728[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF800072C[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000730[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000730[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000734[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000734[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007B8[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007BC[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/fpga/usrp3/top/e320/ip/e320_ps_bd/ps7_init_gpl.c b/fpga/usrp3/top/e320/ip/e320_ps_bd/ps7_init_gpl.c new file mode 100644 index 000000000..dd9994e98 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/e320_ps_bd/ps7_init_gpl.c @@ -0,0 +1,13326 @@ +/****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see <http://www.gnu.org/licenses/> +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xc + // .. ==> 0XF8000158[13:8] = 0x0000000CU + // .. ==> MASK : 0x00003F00U VAL : 0x00000C00U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x5 + // .. .. ==> 0XF8000180[25:20] = 0x00000005U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000190[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x3 + // .. .. ==> 0XF8000190[25:20] = 0x00000003U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF80001A0[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF800612C[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0x7a + // .. .. ==> 0XF800612C[19:10] = 0x0000007AU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006130[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006130[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006134[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006134[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1 + // .. .. ==> 0XF8006138[9:0] = 0x00000001U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000001U + // .. .. reg_phy_gatelvl_init_ratio = 0x78 + // .. .. ==> 0XF8006138[19:10] = 0x00000078U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006154[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF8006158[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF800615C[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x81 + // .. .. ==> 0XF8006160[9:0] = 0x00000081U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000081U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcf + // .. .. ==> 0XF8006168[10:0] = 0x000000CFU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CFU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF800616C[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF8006170[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcd + // .. .. ==> 0XF8006174[10:0] = 0x000000CDU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CDU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF800617C[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006180[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006184[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc1 + // .. .. ==> 0XF8006188[9:0] = 0x000000C1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000728[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF800072C[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000730[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000730[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000734[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000734[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007B8[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007BC[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. .. START: AFI2 SECURE REGISTER + // .. .. FINISH: AFI2 SECURE REGISTER + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xc + // .. ==> 0XF8000158[13:8] = 0x0000000CU + // .. ==> MASK : 0x00003F00U VAL : 0x00000C00U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x5 + // .. .. ==> 0XF8000180[25:20] = 0x00000005U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000190[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x3 + // .. .. ==> 0XF8000190[25:20] = 0x00000003U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF80001A0[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF800612C[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0x7a + // .. .. ==> 0XF800612C[19:10] = 0x0000007AU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006130[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006130[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006134[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006134[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1 + // .. .. ==> 0XF8006138[9:0] = 0x00000001U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000001U + // .. .. reg_phy_gatelvl_init_ratio = 0x78 + // .. .. ==> 0XF8006138[19:10] = 0x00000078U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006154[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF8006158[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF800615C[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x81 + // .. .. ==> 0XF8006160[9:0] = 0x00000081U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000081U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcf + // .. .. ==> 0XF8006168[10:0] = 0x000000CFU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CFU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF800616C[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF8006170[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcd + // .. .. ==> 0XF8006174[10:0] = 0x000000CDU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CDU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF800617C[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006180[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006184[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc1 + // .. .. ==> 0XF8006188[9:0] = 0x000000C1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000728[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF800072C[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000730[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000730[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000734[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000734[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007B8[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007BC[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xc + // .. ==> 0XF8000158[13:8] = 0x0000000CU + // .. ==> MASK : 0x00003F00U VAL : 0x00000C00U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x5 + // .. .. ==> 0XF8000180[25:20] = 0x00000005U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000190[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x3 + // .. .. ==> 0XF8000190[25:20] = 0x00000003U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF80001A0[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF800612C[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0x7a + // .. .. ==> 0XF800612C[19:10] = 0x0000007AU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006130[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006130[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006134[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006134[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1 + // .. .. ==> 0XF8006138[9:0] = 0x00000001U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000001U + // .. .. reg_phy_gatelvl_init_ratio = 0x78 + // .. .. ==> 0XF8006138[19:10] = 0x00000078U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006154[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF8006158[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF800615C[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x81 + // .. .. ==> 0XF8006160[9:0] = 0x00000081U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000081U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcf + // .. .. ==> 0XF8006168[10:0] = 0x000000CFU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CFU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF800616C[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF8006170[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcd + // .. .. ==> 0XF8006174[10:0] = 0x000000CDU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CDU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF800617C[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006180[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006184[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc1 + // .. .. ==> 0XF8006188[9:0] = 0x000000C1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000728[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF800072C[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000730[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000730[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000734[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000734[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007B8[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007BC[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/fpga/usrp3/top/e320/ip/fifo_4k_2clk/Makefile.inc b/fpga/usrp3/top/e320/ip/fifo_4k_2clk/Makefile.inc new file mode 100644 index 000000000..e022d9a1c --- /dev/null +++ b/fpga/usrp3/top/e320/ip/fifo_4k_2clk/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci + +IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \ +fifo_4k_2clk.xci.out \ +synth/fifo_4k_2clk.vhd \ +) + +$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci + $(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/e320/ip/fifo_4k_2clk/fifo_4k_2clk.xci b/fpga/usrp3/top/e320/ip/fifo_4k_2clk/fifo_4k_2clk.xci new file mode 100644 index 000000000..888840273 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/fifo_4k_2clk/fifo_4k_2clk.xci @@ -0,0 +1,576 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>fifo_4k_2clk</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ARESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">9</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">511</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">510</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">fifo_4k_2clk</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">511</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">510</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Disable_Timing_Violations" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Extra_Logic" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/e320/ip/fifo_short_2clk/Makefile.inc b/fpga/usrp3/top/e320/ip/fifo_short_2clk/Makefile.inc new file mode 100644 index 000000000..8c5c54213 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/fifo_short_2clk/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_FIFO_SHORT_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_short_2clk/fifo_short_2clk.xci + +IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \ +fifo_short_2clk.xci.out \ +synth/fifo_short_2clk.vhd \ +) + +$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci + $(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/e320/ip/fifo_short_2clk/fifo_short_2clk.xci b/fpga/usrp3/top/e320/ip/fifo_short_2clk/fifo_short_2clk.xci new file mode 100644 index 000000000..cc0f896b8 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/fifo_short_2clk/fifo_short_2clk.xci @@ -0,0 +1,578 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>fifo_short_2clk</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ARESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">31</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">30</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">6</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">6</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">fifo_short_2clk</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">31</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">30</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">6</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">6</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Extra_Logic" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.synchronization_stages" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/Makefile.inc b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/Makefile.inc new file mode 100644 index 000000000..413db0f83 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/Makefile.inc @@ -0,0 +1,49 @@ +# +# Copyright 2008-2013 Ettus Research LLC +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +ONE_GIGE_PHY_SRCS = \ +$(IP_DIR)/one_gig_eth_pcs_pma/one_gige_phy.v \ +$(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) + +IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/, \ +one_gig_eth_pcs_pma_example_design.v \ +one_gig_eth_pcs_pma_reset_sync_ex.v \ +one_gig_eth_pcs_pma_sync_block_ex.v \ +one_gig_eth_pcs_pma_tx_elastic_buffer.v \ +one_gig_eth_pcs_pma_clocking.v \ +one_gig_eth_pcs_pma_gt_common.v \ +one_gig_eth_pcs_pma_resets.v \ +one_gig_eth_pcs_pma_support.v \ +) + +IP_ONE_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci + +IP_ONE_GIG_ETH_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/one_gig_eth_pcs_pma/, \ +one_gig_eth_pcs_pma.xci.out \ +synth/one_gig_eth_pcs_pma_block.v \ +synth/one_gig_eth_pcs_pma_reset_sync.v \ +synth/one_gig_eth_pcs_pma.v \ +synth/one_gig_eth_pcs_pma_ooc.xdc \ +synth/one_gig_eth_pcs_pma_sync_block.v \ +synth/one_gig_eth_pcs_pma.xdc \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_gt.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard.v \ +synth/transceiver/one_gig_eth_pcs_pma_transceiver.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_init.v \ +synth/transceiver/one_gig_eth_pcs_pma_reset_wtd_timer.v \ +synth/transceiver/one_gig_eth_pcs_pma_tx_startup_fsm.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_multi_gt.v \ +synth/transceiver/one_gig_eth_pcs_pma_rx_startup_fsm.v \ +) + +$(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) + +$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci + $(call BUILD_VIVADO_IP,one_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) + cp $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v.orig + patch $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch + cp $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_support.v $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_support.v.orig + patch $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_support.v $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v.patch diff --git a/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci new file mode 100644 index 000000000..ae93c645d --- /dev/null +++ b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci @@ -0,0 +1,352 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>one_gig_eth_pcs_pma</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="gig_ethernet_pcs_pma" spirit:version="16.1"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_INTERRUPT_PORT.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_INTERRUPT_PORT_0.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_INTERRUPT_PORT_1.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_INTERRUPT_PORT_2.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK104_OUT_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK104_OUT_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK104_OUT_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK104_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK104_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK104_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK104_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK104_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK125M_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK125M_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK125M_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK125_OUT_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK125_OUT_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK125_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK208_OUT_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK208_OUT_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK208_OUT_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK208_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK208_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK208_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK208_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK208_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK312_OUT_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK312_OUT_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK312_OUT_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK312_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK312_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK312_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK312_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK312_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK625_OUT_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK625_OUT_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK625_OUT_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK625_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK625_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK625_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK625_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK625_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK_PORT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK_PORT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_MDIO_PCS_PMA.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_MDIO_PCS_PMA_0.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_MDIO_PCS_PMA_1.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_MDIO_PCS_PMA_2.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT0_PLL0RESET_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_BUFG_OUT_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_BUFG_OUT_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_BUFG_OUT_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_BUFG_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_BUFG_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_BUFG_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_BUFG_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_BUFG_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_IN.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_IN.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_OUT_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_OUT_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_OUT_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTREFCLK_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTX_CLK_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTX_CLK_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTX_CLK_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTX_CLK_PORT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTX_CLK_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTX_CLK_PORT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLK_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLK_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLK_PORT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLK_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLK_PORT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLOCK_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLOCK_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLOCK_PORT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLOCK_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INDEPENDENT_CLOCK_PORT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MDIO_PCS_PMA.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MDIO_PCS_PMA_0.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MDIO_PCS_PMA_1.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MDIO_PCS_PMA_2.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RESET_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RESET_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RX_CLK0_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RX_CLK0_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RX_CLK0_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RX_CLK0_PORT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RX_CLK0_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RX_CLK0_PORT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_TX_CLK_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_TX_CLK_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_TX_CLK_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_TX_CLK_PORT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_TX_CLK_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_TX_CLK_PORT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK125_IN.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK156_25_IN.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK625_IN.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK_PORT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK_PORT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST_125_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXOUTCLK_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXOUTCLK_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXOUTCLK_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXOUTCLK_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK2_OUT_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK2_OUT_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK2_OUT_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK2_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK2_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK2_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK2_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK2_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK_OUT_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK_OUT_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK_OUT_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXUSERCLK_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SGMII_CLK_EN_0_PORT.POLARITY">ACTIVE_LOW</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SGMII_CLK_EN_1_PORT.POLARITY">ACTIVE_LOW</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SGMII_CLK_EN_2_PORT.POLARITY">ACTIVE_LOW</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SGMII_CLK_EN_PORT.POLARITY">ACTIVE_LOW</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_RESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK2_OUT_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK2_OUT_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK2_OUT_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK2_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK2_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK2_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK2_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK2_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK_OUT_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK_OUT_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK_OUT_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK_OUT_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USERCLK_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EMAC_IF_TEMAC">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXAMPLE_SIMULATION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_1588">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_8_or_9_family">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_InstantiateBitslice0">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_RxLane0_Placement">DIFF_PAIR_0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_RxLane1_Placement">DIFF_PAIR_1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_RxNibbleBitslice0Used">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_TxLane0_Placement">DIFF_PAIR_0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_TxLane1_Placement">DIFF_PAIR_1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_architecture">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_clock_selection">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">one_gig_eth_pcs_pma</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_drpclkrate">50.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_dynamic_switching">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_elaboration_transient_dir">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_enable_async_lvds">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_enable_async_lvds_rx_only">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_enable_async_sgmii">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_enable_tx_userclk_reset_port">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_family">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_dmonitorout_width">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_drpaddr_width">9</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc">X0Y0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_rxmonitorout_width">7</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_txdiffctrl_width">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_type">GTH</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gtinex">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_an">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_axil">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_ext_mdio">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_mdio">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_is_2_5g">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_is_sgmii">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_num_of_lanes">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_refclk_src">clk0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_refclkrate">125</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_rx_gmii_clk_src">TXOUTCLK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_sgmii_fabric_buffer">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_sgmii_phy_mode">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_sub_core_name">one_gig_eth_pcs_pma_gt</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_support_level">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_transceiver_type">GTXE2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_transceivercontrol">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_tx_in_upper_nibble">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_use_lvds">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_use_tbi">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_use_transceiver">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xdevicefamily">xc7z045</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.characterization">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_rx_byte_width">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXILite_Interface">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Auto_Negotiation">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ClockSelection">Sync</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">one_gig_eth_pcs_pma</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFFCLK_BOARD_INTERFACE">Custom</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DrpClkRate">50.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMAC_IF_TEMAC">TEMAC</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ETHERNET_BOARD_INTERFACE">Custom</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXAMPLE_SIMULATION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EnableAsyncSGMII">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_1588">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_1588_1step">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Ext_Management_Interface">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_Location">X0Y0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_Type">GTH</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GTinEx">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.InstantiateBitslice0">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LvdsRefClk">125</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MDIO_BOARD_INTERFACE">Custom</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Management_Interface">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MaxDataRate">1G</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NumOfLanes">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Physical_Interface">Transceiver</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RefClkRate">125</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RefClkSrc">clk0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RxGmiiClkSrc">TXOUTCLK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RxLane0_Placement">DIFF_PAIR_0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RxLane1_Placement">DIFF_PAIR_1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RxNibbleBitslice0Used">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SGMII_Mode">10_100_1000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SGMII_PHY_Mode">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Standard">1000BASEX</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SupportLevel">Include_Shared_Logic_in_Example_Design</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Timer_Format">Time_of_day</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverControl">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TxLane0_Placement">DIFF_PAIR_0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TxLane1_Placement">DIFF_PAIR_1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Tx_In_Upper_Nibble">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z045</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">6</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Auto_Negotiation" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch new file mode 100644 index 000000000..41f963797 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch @@ -0,0 +1,25 @@ +65,66d64 +< input gtrefclk_p, // Differential +ve of reference clock for MGT: 125MHz, very high quality. +< input gtrefclk_n, // Differential -ve of reference clock for MGT: 125MHz, very high quality. +70,71d67 +< output gtrefclk, // gtrefclk routed through an IBUFG. +< output gtrefclk_bufg, // gtrefclk routed through a BUFG for driving logic. +88d83 +< wire gtrefclk_i; +93,108d87 +< // Clock circuitry for the Transceiver uses a differential input clock. +< // gtrefclk is routed to the tranceiver. +< IBUFDS_GTE2 ibufds_gtrefclk ( +< .I (gtrefclk_p), +< .IB (gtrefclk_n), +< .CEB (1'b0), +< .O (gtrefclk_i), +< .ODIV2 () +< ); +< +< assign gtrefclk = gtrefclk_i; +< +< BUFG bufg_gtrefclk ( +< .I (gtrefclk_i), +< .O (gtrefclk_bufg) +< ); diff --git a/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v.patch b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v.patch new file mode 100644 index 000000000..277c890f1 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v.patch @@ -0,0 +1,17 @@ +70,73c70,71 +< input gtrefclk_p, // differential clock +< input gtrefclk_n, // differential clock +< output gtrefclk_out, // Very high quality clock for GT transceiver. +< output gtrefclk_bufg_out, +--- +> input gtrefclk, // gtrefclk routed through an IBUFG. +> input gtrefclk_bufg, // gtrefclk routed through a BUFG for driving logic. +125,126d122 +< wire gtrefclk; // High quality clock +< wire gtrefclk_bufg; +205,206d200 +< .gtrefclk_p (gtrefclk_p), +< .gtrefclk_n (gtrefclk_n), +210,211d203 +< .gtrefclk (gtrefclk), +< .gtrefclk_bufg (gtrefclk_bufg), diff --git a/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gige_phy.v b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gige_phy.v new file mode 100644 index 000000000..f30f98fc3 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gige_phy.v @@ -0,0 +1,102 @@ +// +// Copyright 2014 Ettus Research LLC +// + +module one_gige_phy +( + input independent_clock, + + // Tranceiver Interface + //--------------------- + input gtrefclk, // Reference clock for MGT: 125MHz, very high quality. + input gtrefclk_bufg, // Reference clock routed through a BUFG + output txp, // Differential +ve of serial transmission from PMA to PMD. + output txn, // Differential -ve of serial transmission from PMA to PMD. + input rxp, // Differential +ve for serial reception from PMD to PMA. + input rxn, // Differential -ve for serial reception from PMD to PMA. + + // GMII Interface (client MAC <=> PCS) + //------------------------------------ + output gmii_clk, // Receive clock to client MAC. + input [7:0] gmii_txd, // Transmit data from client MAC. + input gmii_tx_en, // Transmit control signal from client MAC. + input gmii_tx_er, // Transmit control signal from client MAC. + output reg [7:0] gmii_rxd, // Received Data to client MAC. + output reg gmii_rx_dv, // Received control signal to client MAC. + output reg gmii_rx_er, // Received control signal to client MAC. + + // Management: MDIO Interface + //--------------------------- + input mdc, // Management Data Clock + input mdio_i, // Management Data In + output mdio_o, // Management Data Out + output mdio_t, // Management Data Tristate + input [4:0] phyaddr, // MDIO PHY Address + input [4:0] configuration_vector, // Alternative to MDIO interface. + input configuration_valid, // Validation signal for Config vector + + // General IO's + //------------- + output [15:0] status_vector, // Core status. + input reset, // Asynchronous reset for entire core. + input signal_detect // Input from PMD to indicate presence of optical input. +); + + wire resetdone; // To indicate that the GT transceiver has completed its reset cycle + wire userclk; // 62.5MHz clock for GT transceiver Tx/Rx user clocks + wire userclk2; // 125MHz clock for core reference clock. + wire rxuserclk2; + wire gmii_isolate; // internal gmii_isolate signal. + + wire [7:0] gmii_rxd_int; + wire gmii_rx_dv_int; + wire gmii_rx_er_int; + + always @(posedge gmii_clk) begin + gmii_rxd <= gmii_rxd_int; + gmii_rx_dv <= gmii_rx_dv_int; + gmii_rx_er <= gmii_rx_er_int; + end + + //---------------------------------------------------------------------------- + // Instantiate core wrapper + //---------------------------------------------------------------------------- + one_gig_eth_pcs_pma_support core_support_i ( + .gtrefclk (gtrefclk), + .gtrefclk_bufg (gtrefclk_bufg), + .txp (txp), + .txn (txn), + .rxp (rxp), + .rxn (rxn), + .mmcm_locked_out (), + .userclk_out (userclk), + .userclk2_out (userclk2), + .rxuserclk_out (), + .rxuserclk2_out (rxuserclk2), + .independent_clock_bufg(independent_clock), + .pma_reset_out (), + .resetdone (resetdone), + .gmii_txd (gmii_txd), + .gmii_tx_en (gmii_tx_en), + .gmii_tx_er (gmii_tx_er), + .gmii_rxd (gmii_rxd_int), + .gmii_rx_dv (gmii_rx_dv_int), + .gmii_rx_er (gmii_rx_er_int), + .gmii_isolate (gmii_isolate), + .mdc (mdc), + .mdio_i (mdio_i), + .mdio_o (mdio_o), + .mdio_t (mdio_t), + .phyaddr (phyaddr), + .configuration_vector (configuration_vector), + .configuration_valid (configuration_valid), + .status_vector (status_vector), + .reset (reset), + .signal_detect (signal_detect), + .gt0_qplloutclk_out (), + .gt0_qplloutrefclk_out () + ); + + assign gmii_clk = userclk2; + +endmodule // one_gige_phy diff --git a/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/Makefile.inc b/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/Makefile.inc new file mode 100644 index 000000000..899260fe0 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/Makefile.inc @@ -0,0 +1,42 @@ +# +# Copyright 2008-2013 Ettus Research LLC +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +TEN_GIGE_PHY_SRCS = \ +$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v \ +$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gige_phy.v \ +$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) + +IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma_ex/, \ +imports/ten_gig_eth_pcs_pma_example_design.v \ +imports/ten_gig_eth_pcs_pma_ff_synchronizer_rst2.v \ +imports/ten_gig_eth_pcs_pma_shared_clock_and_reset.v \ +imports/ten_gig_eth_pcs_pma_support.v \ +imports/ten_gig_eth_pcs_pma_gt_common.v \ +) + +IP_TEN_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci + +IP_TEN_GIG_ETH_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/, \ +ten_gig_eth_pcs_pma.xci.out \ +synth/ten_gig_eth_pcs_pma_block.v \ +synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_multi_gt.v \ +synth/ten_gig_eth_pcs_pma_cable_pull_logic.v \ +synth/ten_gig_eth_pcs_pma_local_clock_and_reset.v \ +synth/ten_gig_eth_pcs_pma_clocks.xdc \ +synth/ten_gig_eth_pcs_pma_ooc.xdc \ +synth/ten_gig_eth_pcs_pma_ff_synchronizer_rst.v \ +synth/ten_gig_eth_pcs_pma_sim_speedup_controller.v \ +synth/ten_gig_eth_pcs_pma_ff_synchronizer.v \ +synth/ten_gig_eth_pcs_pma.v \ +synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \ +synth/ten_gig_eth_pcs_pma.xdc \ +) + +$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) + +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci + $(call BUILD_VIVADO_IP,ten_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) + diff --git a/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci b/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci new file mode 100644 index 000000000..140a5049b --- /dev/null +++ b/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci @@ -0,0 +1,200 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>ten_gig_eth_pcs_pma</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="ten_gig_eth_pcs_pma" spirit:version="6.0"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESET_CORECLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESET_CORECLK_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESET_DATAPATHCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESET_RXUSRCLK2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DCLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DCLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DCLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DCLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DCLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DCLK_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTRXRESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTRXRESET_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTTXRESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTTXRESET_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_LATCLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_LATCLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_LATCLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_LATCLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_LATCLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_LATCLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFCLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFCLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFCLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFCLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFCLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFCLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFRESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MDIO_INTERFACE.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PCS_RESETOUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RESETOUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK_DIFF_PORT.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET_TX_BUFG_GT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLK_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLK_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLK_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRESET_RXUSRCLK2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_IN.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_IN.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_IN.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_IN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_IN.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXRESET_TXUSRCLK2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_1588">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">ten_gig_eth_pcs_pma</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_dclkrate">78.125</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_family">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc">X0Y0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gtif_width">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gttype">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_an">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_fec">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_mdio">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_is_32bit">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_is_kr">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_no_ebuff">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_refclk">clk0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_refclkrate">156</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_speed10_25">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_sub_core_name">ten_gig_eth_pcs_pma_gt</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">ten_gig_eth_pcs_pma</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DClkRate">78.125</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IEEE_1588">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Locations">X0Y0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MDIO_Management">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RefClk">clk0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RefClkRate">156.25</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SupportLevel">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Timer_Format">Time_of_day</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverControl">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverInExample">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.autonegotiation">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.base_kr">BASE-R</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.baser32">64bit</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.fec">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.no_ebuff">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.speed10_25">10Gig</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vu_gt_type">GTH</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z045</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DClkRate" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TransceiverControl" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v b/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v new file mode 100644 index 000000000..aa4db148f --- /dev/null +++ b/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v @@ -0,0 +1,249 @@ +// +// Copyright 2008-2013 Ettus Research LLC +// + +module ten_gige_phy +( + input refclk, + input clk156, + input dclk, + input areset, + input sim_speedup_control, + input [63:0] xgmii_txd, + input [7:0] xgmii_txc, + output reg [63:0] xgmii_rxd, + output reg [7:0] xgmii_rxc, + output txp, + output txn, + input rxp, + input rxn, + input mdc, + input mdio_in, + output reg mdio_out, + output reg mdio_tri, + input [4:0] prtad, + output [7:0] core_status, + output resetdone, + input signal_detect, + input tx_fault, + output tx_disable +); + + reg [63:0] xgmii_txd_reg; + reg [7:0] xgmii_txc_reg; + wire [63:0] xgmii_rxd_int; + wire [7:0] xgmii_rxc_int; + + // Add a pipeline to the xmgii_tx inputs, to aid timing closure + always @(posedge clk156) + begin + xgmii_txd_reg <= xgmii_txd; + xgmii_txc_reg <= xgmii_txc; + end + + // Add a pipeline to the xmgii_rx outputs, to aid timing closure + always @(posedge clk156) + begin + xgmii_rxd <= xgmii_rxd_int; + xgmii_rxc <= xgmii_rxc_int; + end + + wire mdio_out_int; + wire mdio_tri_int; + reg mdc_reg; + reg mdio_in_reg; + + // Add a pipeline to the mdio in/outputs, to aid timing closure + // This is safe because the mdio clock is running so slowly + always @(posedge clk156) + begin + mdio_out <= mdio_out_int; + mdio_tri <= mdio_tri_int; + mdc_reg <= mdc; + mdio_in_reg <= mdio_in; + end + + // Signal declarations + wire txclk322; + wire qplloutclk; + wire qplloutrefclk; + wire qplllock; + + wire drp_gnt; + wire drp_req; + wire drp_den_o; + wire drp_dwe_o; + wire [15:0] drp_daddr_o; + wire [15:0] drp_di_o; + wire drp_drdy_o; + wire [15:0] drp_drpdo_o; + wire drp_den_i; + wire drp_dwe_i; + wire [15:0] drp_daddr_i; + wire [15:0] drp_di_i; + wire drp_drdy_i; + wire [15:0] drp_drpdo_i; + + wire tx_resetdone_int; + wire rx_resetdone_int; + + wire areset_clk156; + wire gttxreset; + wire gtrxreset; + wire qpllreset; + wire qplllock_txusrclk2; + wire gttxreset_txusrclk2; + wire reset_counter_done; + wire txusrclk; + wire txusrclk2; + reg txuserrdy; + + assign resetdone = tx_resetdone_int && rx_resetdone_int; + + // If no arbitration is required on the GT DRP ports then connect REQ to GNT + // and connect other signals i <= o; + assign drp_gnt = drp_req; + assign drp_den_i = drp_den_o; + assign drp_dwe_i = drp_dwe_o; + assign drp_daddr_i = drp_daddr_o; + assign drp_di_i = drp_di_o; + assign drp_drdy_i = drp_drdy_o; + assign drp_drpdo_i = drp_drpdo_o; + + // Instantiate the 10GBASER/KR GT Common block + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware + ) ten_gig_eth_pcs_pma_gt_common_block ( + .refclk(refclk), + .qpllreset(qpllreset), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk) + ); + + // Asynch reset synchronizers... + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b1) + ) areset_clk156_sync_i ( + .clk(clk156), + .rst(areset), + .data_in(1'b0), + .data_out(areset_clk156) + ); + + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b0) + ) qplllock_txusrclk2_sync_i ( + .clk(txusrclk2), + .rst(!qplllock), + .data_in(1'b1), + .data_out(qplllock_txusrclk2) + ); + + reg [7:0] reset_counter = 8'h00; + reg [3:0] reset_pulse = 4'b1110; + assign reset_counter_done = reset_counter[7]; + + // Hold off the GT resets until 500ns after configuration. + // 128 ticks at 6.4ns period will be >> 500 ns. + always @(posedge clk156) + begin + if (!reset_counter[7]) + reset_counter <= reset_counter + 1'b1; + else + reset_counter <= reset_counter; + end + + always @(posedge clk156) + begin + if (areset_clk156 == 1'b1) + reset_pulse <= 4'b1110; + else if(reset_counter[7]) + reset_pulse <= {1'b0, reset_pulse[3:1]}; + end + + assign qpllreset = reset_pulse[0]; + assign gttxreset = reset_pulse[0]; + assign gtrxreset = reset_pulse[0]; + + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b1) + ) gttxreset_txusrclk2_sync_i ( + .clk(txusrclk2), + .rst(gttxreset), + .data_in(1'b0), + .data_out(gttxreset_txusrclk2) + ); + + always @(posedge txusrclk2 or posedge gttxreset_txusrclk2) + begin + if(gttxreset_txusrclk2) + txuserrdy <= 1'b0; + else + txuserrdy <= qplllock_txusrclk2; + end + + BUFG tx322clk_bufg_i ( + .I (txclk322), + .O (txusrclk) + ); + + assign txusrclk2 = txusrclk; + + // Instantiate the 10GBASER/KR Block Level + ten_gig_eth_pcs_pma ten_gig_eth_pcs_pma_i ( + .coreclk(clk156), + .dclk(dclk), + .txusrclk(txusrclk), + .txusrclk2(txusrclk2), + .txoutclk(txclk322), + .areset_coreclk(areset_clk156), + .txuserrdy(txuserrdy), + .areset(areset), + .gttxreset(gttxreset), + .gtrxreset(gtrxreset), + .sim_speedup_control(sim_speedup_control), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .reset_counter_done(reset_counter_done), + .xgmii_txd(xgmii_txd_reg), + .xgmii_txc(xgmii_txc_reg), + .xgmii_rxd(xgmii_rxd_int), + .xgmii_rxc(xgmii_rxc_int), + .txp(txp), + .txn(txn), + .rxp(rxp), + .rxn(rxn), + .mdc(mdc_reg), + .mdio_in(mdio_in_reg), + .mdio_out(mdio_out_int), + .mdio_tri(mdio_tri_int), + .prtad(prtad), + .core_status(core_status), + .tx_resetdone(tx_resetdone_int), + .rx_resetdone(rx_resetdone_int), + .signal_detect(signal_detect), + .tx_fault(tx_fault), + .drp_req(drp_req), + .drp_gnt(drp_gnt), + .drp_den_o(drp_den_o), + .drp_dwe_o(drp_dwe_o), + .drp_daddr_o(drp_daddr_o), + .drp_di_o(drp_di_o), + .drp_drdy_o(drp_drdy_o), + .drp_drpdo_o(drp_drpdo_o), + .drp_den_i(drp_den_i), + .drp_dwe_i(drp_dwe_i), + .drp_daddr_i(drp_daddr_i), + .drp_di_i(drp_di_i), + .drp_drdy_i(drp_drdy_i), + .drp_drpdo_i(drp_drpdo_i), + .pma_pmd_type(3'b101), + .tx_disable(tx_disable) + ); + +endmodule diff --git a/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v b/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v new file mode 100644 index 000000000..7c1d09fe6 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v @@ -0,0 +1,37 @@ +// +// Copyright 2008-2013 Ettus Research LLC +// + +module ten_gige_phy_clk_gen +( + input refclk_ibuf, + output clk156, + output dclk +); + + wire dclk_buf; + + BUFG clk156_bufg_inst ( + .I (refclk_ibuf), + .O (clk156) + ); + + // Dividing independent clock by 2 as source for DRP clock + BUFR # ( + .BUFR_DIVIDE ("2") + ) dclk_divide_by_2_buf ( + .I (clk156), + .O (dclk_buf), + .CE (1'b1), + .CLR (1'b0) + ); + + BUFG dclk_bufg_i ( + .I (dclk_buf), + .O (dclk) + ); + +endmodule + + + diff --git a/fpga/usrp3/top/e320/mb_pins.xdc b/fpga/usrp3/top/e320/mb_pins.xdc new file mode 100644 index 000000000..aa299133c --- /dev/null +++ b/fpga/usrp3/top/e320/mb_pins.xdc @@ -0,0 +1,473 @@ +# +# Copyright 2018 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Motherboard Pin Definitions for the E320. +# + +## Power ################################################################### +## +############################################################################ + +# Power Enable, Bank 10 +set_property PACKAGE_PIN AK15 [get_ports {ENA_PAPWR}] +set_property IOSTANDARD LVCMOS33 [get_ports {ENA_PAPWR}] + +## SFP + ################################################################### +## +############################################################################ + +## Power +#set_property PACKAGE_PIN AB9 [get_ports {+1V2_MGT_AVTT}] +#set_property IOSTANDARD <IOSTD_BANK112> [get_ports {+1V2_MGT_AVTT}] + +## Clocks, Bank 112 +set_property PACKAGE_PIN R7 [get_ports {CLK_MGT_156_25M_N}] +set_property PACKAGE_PIN R8 [get_ports {CLK_MGT_156_25M_P}] + +set_property PACKAGE_PIN N7 [get_ports {CLK_MGT_125M_N}] +set_property PACKAGE_PIN N8 [get_ports {CLK_MGT_125M_P}] + +## MGT, Bank 112 +set_property PACKAGE_PIN V5 [get_ports {SFP1_RX_N}] +set_property PACKAGE_PIN V6 [get_ports {SFP1_RX_P}] +set_property PACKAGE_PIN T1 [get_ports {SFP1_TX_N}] +set_property PACKAGE_PIN T2 [get_ports {SFP1_TX_P}] + +## SFP Sideband, Bank 10, 3.3V +set_property PACKAGE_PIN AJ16 [get_ports {SFP1_RXLOS}] +set_property IOSTANDARD LVCMOS33 [get_ports {SFP1_RXLOS}] + +set_property PACKAGE_PIN AK13 [get_ports {SFP1_TXFAULT}] +set_property IOSTANDARD LVCMOS33 [get_ports {SFP1_TXFAULT}] + +set_property PACKAGE_PIN AK12 [get_ports {SFP1_TXDISABLE}] +set_property IOSTANDARD LVCMOS33 [get_ports {SFP1_TXDISABLE}] + +set_property PACKAGE_PIN AE17 [get_ports {SFP1_MOD_ABS}] +set_property IOSTANDARD LVCMOS33 [get_ports {SFP1_MOD_ABS}] + +set_property PACKAGE_PIN AJ18 [get_ports {SFP1_RS0}] +set_property PACKAGE_PIN AK16 [get_ports {SFP1_RS1}] +set_property IOSTANDARD LVCMOS33 [get_ports {SFP1_RS*}] + +set_property PACKAGE_PIN AB17 [get_ports {LED_LINK1}] +set_property IOSTANDARD LVCMOS33 [get_ports {LED_LINK1}] + +set_property PACKAGE_PIN AB16 [get_ports {LED_ACT1}] +set_property IOSTANDARD LVCMOS33 [get_ports {LED_ACT1}] + +## Used with N310 hardware +#set_property PACKAGE_PIN U25 [get_ports PANEL_LED_GPS] +#set_property PACKAGE_PIN T25 [get_ports PANEL_LED_LINK] +#set_property PACKAGE_PIN W29 [get_ports PANEL_LED_PPS] +#set_property PACKAGE_PIN V24 [get_ports PANEL_LED_REF] +#set_property IOSTANDARD LVCMOS33 [get_ports PANEL_LED_*] +#set_property DRIVE 4 [get_ports PANEL_LED_*] +#set_property SLEW SLOW [get_ports PANEL_LED_*] + +## XCVR #################################################################### +## Catalina AD9361 Connections +## -- Data Buses +## -- Clocks +## -- SPI +## -- TX Amplifier +## -- LEDs +## +############################################################################ + +set_property PACKAGE_PIN P25 [get_ports {XCVR_ENABLE}] +set_property PACKAGE_PIN T25 [get_ports {XCVR_SYNC}] +set_property PACKAGE_PIN P23 [get_ports {XCVR_TXNRX}] +set_property PACKAGE_PIN N27 [get_ports {XCVR_ENA_AGC}] +set_property PACKAGE_PIN P26 [get_ports {XCVR_RESET_N}] + +## AD9361 SPI, Bank 13, 1.8V +set_property PACKAGE_PIN T27 [get_ports {XCVR_SPI_CS_N}] +set_property PACKAGE_PIN N26 [get_ports {XCVR_SPI_MISO}] +set_property PACKAGE_PIN P24 [get_ports {XCVR_SPI_MOSI}] +set_property PACKAGE_PIN T24 [get_ports {XCVR_SPI_CLK}] + +set_property IOSTANDARD LVCMOS18 [get_ports {XCVR_*}] + +## Catalina TX Data Bus +set_property PACKAGE_PIN F3 [get_ports {TX_CLK_N}] +set_property PACKAGE_PIN F4 [get_ports {TX_CLK_P}] +set_property IOSTANDARD LVDS [get_ports {TX_CLK_*}] +# +set_property PACKAGE_PIN B4 [get_ports {TX_FRAME_N}] +set_property PACKAGE_PIN B5 [get_ports {TX_FRAME_P}] +set_property IOSTANDARD LVDS [get_ports {TX_FRAME_*}] +# +set_property PACKAGE_PIN L2 [get_ports {TX_DATA_N[0]}] +set_property PACKAGE_PIN L3 [get_ports {TX_DATA_P[0]}] +set_property PACKAGE_PIN D5 [get_ports {TX_DATA_N[1]}] +set_property PACKAGE_PIN E6 [get_ports {TX_DATA_P[1]}] +set_property PACKAGE_PIN A4 [get_ports {TX_DATA_N[2]}] +set_property PACKAGE_PIN A5 [get_ports {TX_DATA_P[2]}] +set_property PACKAGE_PIN J3 [get_ports {TX_DATA_N[3]}] +set_property PACKAGE_PIN J4 [get_ports {TX_DATA_P[3]}] +set_property PACKAGE_PIN D1 [get_ports {TX_DATA_N[4]}] +set_property PACKAGE_PIN E1 [get_ports {TX_DATA_P[4]}] +set_property PACKAGE_PIN E2 [get_ports {TX_DATA_N[5]}] +set_property PACKAGE_PIN E3 [get_ports {TX_DATA_P[5]}] +set_property IOSTANDARD LVDS [get_ports {TX_DATA_*[*]}] + +## Catalina RX Data Bus +set_property PACKAGE_PIN G4 [get_ports {RX_CLK_N}] +set_property PACKAGE_PIN G5 [get_ports {RX_CLK_P}] +set_property IOSTANDARD LVDS [get_ports {RX_CLK_*}] +set_property DIFF_TERM TRUE [get_ports {RX_CLK_*}] +# +set_property PACKAGE_PIN J6 [get_ports {RX_FRAME_N}] +set_property PACKAGE_PIN K6 [get_ports {RX_FRAME_P}] +set_property IOSTANDARD LVDS [get_ports {RX_FRAME_*}] +set_property DIFF_TERM TRUE [get_ports {RX_FRAME_*}] +# +set_property PACKAGE_PIN C3 [get_ports {RX_DATA_N[0]}] +set_property PACKAGE_PIN C4 [get_ports {RX_DATA_P[0]}] +set_property PACKAGE_PIN G6 [get_ports {RX_DATA_N[1]}] +set_property PACKAGE_PIN H6 [get_ports {RX_DATA_P[1]}] +set_property PACKAGE_PIN D3 [get_ports {RX_DATA_N[2]}] +set_property PACKAGE_PIN D4 [get_ports {RX_DATA_P[2]}] +set_property PACKAGE_PIN K1 [get_ports {RX_DATA_N[3]}] +set_property PACKAGE_PIN L1 [get_ports {RX_DATA_P[3]}] +set_property PACKAGE_PIN J5 [get_ports {RX_DATA_N[4]}] +set_property PACKAGE_PIN K5 [get_ports {RX_DATA_P[4]}] +set_property PACKAGE_PIN F2 [get_ports {RX_DATA_N[5]}] +set_property PACKAGE_PIN G2 [get_ports {RX_DATA_P[5]}] +set_property IOSTANDARD LVDS [get_ports {RX_DATA_*[*]}] +set_property DIFF_TERM TRUE [get_ports {RX_DATA_*[*]}] + +## TX Amp, Bank 13, 1.8V +set_property PACKAGE_PIN P29 [get_ports {TX_HFAMP1_ENA}] +set_property PACKAGE_PIN U29 [get_ports {TX_HFAMP2_ENA}] +set_property IOSTANDARD LVCMOS18 [get_ports {TX_HFAMP*_ENA}] + +set_property PACKAGE_PIN N29 [get_ports {TX_LFAMP1_ENA}] +set_property PACKAGE_PIN T29 [get_ports {TX_LFAMP2_ENA}] +set_property IOSTANDARD LVCMOS18 [get_ports {TX_LFAMP*_ENA}] + +# CTRL_OUT, Bank 13, 1.8 V +set_property PACKAGE_PIN V28 [get_ports {XCVR_CTRL_OUT[0]}] +set_property PACKAGE_PIN V29 [get_ports {XCVR_CTRL_OUT[1]}] +set_property PACKAGE_PIN W29 [get_ports {XCVR_CTRL_OUT[2]}] +set_property PACKAGE_PIN W30 [get_ports {XCVR_CTRL_OUT[3]}] +set_property PACKAGE_PIN V27 [get_ports {XCVR_CTRL_OUT[4]}] +set_property PACKAGE_PIN W28 [get_ports {XCVR_CTRL_OUT[5]}] +set_property PACKAGE_PIN W25 [get_ports {XCVR_CTRL_OUT[6]}] +set_property PACKAGE_PIN W26 [get_ports {XCVR_CTRL_OUT[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {XCVR_CTRL_OUT[*]}] +# Set pull-up on bits 6 and 7 to make the bitstream compatible with Rev A, +# where the signals don't exist. +set_property PULLUP TRUE [get_ports {XCVR_CTRL_OUT[6]}] +set_property PULLUP TRUE [get_ports {XCVR_CTRL_OUT[7]}] + +## RX/TX LEDs, Bank 10, 3.3 V +set_property PACKAGE_PIN AG14 [get_ports {RX1_GRN_ENA}] +set_property PACKAGE_PIN AG17 [get_ports {RX2_GRN_ENA}] +set_property IOSTANDARD LVCMOS33 [get_ports {RX*_GRN_ENA}] + +set_property PACKAGE_PIN AG16 [get_ports {TX1_RED_ENA}] +set_property PACKAGE_PIN AF15 [get_ports {TX2_RED_ENA}] +set_property IOSTANDARD LVCMOS33 [get_ports {TX*_RED_ENA}] + +set_property PACKAGE_PIN AG15 [get_ports {TXRX1_GRN_ENA}] +set_property PACKAGE_PIN AF18 [get_ports {TXRX2_GRN_ENA}] +set_property IOSTANDARD LVCMOS33 [get_ports {TXRX*_GRN_ENA}] + + +## PL DDR #################################################################### +## +############################################################################ + +## PL DDR, Bank 34,35 + +set_property PACKAGE_PIN G9 [get_ports {SYS_CLK_N}] +set_property PACKAGE_PIN H9 [get_ports {SYS_CLK_P}] +set_property PACKAGE_PIN D8 [get_ports {DDR3_ADDR[0]}] +set_property PACKAGE_PIN F9 [get_ports {DDR3_ADDR[1]}] +set_property PACKAGE_PIN A7 [get_ports {DDR3_ADDR[2]}] +set_property PACKAGE_PIN D9 [get_ports {DDR3_ADDR[3]}] +set_property PACKAGE_PIN H7 [get_ports {DDR3_ADDR[4]}] +set_property PACKAGE_PIN E8 [get_ports {DDR3_ADDR[5]}] +set_property PACKAGE_PIN F8 [get_ports {DDR3_ADDR[6]}] +set_property PACKAGE_PIN E7 [get_ports {DDR3_ADDR[7]}] +set_property PACKAGE_PIN C6 [get_ports {DDR3_ADDR[8]}] +set_property PACKAGE_PIN C7 [get_ports {DDR3_ADDR[9]}] +set_property PACKAGE_PIN B7 [get_ports {DDR3_ADDR[10]}] +set_property PACKAGE_PIN J9 [get_ports {DDR3_ADDR[11]}] +set_property PACKAGE_PIN D11 [get_ports {DDR3_ADDR[12]}] +set_property PACKAGE_PIN F7 [get_ports {DDR3_ADDR[13]}] +set_property PACKAGE_PIN D6 [get_ports {DDR3_ADDR[14]}] +set_property PACKAGE_PIN B6 [get_ports {DDR3_ADDR[15]}] +set_property PACKAGE_PIN C9 [get_ports {DDR3_BA[0]}] +set_property PACKAGE_PIN G7 [get_ports {DDR3_BA[1]}] +set_property PACKAGE_PIN B9 [get_ports {DDR3_BA[2]}] +set_property PACKAGE_PIN D10 [get_ports {DDR3_CAS_N}] +set_property PACKAGE_PIN E11 [get_ports {DDR3_CKE[0]}] +set_property PACKAGE_PIN H8 [get_ports {DDR3_CK_N[0]}] +set_property PACKAGE_PIN J8 [get_ports {DDR3_CK_P[0]}] +set_property PACKAGE_PIN E10 [get_ports {DDR3_CS_N[0]}] +set_property PACKAGE_PIN D16 [get_ports {DDR3_DM[0]}] +set_property PACKAGE_PIN C12 [get_ports {DDR3_DM[1]}] +set_property PACKAGE_PIN J13 [get_ports {DDR3_DM[2]}] +set_property PACKAGE_PIN F14 [get_ports {DDR3_DM[3]}] +set_property PACKAGE_PIN B16 [get_ports {DDR3_DQ[0]}] +set_property PACKAGE_PIN A17 [get_ports {DDR3_DQ[1]}] +set_property PACKAGE_PIN C16 [get_ports {DDR3_DQ[2]}] +set_property PACKAGE_PIN E15 [get_ports {DDR3_DQ[3]}] +set_property PACKAGE_PIN C17 [get_ports {DDR3_DQ[4]}] +set_property PACKAGE_PIN D14 [get_ports {DDR3_DQ[5]}] +set_property PACKAGE_PIN B17 [get_ports {DDR3_DQ[6]}] +set_property PACKAGE_PIN D15 [get_ports {DDR3_DQ[7]}] +set_property PACKAGE_PIN B12 [get_ports {DDR3_DQ[8]}] +set_property PACKAGE_PIN A13 [get_ports {DDR3_DQ[9]}] +set_property PACKAGE_PIN C11 [get_ports {DDR3_DQ[10]}] +set_property PACKAGE_PIN C14 [get_ports {DDR3_DQ[11]}] +set_property PACKAGE_PIN A12 [get_ports {DDR3_DQ[12]}] +set_property PACKAGE_PIN B14 [get_ports {DDR3_DQ[13]}] +set_property PACKAGE_PIN B11 [get_ports {DDR3_DQ[14]}] +set_property PACKAGE_PIN A14 [get_ports {DDR3_DQ[15]}] +set_property PACKAGE_PIN J16 [get_ports {DDR3_DQ[16]}] +set_property PACKAGE_PIN J14 [get_ports {DDR3_DQ[17]}] +set_property PACKAGE_PIN L15 [get_ports {DDR3_DQ[18]}] +set_property PACKAGE_PIN H14 [get_ports {DDR3_DQ[19]}] +set_property PACKAGE_PIN K15 [get_ports {DDR3_DQ[20]}] +set_property PACKAGE_PIN H13 [get_ports {DDR3_DQ[21]}] +set_property PACKAGE_PIN L14 [get_ports {DDR3_DQ[22]}] +set_property PACKAGE_PIN J15 [get_ports {DDR3_DQ[23]}] +set_property PACKAGE_PIN E13 [get_ports {DDR3_DQ[24]}] +set_property PACKAGE_PIN F15 [get_ports {DDR3_DQ[25]}] +set_property PACKAGE_PIN F13 [get_ports {DDR3_DQ[26]}] +set_property PACKAGE_PIN G16 [get_ports {DDR3_DQ[27]}] +set_property PACKAGE_PIN E12 [get_ports {DDR3_DQ[28]}] +set_property PACKAGE_PIN G15 [get_ports {DDR3_DQ[29]}] +set_property PACKAGE_PIN D13 [get_ports {DDR3_DQ[30]}] +set_property PACKAGE_PIN G14 [get_ports {DDR3_DQ[31]}] +set_property PACKAGE_PIN E17 [get_ports {DDR3_DQS_N[0]}] +set_property PACKAGE_PIN F17 [get_ports {DDR3_DQS_P[0]}] +set_property PACKAGE_PIN A15 [get_ports {DDR3_DQS_N[1]}] +set_property PACKAGE_PIN B15 [get_ports {DDR3_DQS_P[1]}] +set_property PACKAGE_PIN K13 [get_ports {DDR3_DQS_N[2]}] +set_property PACKAGE_PIN L13 [get_ports {DDR3_DQS_P[2]}] +set_property PACKAGE_PIN F12 [get_ports {DDR3_DQS_N[3]}] +set_property PACKAGE_PIN G12 [get_ports {DDR3_DQS_P[3]}] +set_property PACKAGE_PIN G11 [get_ports {DDR3_ODT[0]}] +set_property PACKAGE_PIN A10 [get_ports {DDR3_RAS_N}] +set_property PACKAGE_PIN B10 [get_ports {DDR3_RESET_N}] +set_property PACKAGE_PIN A9 [get_ports {DDR3_WE_N}] + +## Front Panel GPIO ######################################################## +## +############################################################################ + +# GPIO, Bank 12 +set_property PACKAGE_PIN AC26 [get_ports {EN_GPIO_2V5}] +set_property IOSTANDARD LVCMOS18 [get_ports {EN_GPIO_2V5}] + +set_property PACKAGE_PIN AA29 [get_ports {EN_GPIO_3V3}] +set_property IOSTANDARD LVCMOS18 [get_ports {EN_GPIO_3V3}] + +set_property PACKAGE_PIN AB30 [get_ports {EN_GPIO_VAR_SUPPLY}] +set_property IOSTANDARD LVCMOS18 [get_ports {EN_GPIO_VAR_SUPPLY}] + +set_property PACKAGE_PIN AF27 [get_ports {GPIO_PREBUFF[0]}] +set_property PACKAGE_PIN AF29 [get_ports {GPIO_PREBUFF[1]}] +set_property PACKAGE_PIN AE25 [get_ports {GPIO_PREBUFF[2]}] +set_property PACKAGE_PIN AF25 [get_ports {GPIO_PREBUFF[3]}] +set_property PACKAGE_PIN AJ30 [get_ports {GPIO_PREBUFF[4]}] +set_property PACKAGE_PIN AK30 [get_ports {GPIO_PREBUFF[5]}] +set_property PACKAGE_PIN AJ28 [get_ports {GPIO_PREBUFF[6]}] +set_property PACKAGE_PIN AJ29 [get_ports {GPIO_PREBUFF[7]}] + +set_property PACKAGE_PIN AA27 [get_ports {GPIO_DIR[0]}] +set_property PACKAGE_PIN AA28 [get_ports {GPIO_DIR[1]}] +set_property PACKAGE_PIN AB25 [get_ports {GPIO_DIR[2]}] +set_property PACKAGE_PIN AB26 [get_ports {GPIO_DIR[3]}] +set_property PACKAGE_PIN AE26 [get_ports {GPIO_DIR[4]}] +set_property PACKAGE_PIN AB27 [get_ports {GPIO_DIR[5]}] +set_property PACKAGE_PIN AC27 [get_ports {GPIO_DIR[6]}] +set_property PACKAGE_PIN Y25 [get_ports {GPIO_DIR[7]}] + +set_property PACKAGE_PIN AD26 [get_ports {GPIO_OE_N}] + +set_property IOSTANDARD LVCMOS18 [get_ports {GPIO_*}] + +## GPSDO ################################################################### +## +############################################################################ + +# GPSDO, Bank 13 +set_property PACKAGE_PIN R28 [get_ports {CLK_GPS_PWR_EN}] +set_property IOSTANDARD LVCMOS18 [get_ports {CLK_GPS_PWR_EN}] + +# GPSDO, Bank 10 +set_property PACKAGE_PIN AD14 [get_ports {GPS_ALARM}] +set_property PACKAGE_PIN AD13 [get_ports {GPS_INITSURV_N}] +set_property PACKAGE_PIN AH13 [get_ports {GPS_LOCK}] +set_property PACKAGE_PIN AE12 [get_ports {GPS_PHASELOCK}] +set_property PACKAGE_PIN AG12 [get_ports {GPS_RST_N}] +set_property PACKAGE_PIN AH14 [get_ports {GPS_SURVEY}] +set_property PACKAGE_PIN AF12 [get_ports {GPS_WARMUP}] + +set_property IOSTANDARD LVCMOS33 [get_ports {GPS_*}] + +## Daughterboard Connections ############################################### +## +############################################################################ + +# Switches, Bank 9 +set_property PACKAGE_PIN Y20 [get_ports {FE1_SEL[0]}] +set_property PACKAGE_PIN AA20 [get_ports {FE1_SEL[1]}] +set_property PACKAGE_PIN AC18 [get_ports {FE1_SEL[2]}] +set_property PACKAGE_PIN AA18 [get_ports {FE2_SEL[0]}] +set_property PACKAGE_PIN AA19 [get_ports {FE2_SEL[1]}] +set_property PACKAGE_PIN AB19 [get_ports {FE2_SEL[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FE*_SEL[*]}] + +set_property PACKAGE_PIN AC19 [get_ports {RX1_SEL[0]}] +set_property PACKAGE_PIN AD18 [get_ports {RX1_SEL[1]}] +set_property PACKAGE_PIN AB20 [get_ports {RX2_SEL[0]}] +set_property PACKAGE_PIN AD20 [get_ports {RX2_SEL[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {RX*_SEL[*]}] + +# Switches, Bank 11 +set_property PACKAGE_PIN AB21 [get_ports {RX1_BSEL[0]}] +set_property PACKAGE_PIN AB22 [get_ports {RX1_BSEL[1]}] +set_property PACKAGE_PIN W21 [get_ports {RX1_BSEL[2]}] +set_property PACKAGE_PIN Y21 [get_ports {RX1_BSEL[3]}] +set_property PACKAGE_PIN AA24 [get_ports {RX1_BSEL[4]}] +set_property PACKAGE_PIN AB24 [get_ports {RX1_BSEL[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {RX1_BSEL[*]}] + +set_property PACKAGE_PIN AC24 [get_ports {RX2_BSEL[0]}] +set_property PACKAGE_PIN AD24 [get_ports {RX2_BSEL[1]}] +set_property PACKAGE_PIN AG24 [get_ports {RX2_BSEL[2]}] +set_property PACKAGE_PIN AG25 [get_ports {RX2_BSEL[3]}] +set_property PACKAGE_PIN AD21 [get_ports {RX2_BSEL[4]}] +set_property PACKAGE_PIN AE21 [get_ports {RX2_BSEL[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {RX2_BSEL[*]}] + +set_property PACKAGE_PIN AK17 [get_ports {TX1_BSEL[0]}] +set_property PACKAGE_PIN AK18 [get_ports {TX1_BSEL[1]}] +set_property PACKAGE_PIN AH19 [get_ports {TX1_BSEL[2]}] +set_property PACKAGE_PIN AJ19 [get_ports {TX1_BSEL[3]}] +set_property PACKAGE_PIN AF19 [get_ports {TX1_BSEL[4]}] +set_property PACKAGE_PIN AG19 [get_ports {TX1_BSEL[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {TX1_BSEL[*]}] + +set_property PACKAGE_PIN AK23 [get_ports {TX2_BSEL[0]}] +set_property PACKAGE_PIN AJ23 [get_ports {TX2_BSEL[1]}] +set_property PACKAGE_PIN AJ24 [get_ports {TX2_BSEL[2]}] +set_property PACKAGE_PIN AH23 [get_ports {TX2_BSEL[3]}] +set_property PACKAGE_PIN AH24 [get_ports {TX2_BSEL[4]}] +set_property PACKAGE_PIN AG22 [get_ports {TX2_BSEL[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {TX2_BSEL[*]}] + +## PPS, REFCLK ############################################################# +## +############################################################################ + +# RefClk, Bank 10 +set_property PACKAGE_PIN AF14 [get_ports {CLK_REF_RAW}] +set_property PACKAGE_PIN AH17 [get_ports {CLK_REF_SEL}] +set_property IOSTANDARD LVCMOS33 [get_ports {CLK_REF_*}] + +# PPS, Bank 10 +set_property PACKAGE_PIN AD15 [get_ports {CLK_SYNC_EXT}] +set_property PACKAGE_PIN AC14 [get_ports {CLK_SYNC_INT}] +set_property PACKAGE_PIN AA15 [get_ports {CLK_SYNC_INT_RAW}] +set_property IOSTANDARD LVCMOS33 [get_ports {CLK_SYNC_*}] + +## REF CLK PLL, Bank 10 +set_property PACKAGE_PIN AE15 [get_ports {CLK_PLL_SCLK}] +set_property PACKAGE_PIN AE16 [get_ports {CLK_PLL_SDATA}] +set_property PACKAGE_PIN AE18 [get_ports {CLK_PLL_SLE}] +set_property IOSTANDARD LVCMOS33 [get_ports {CLK_PLL_*}] +# +# Set pull-up on CLK_MUX_OUT to make the bitstream compatible with Rev A, where +# the signal doesn't exist. +set_property PACKAGE_PIN AH18 [get_ports {CLK_MUX_OUT}] +set_property IOSTANDARD LVCMOS33 [get_ports {CLK_MUX_OUT}] +set_property PULLUP TRUE [get_ports {CLK_MUX_OUT}] + + +############################################################################ +##FIXME: Remove this? + +## PS DDR +#set_property PACKAGE_PIN K25 [get_ports DDR_MODCLK_P] +#set_property PACKAGE_PIN J25 [get_ports DDR_MODCLK_N] +#set_property PACKAGE_PIN M22 [get_ports PS_DDR3_CKE] +#set_property PACKAGE_PIN F25 [get_ports PS_DDR3_RESET_N] +#set_property PACKAGE_PIN J24 [get_ports PS_DDR3_ADDR[14]] +#set_property PACKAGE_PIN H23 [get_ports PS_DDR3_ADDR[13]] +#set_property PACKAGE_PIN K23 [get_ports PS_DDR3_ADDR[12]] +#set_property PACKAGE_PIN H24 [get_ports PS_DDR3_ADDR[11]] +#set_property PACKAGE_PIN G26 [get_ports PS_DDR3_ADDR[10]] +#set_property PACKAGE_PIN J23 [get_ports PS_DDR3_ADDR[9]] +#set_property PACKAGE_PIN F27 [get_ports PS_DDR3_ADDR[8]] +#set_property PACKAGE_PIN K22 [get_ports PS_DDR3_ADDR[7]] +#set_property PACKAGE_PIN H26 [get_ports PS_DDR3_ADDR[6]] +#set_property PACKAGE_PIN G24 [get_ports PS_DDR3_ADDR[5]] +#set_property PACKAGE_PIN J26 [get_ports PS_DDR3_ADDR[4]] +#set_property PACKAGE_PIN G25 [get_ports PS_DDR3_ADDR[3]] +#set_property PACKAGE_PIN L27 [get_ports PS_DDR3_ADDR[2]] +#set_property PACKAGE_PIN K26 [get_ports PS_DDR3_ADDR[1]] +#set_property PACKAGE_PIN L25 [get_ports PS_DDR3_ADDR[0]] +#set_property PACKAGE_PIN K28 [get_ports PS_DDR3_DM[3]] +#set_property PACKAGE_PIN H29 [get_ports PS_DDR3_DM[2]] +#set_property PACKAGE_PIN B30 [get_ports PS_DDR3_DM[1]] +#set_property PACKAGE_PIN C27 [get_ports PS_DDR3_DM[0]] +#set_property PACKAGE_PIN M25 [get_ports PS_DDR3_BA[2]] +#set_property PACKAGE_PIN M26 [get_ports PS_DDR3_BA[1]] +#set_property PACKAGE_PIN M27 [get_ports PS_DDR3_BA[0]] +#set_property PACKAGE_PIN L28 [get_ports PS_DDR3_DQS_P[3]] +#set_property PACKAGE_PIN G29 [get_ports PS_DDR3_DQS_P[2]] +#set_property PACKAGE_PIN C29 [get_ports PS_DDR3_DQS_P[1]] +#set_property PACKAGE_PIN C26 [get_ports PS_DDR3_DQS_P[0]] +#set_property PACKAGE_PIN L29 [get_ports PS_DDR3_DQS_N[3]] +#set_property PACKAGE_PIN F29 [get_ports PS_DDR3_DQS_N[2]] +#set_property PACKAGE_PIN B29 [get_ports PS_DDR3_DQS_N[1]] +#set_property PACKAGE_PIN B26 [get_ports PS_DDR3_DQS_N[0]] +#set_property PACKAGE_PIN M30 [get_ports PS_DDR3_DQ[31]] +#set_property PACKAGE_PIN L30 [get_ports PS_DDR3_DQ[30]] +#set_property PACKAGE_PIN M29 [get_ports PS_DDR3_DQ[29]] +#set_property PACKAGE_PIN K30 [get_ports PS_DDR3_DQ[28]] +#set_property PACKAGE_PIN J28 [get_ports PS_DDR3_DQ[27]] +#set_property PACKAGE_PIN J30 [get_ports PS_DDR3_DQ[26]] +#set_property PACKAGE_PIN K27 [get_ports PS_DDR3_DQ[25]] +#set_property PACKAGE_PIN J29 [get_ports PS_DDR3_DQ[24]] +#set_property PACKAGE_PIN F30 [get_ports PS_DDR3_DQ[23]] +#set_property PACKAGE_PIN G30 [get_ports PS_DDR3_DQ[22]] +#set_property PACKAGE_PIN F28 [get_ports PS_DDR3_DQ[21]] +#set_property PACKAGE_PIN E30 [get_ports PS_DDR3_DQ[20]] +#set_property PACKAGE_PIN E28 [get_ports PS_DDR3_DQ[19]] +#set_property PACKAGE_PIN H28 [get_ports PS_DDR3_DQ[18]] +#set_property PACKAGE_PIN G27 [get_ports PS_DDR3_DQ[17]] +#set_property PACKAGE_PIN H27 [get_ports PS_DDR3_DQ[16]] +#set_property PACKAGE_PIN D29 [get_ports PS_DDR3_DQ[15]] +#set_property PACKAGE_PIN D28 [get_ports PS_DDR3_DQ[14]] +#set_property PACKAGE_PIN D30 [get_ports PS_DDR3_DQ[13]] +#set_property PACKAGE_PIN C28 [get_ports PS_DDR3_DQ[12]] +#set_property PACKAGE_PIN A28 [get_ports PS_DDR3_DQ[11]] +#set_property PACKAGE_PIN A30 [get_ports PS_DDR3_DQ[10]] +#set_property PACKAGE_PIN A27 [get_ports PS_DDR3_DQ[9]] +#set_property PACKAGE_PIN A29 [get_ports PS_DDR3_DQ[8]] +#set_property PACKAGE_PIN E27 [get_ports PS_DDR3_DQ[7]] +#set_property PACKAGE_PIN D26 [get_ports PS_DDR3_DQ[6]] +#set_property PACKAGE_PIN E26 [get_ports PS_DDR3_DQ[5]] +#set_property PACKAGE_PIN B25 [get_ports PS_DDR3_DQ[4]] +#set_property PACKAGE_PIN D25 [get_ports PS_DDR3_DQ[3]] +#set_property PACKAGE_PIN B27 [get_ports PS_DDR3_DQ[2]] +#set_property PACKAGE_PIN E25 [get_ports PS_DDR3_DQ[1]] +#set_property PACKAGE_PIN A25 [get_ports PS_DDR3_DQ[0]] +#set_property PACKAGE_PIN L23 [get_ports PS_DDR3_ODT] +#set_property PACKAGE_PIN N21 [get_ports PS_DDR3_VRN] +#set_property PACKAGE_PIN M21 [get_ports PS_DDR3_VRP] +#set_property PACKAGE_PIN N23 [get_ports PS_DDR3_WE_N] +#set_property PACKAGE_PIN N22 [get_ports PS_DDR3_CS_N] +#set_property PACKAGE_PIN M24 [get_ports PS_DDR3_CAS_N] +#set_property PACKAGE_PIN N24 [get_ports PS_DDR3_RAS_N] + diff --git a/fpga/usrp3/top/e320/mb_timing.xdc b/fpga/usrp3/top/e320/mb_timing.xdc new file mode 100644 index 000000000..3b77cad2d --- /dev/null +++ b/fpga/usrp3/top/e320/mb_timing.xdc @@ -0,0 +1,360 @@ +# +# Copyright 2018 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Description: Timing constraints for the USRP E320 +# + + +############################################################################### +# Input Clocks +############################################################################### + +# External Reference Clock +set REF_CLK_PERIOD 50.00 +create_clock -name ref_clk -period $REF_CLK_PERIOD [get_ports CLK_REF_RAW] + +# Radio clock from AD9361 +set rx_clk_period 8.138 +create_clock -name rx_clk -period $rx_clk_period [get_ports RX_CLK_P] + +# 1 Gigabit Ethernet Reference Clock +create_clock -name ge_clk -period 8.000 [get_ports CLK_MGT_125M_P] + +# 10 Gigabit and Aurora Reference Clock +create_clock -name xge_clk -period 6.400 [get_ports CLK_MGT_156_25M_P] + +# Derived radio clocks (two mutually-exclusive clocks using a BUFGMUX) +create_generated_clock -name radio_clk_1x \ + -divide_by 4 \ + -add \ + -master_clock rx_clk \ + -source [get_pins cat_io_lvds_dual_mode_i0/cat_io_lvds_i0/cat_input_lvds_i0/sdr_clk_2x_bufr/O] \ + [get_pins cat_io_lvds_dual_mode_i0/BUFGCTRL_radio_clk/O] +create_generated_clock -name radio_clk_2x \ + -divide_by 2 \ + -add \ + -master_clock rx_clk \ + -source [get_pins cat_io_lvds_dual_mode_i0/cat_io_lvds_i0/cat_input_lvds_i0/sdr_clk_bufr/O] \ + [get_pins cat_io_lvds_dual_mode_i0/BUFGCTRL_radio_clk/O] +set_clock_groups -physically_exclusive -group radio_clk_1x -group radio_clk_2x + + + +############################################################################### +# Rename Clocks +############################################################################### + +create_clock -name clk100 \ + -period [get_property PERIOD [get_clocks clk_fpga_0]] \ + [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_0]]] +set_input_jitter clk100 0.3 + +create_clock -name clk40 \ + -period [get_property PERIOD [get_clocks clk_fpga_1]] \ + [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_1]]] +set_input_jitter clk40 0.75 + +create_clock -name meas_clk_ref \ + -period [get_property PERIOD [get_clocks clk_fpga_2]] \ + [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_2]]] +set_input_jitter meas_clk_ref 0.18 + +create_clock -name bus_clk \ + -period [get_property PERIOD [get_clocks clk_fpga_3]] \ + [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_3]]] +set_input_jitter bus_clk 0.15 + +# DMA Clock +create_generated_clock -name ddr3_dma_clk \ + [get_pins {e320_clocking_i/mmcm_adv_inst/CLKOUT0}] + + + +############################################################################### +# Clock Crossings +############################################################################### + +set DDR3_UI_CLK_PERIOD [get_property period [get_clocks ddr3_ui_clk]] +set RADIO_CLK_1X_PERIOD [get_property period [get_clocks radio_clk_1x]] +set RADIO_CLK_2X_PERIOD [get_property period [get_clocks radio_clk_2x]] +set XGE_CLK_PERIOD [get_property period [get_clocks xge_clk]] + +# XADC temperature +set_max_delay -from [get_pins tempmon_i/device_temp_r_reg[*]/C] -to [get_clocks ddr3_ui_clk] $DDR3_UI_CLK_PERIOD -datapath_only + +# GPIO muxing +set_max_delay -from [get_pins e320_core_i/fp_gpio_src_reg_reg[*]/C] -to [get_clocks radio_clk_1x] $RADIO_CLK_1X_PERIOD -datapath_only +set_max_delay -from [get_pins e320_core_i/fp_gpio_src_reg_reg[*]/C] -to [get_clocks radio_clk_2x] $RADIO_CLK_2X_PERIOD -datapath_only + +# Codec reset +set_max_delay -from [get_pins e320_core_i/dboard_ctrl_reg[2]/C] -to [get_clocks radio_clk_1x_1] $RADIO_CLK_1X_PERIOD -datapath_only + +# Power-on reset +set_max_delay -from [get_pins por_gen/por_rst_reg/C] -to [get_clocks xge_clk] $XGE_CLK_PERIOD -datapath_only + +# SFP MDIO data and clock signal crossings. These are double synchronized in +# the Xilinx MDIO IP. +set_max_delay -from [get_pins sfp_wrapper_i/mgt_io_i/mdio_master_i/mdio_out_reg/C] \ + -to [get_clocks xge_clk] $XGE_CLK_PERIOD -datapath_only +set_max_delay -from [get_pins sfp_wrapper_i/mgt_io_i/mdio_master_i/mdc_reg/C] \ + -to [get_clocks xge_clk] $XGE_CLK_PERIOD -datapath_only + + + +############################################################################### +# False Paths +############################################################################### + +# Synchronizer core false paths +set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/D}] +set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/S}] + + +# MIG core reset +# According to Xilinx AR 61112, it is safe to make sys_rst a false path. +set_false_path -from [get_pins bus_reset_gen/reset_out_reg/C] \ + -to [get_clocks ddr3_ui_clk] +set_false_path -from [get_pins bus_reset_gen/reset_out_reg/C] \ + -to [get_clocks ddr3_ui_clk_2x] + +# USR_ACCESS build date +set_false_path -through [get_pins usr_access_i/DATA[*]] + + + +############################################################################### +# PPS Input Timing +############################################################################### + +# The external PPS is synchronous to the external reference clock. We want to +# allow for 5 ns of setup and 5 ns of hold at the external connectors of the +# device. +set t_ext_setup 5.0 +set t_ext_hold 5.0 + +# Board delays for external REF/PPS +set t_ext_pps_to_fpga(min) 1.673 ; # Delay from external pin of PPS to FPGA +set t_ext_pps_to_fpga(max) 5.011 +set t_ext_ref_to_fpga(min) 1.452 ; # Delay from external pin of reference clock to FPGA +set t_ext_ref_to_fpga(max) 4.000 + +# Calculate the needed setup and hold at FPGA for external PPS, taking into +# account worst-case clock and data path skew. +set t_ext_fpga_setup [expr $t_ext_setup + ($t_ext_ref_to_fpga(min) - $t_ext_pps_to_fpga(max))] +set t_ext_fpga_hold [expr $t_ext_hold + ($t_ext_pps_to_fpga(min) - $t_ext_ref_to_fpga(max))] + +set_input_delay -clock ref_clk -max [expr $REF_CLK_PERIOD - $t_ext_fpga_setup] [get_ports CLK_SYNC_EXT] +set_input_delay -clock ref_clk -min $t_ext_fpga_hold [get_ports CLK_SYNC_EXT] + + +# The GPS provides 2 ns setup and 2 ns of hold around the rising clock edge +set t_int_setup 2.0 +set t_int_hold 2.0 + +# Board delays for internal REF/PPS +set t_int_pps_to_fpga(min) 0.359 ; # Delay from PPS output of GPS to FPGA +set t_int_pps_to_fpga(max) 0.438 +set t_int_ref_to_fpga(min) 1.699 ; # Delay from reference clock output of GPS to FPGA +set t_int_ref_to_fpga(max) 3.149 + +# Calculate the needed setup and hold at FPGA for internal PPS, taking into +# account worst-case clock and data path skew. +set t_int_fpga_setup [expr $t_int_setup + ($t_int_ref_to_fpga(min) - $t_int_pps_to_fpga(max))] +set t_int_fpga_hold [expr $t_int_hold + ($t_int_pps_to_fpga(min) - $t_int_ref_to_fpga(max))] + +set_input_delay -clock ref_clk -max [expr $REF_CLK_PERIOD - $t_int_fpga_setup] [get_ports CLK_SYNC_INT] +set_input_delay -clock ref_clk -min $t_int_fpga_hold [get_ports CLK_SYNC_INT] + + + +############################################################################### +# LVDS Interface +############################################################################### + +# LVDS interface is source synchronous DDR. tPCB numbers are taken from +# HyperLynx for the Rev B PCB. 10 ps was added to each PCB delay for additional +# margin. + +# From the AD9361 data sheet +set tDDRX(min) 0.25 +set tDDRX(max) 1.25 +set tSTX(min) 1.0 +set tHTX(min) 0.0 + +# Other timing parameters +set tCP2X(min) [expr 0.45 * $rx_clk_period] ; # Worst-case bit period +set tTrns(max) 0.220 ; # Amount of time it takes an input to transition + +# Input timing parameters +set tPCB_RX(max) 0.058 ; # Max delay by which the clock trace is longer than the data trace +set tPCB_RX(min) -0.059 ; # Min delay by which the clock trace is longer than the data trace +set tSetupIn [expr $tCP2X(min) - $tDDRX(max) + $tPCB_RX(min)] +set tHoldIn [expr $tDDRX(min) - $tTrns(max) - $tPCB_RX(max)] + +# Input Setup/Hold (Rising Clock Edge) +set_input_delay -clock [get_clocks rx_clk] -max [expr $tCP2X(min) - $tSetupIn] [get_ports {RX_DATA_*[*] RX_FRAME_*}] +set_input_delay -clock [get_clocks rx_clk] -min $tHoldIn [get_ports {RX_DATA_*[*] RX_FRAME_*}] + +# Input Setup/Hold (Falling Clock Edge) +set_input_delay -clock [get_clocks rx_clk] -max [expr $tCP2X(min) - $tSetupIn] [get_ports {RX_DATA_*[*] RX_FRAME_*}] -clock_fall -add_delay +set_input_delay -clock [get_clocks rx_clk] -min $tHoldIn [get_ports {RX_DATA_*[*] RX_FRAME_*}] -clock_fall -add_delay + + +# Output timing parameters +set tPCB_TX(max) 0.066 ; # Max delay by which the clock trace is longer than the data trace +set tPCB_TX(min) -0.049 ; # Min delay by which the clock trace is longer than the data trace +set tSetupOut [expr $tSTX(min) - $tPCB_TX(min)] +set tHoldOut [expr $tHTX(min) + $tPCB_TX(max)] + +# Create tx_clk (FB_CLK) +create_generated_clock \ + -name tx_clk \ + -multiply_by 1 \ + -source [get_pins cat_io_lvds_dual_mode_i0/cat_io_lvds_i0/cat_output_lvds_i0/ddr_clk_oserdese2/CLK] \ + [get_ports TX_CLK_P] + +# Output Setup +set_output_delay -clock [get_clocks tx_clk] -max $tSetupOut [get_ports {TX_DATA_*[*] TX_FRAME_*}] +set_output_delay -clock [get_clocks tx_clk] -max $tSetupOut [get_ports {TX_DATA_*[*] TX_FRAME_*}] -clock_fall -add_delay + +# Output Hold +set_output_delay -clock [get_clocks tx_clk] -min [expr -$tHoldOut] [get_ports {TX_DATA_*[*] TX_FRAME_*}] +set_output_delay -clock [get_clocks tx_clk] -min [expr -$tHoldOut] [get_ports {TX_DATA_*[*] TX_FRAME_*}] -clock_fall -add_delay + + + +############################################################################### +# SPI +############################################################################### + +# Xilinx doesn't allow you to fully constrain EMIO because the internal SPI +# clock is not accessible. So delay constraints are used to limit the delays to +# compatible values. + +# Transceiver SPI +set_max_delay -from [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI0MO] \ + -to [get_ports XCVR_SPI_MOSI] 6.0 -datapath_only +set_min_delay -to [get_ports XCVR_SPI_MOSI] 0.0 +# +set_max_delay -from [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI0SCLKO] \ + -to [get_ports XCVR_SPI_CLK] 6.0 -datapath_only +set_min_delay -to [get_ports XCVR_SPI_CLK] 0.0 +# +set_max_delay -from [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI0SSON[0]] \ + -to [get_ports XCVR_SPI_CS_N] 6.0 -datapath_only +set_min_delay -to [get_ports XCVR_SPI_CS_N] 0.0 +# +set_max_delay -from [get_ports XCVR_SPI_MISO] \ + -to [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI0MI] 4.0 -datapath_only +set_min_delay -from [get_ports XCVR_SPI_MISO] -to [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI0MI] 0.0 + +# Clock synthesizer SPI +set_max_delay -from [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI1MO] \ + -to [get_ports CLK_PLL_SDATA] 9.0 -datapath_only +set_min_delay -to [get_ports XCVR_SPI_MOSI] 0.0 +# +set_max_delay -from [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI1SCLKO] \ + -to [get_ports CLK_PLL_SCLK] 9.0 -datapath_only +set_min_delay -to [get_ports XCVR_SPI_CLK] 0.0 +# +set_max_delay -from [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI1SSON[0]] \ + -to [get_ports CLK_PLL_SLE] 9.0 -datapath_only +set_min_delay -to [get_ports XCVR_SPI_CS_N] 0.0 + + + +############################################################################### +# Miscellaneous I/O Constraints +############################################################################### + +# Transceiver +set_max_delay -to [get_ports XCVR_RESET_N] 50.0 +set_min_delay -to [get_ports XCVR_RESET_N] 0.0 +# +set_max_delay -from [get_ports XCVR_CTRL_OUT[*]] 5.0 -datapath_only +set_min_delay -from [get_ports XCVR_CTRL_OUT[*]] 0.0 + +# GPIO +set_max_delay -from [get_ports GPIO_PREBUFF[*]] 5.0 -datapath_only +set_min_delay -from [get_ports GPIO_PREBUFF[*]] 0.0 +# +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports GPIO_DIR[*]]] \ + -to [get_ports GPIO_DIR[*]] 8.0 -datapath_only +set_min_delay -to [get_ports GPIO_DIR[*]] 0.0 +# +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports GPIO_PREBUFF[*]]] \ + -to [get_ports GPIO_PREBUFF[*]] 8.0 -datapath_only +set_min_delay -to [get_ports GPIO_PREBUFF[*]] 0.0 +# +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports GPIO_OE_N]] \ + -to [get_ports GPIO_OE_N] 8.0 -datapath_only +set_min_delay -to [get_ports GPIO_OE_N] 0.0 +# +set_max_delay -to [get_ports {EN_GPIO_2V5 EN_GPIO_3V3 EN_GPIO_VAR_SUPPLY}] 50.0 +set_min_delay -to [get_ports {EN_GPIO_2V5 EN_GPIO_3V3 EN_GPIO_VAR_SUPPLY}] 0.0 + +# GPS +set_max_delay -from [get_ports {GPS_ALARM GPS_LOCK GPS_PHASELOCK GPS_SURVEY GPS_WARMUP}] 10.0 -datapath_only +set_min_delay -from [get_ports {GPS_ALARM GPS_LOCK GPS_PHASELOCK GPS_SURVEY GPS_WARMUP}] 0.0 +# +set_max_delay -to [get_ports GPS_INITSURV_N] 50.0 +set_min_delay -to [get_ports GPS_INITSURV_N] 0.0 +set_max_delay -to [get_ports GPS_RST_N] 50.0 +set_min_delay -to [get_ports GPS_RST_N] 0.0 +# +set_max_delay -to [get_ports CLK_GPS_PWR_EN] 50.0 +set_min_delay -to [get_ports CLK_GPS_PWR_EN] 0.0 + +# Clock Control +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports CLK_REF_SEL]] \ + -to [get_ports CLK_REF_SEL] 8.0 -datapath_only +set_min_delay -to [get_ports CLK_REF_SEL] 0.0 +# +set_max_delay -from [get_ports CLK_MUX_OUT] 5.0 -datapath_only +set_min_delay -from [get_ports CLK_MUX_OUT] 0.0 + +# DDR3 +set_max_delay -to [get_ports ddr3_reset_n] 50.0 +set_min_delay -to [get_ports ddr3_reset_n] 0.0 + +# LEDs +set_max_delay -to [get_ports RX1_GRN_ENA] 50.0 +set_min_delay -to [get_ports RX1_GRN_ENA] 0.0 +set_max_delay -to [get_ports TX1_RED_ENA] 50.0 +set_min_delay -to [get_ports TX1_RED_ENA] 0.0 +set_max_delay -to [get_ports TXRX1_GRN_ENA] 50.0 +set_min_delay -to [get_ports TXRX1_GRN_ENA] 0.0 +set_max_delay -to [get_ports RX2_GRN_ENA] 50.0 +set_min_delay -to [get_ports RX2_GRN_ENA] 0.0 +set_max_delay -to [get_ports TX2_RED_ENA] 50.0 +set_min_delay -to [get_ports TX2_RED_ENA] 0.0 +set_max_delay -to [get_ports TXRX2_GRN_ENA] 50.0 +set_min_delay -to [get_ports TXRX2_GRN_ENA] 0.0 +# +set_max_delay -to [get_ports LED_ACT1] 50.0 +set_min_delay -to [get_ports LED_ACT1] 0.0 +set_max_delay -to [get_ports LED_LINK1] 50.0 +set_min_delay -to [get_ports LED_LINK1] 0.0 + +# Control Filters +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports FE*_SEL[*]]] \ + -to [get_ports FE*_SEL[*]] 10.0 -datapath_only +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports RX*_SEL[*]]] \ + -to [get_ports RX*_SEL[*]] 10.0 -datapath_only +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports RX*_BSEL[*]]] \ + -to [get_ports RX*_BSEL[*]] 10.0 -datapath_only +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports TX*_BSEL[*]]] \ + -to [get_ports TX*_BSEL[*]] 10.0 -datapath_only + +# PA Control +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports TX_HFAMP*_ENA]] \ + -to [get_ports TX_HFAMP*_ENA] 10.0 -datapath_only +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports TX_LFAMP*_ENA]] \ + -to [get_ports TX_LFAMP*_ENA] 10.0 -datapath_only + +# SFP +set_max_delay -from [get_ports SFP1_RXLOS] 50.0 +set_min_delay -from [get_ports SFP1_RXLOS] 0.0 +set_max_delay -to [get_ports SFP1_TXDISABLE] 50.0 +set_min_delay -to [get_ports SFP1_TXDISABLE] 0.0 diff --git a/fpga/usrp3/top/e320/n3xx_mgt_io_core.v b/fpga/usrp3/top/e320/n3xx_mgt_io_core.v new file mode 100644 index 000000000..aa702775e --- /dev/null +++ b/fpga/usrp3/top/e320/n3xx_mgt_io_core.v @@ -0,0 +1,654 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0 +// +// Module: e320_mgt_io_core +// Description: +// Encapsulates the PSC/PMA, the MAC layer and the control interface +// for 1GbE, 10GbE and Aurora +// +////////////////////////////////////////////////////////////////////// + +module n3xx_mgt_io_core #( + parameter PROTOCOL = "10GbE", // Must be {10GbE, 1GbE, Aurora, Disabled} + parameter [13:0] REG_BASE = 14'h0, + parameter REG_DWIDTH = 32, + parameter REG_AWIDTH = 14, + parameter [7:0] PORTNUM = 8'd0, + parameter MDIO_EN = 0, + parameter [4:0] MDIO_PHYADDR = 5'd0 +)( + // Resets + input areset, + input bus_rst, + // Clocks + input gt_refclk, + input gb_refclk, + input misc_clk, + input bus_clk, + // SFP high-speed IO + output txp, + output txn, + input rxp, + input rxn, + // SFP low-speed IO + input sfpp_rxlos, + input sfpp_tx_fault, + output sfpp_tx_disable, + // Data port: Ethernet TX + input [63:0] s_axis_tdata, + input [3:0] s_axis_tuser, + input s_axis_tlast, + input s_axis_tvalid, + output s_axis_tready, + // Data port: Ethernet RX + output [63:0] m_axis_tdata, + output [3:0] m_axis_tuser, + output m_axis_tlast, + output m_axis_tvalid, + input m_axis_tready, + // Register port + input reg_wr_req, + input [REG_AWIDTH-1:0] reg_wr_addr, + input [REG_DWIDTH-1:0] reg_wr_data, + input reg_rd_req, + input [REG_AWIDTH-1:0] reg_rd_addr, + output reg_rd_resp, + output [REG_DWIDTH-1:0] reg_rd_data, + // Misc + output [31:0] port_info, + output link_up, + output reg activity +); + + //----------------------------------------------------------------- + // Registers + //----------------------------------------------------------------- + localparam [7:0] COMPAT_NUM = 8'd2; + + // Common registers + localparam REG_PORT_INFO = REG_BASE + 'h0; + localparam REG_MAC_CTRL_STATUS = REG_BASE + 'h4; + localparam REG_PHY_CTRL_STATUS = REG_BASE + 'h8; + localparam REG_MAC_LED_CTL = REG_BASE + 'hC; + + // Ethernet specific + localparam REG_ETH_MDIO_BASE = REG_BASE + 'h10; + // Aurora specific + localparam REG_AURORA_OVERRUNS = REG_BASE + 'h20; + localparam REG_CHECKSUM_ERRORS = REG_BASE + 'h24; + localparam REG_BIST_CHECKER_SAMPS = REG_BASE + 'h28; + localparam REG_BIST_CHECKER_ERRORS = REG_BASE + 'h2C; + + wire reg_rd_resp_mdio; + reg reg_rd_resp_glob = 1'b0; + wire [REG_DWIDTH-1:0] reg_rd_data_mdio; + reg [REG_DWIDTH-1:0] reg_rd_data_glob = 32'h0; + + // Protocol specific constants + wire [7:0] mgt_protocol; + wire [31:0] mac_ctrl_rst_val, phy_ctrl_rst_val; + wire [1:0] mac_led_ctl_rst_val = 2'h0; + + // Flush logic: If the link is not up, we will flush all packets coming from + // the device. This avoids the MAC backpressuring when the PHY is down. + // The device will always send discovery packets to the transports during + // initialization, and they have no way of knowing if it's safe to travel + // down this route. c2mac == "CHDR to MAC" + wire [63:0] c2mac_tdata; + wire [3:0] c2mac_tuser; + wire c2mac_tlast; + wire c2mac_tvalid; + wire c2mac_tready; + + axis_packet_flush #( + .WIDTH(64+3), // tdata + tuser + .TIMEOUT_W(1), // Not using timeout + .FLUSH_PARTIAL_PKTS(0), + .PIPELINE("NONE") + ) linkup_flush ( + .clk(bus_clk), + .reset(bus_rst), + .enable(~link_up), // enable flushing when link down + .timeout(1'b0), + .flushing(/* not required */), + .done(/* not required */), + // Input from device/crossbar + .s_axis_tdata ({s_axis_tuser, s_axis_tdata}), + .s_axis_tlast (s_axis_tlast), + .s_axis_tvalid (s_axis_tvalid), + .s_axis_tready (s_axis_tready), + // Output to MAC + .m_axis_tdata ({c2mac_tuser, c2mac_tdata}), + .m_axis_tlast (c2mac_tlast), + .m_axis_tvalid (c2mac_tvalid), + .m_axis_tready (c2mac_tready) + ); + + generate + if (PROTOCOL == "Aurora") begin + assign mgt_protocol = 8'd3; + assign mac_ctrl_rst_val = 32'h0; + assign phy_ctrl_rst_val = 32'h0; + end else if (PROTOCOL == "10GbE") begin + assign mgt_protocol = 8'd2; + assign mac_ctrl_rst_val = {31'h0, 1'b1}; // tx_enable on reset + assign phy_ctrl_rst_val = 32'h0; + end else if (PROTOCOL == "1GbE") begin + assign mgt_protocol = 8'd1; + assign mac_ctrl_rst_val = {31'h0, 1'b1}; // tx_enable on reset + assign phy_ctrl_rst_val = 32'h0; + end else begin + assign mgt_protocol = 8'd0; + assign mac_ctrl_rst_val = 32'h0; + assign phy_ctrl_rst_val = 32'h0; + end + endgenerate + + // Writable registers + reg [31:0] mac_ctrl_reg = 32'h0; + reg [31:0] phy_ctrl_reg = 32'h0; + reg [1:0] mac_led_ctl = 2'h0; + + always @(posedge bus_clk) begin + if (bus_rst) begin + mac_ctrl_reg <= mac_ctrl_rst_val; + phy_ctrl_reg <= phy_ctrl_rst_val; + mac_led_ctl <= mac_led_ctl_rst_val; + end else if (reg_wr_req) begin + case(reg_wr_addr) + REG_MAC_CTRL_STATUS: + mac_ctrl_reg <= reg_wr_data; + REG_PHY_CTRL_STATUS: + phy_ctrl_reg <= reg_wr_data; + REG_MAC_LED_CTL: + mac_led_ctl <= reg_wr_data[1:0]; + endcase + end + end + + // Readable registers + wire [31:0] overruns; + wire [31:0] checksum_errors; + wire [47:0] bist_checker_samps; + wire [47:0] bist_checker_errors; + wire [31:0] mac_status, phy_status; + wire [31:0] mac_status_bclk, phy_status_bclk; + + assign port_info = {COMPAT_NUM, 6'h0, activity, link_up, mgt_protocol, PORTNUM}; + + always @(posedge bus_clk) begin + // No reset handling needed for readback + if (reg_rd_req) begin + reg_rd_resp_glob <= 1'b1; + case(reg_rd_addr) + REG_PORT_INFO: + reg_rd_data_glob <= port_info; + REG_MAC_CTRL_STATUS: + reg_rd_data_glob <= mac_status_bclk; + REG_PHY_CTRL_STATUS: + reg_rd_data_glob <= phy_status_bclk; + REG_MAC_LED_CTL: + reg_rd_data_glob <= {30'd0, mac_led_ctl}; + REG_AURORA_OVERRUNS: + reg_rd_data_glob <= overruns; + REG_CHECKSUM_ERRORS: + reg_rd_data_glob <= checksum_errors; + REG_BIST_CHECKER_SAMPS: + reg_rd_data_glob <= bist_checker_samps[47:16]; //Scale num samples by 2^16 + REG_BIST_CHECKER_ERRORS: + reg_rd_data_glob <= bist_checker_errors[31:0]; //Don't scale errors + default: + reg_rd_resp_glob <= 1'b0; + endcase + end if (reg_rd_resp_glob) begin + reg_rd_resp_glob <= 1'b0; + end + end + + synchronizer #( .STAGES(2), .WIDTH(32), .INITIAL_VAL(32'h0) ) mac_status_sync_i ( + .clk(bus_clk), .rst(1'b0), .in(mac_status), .out(mac_status_bclk) + ); + + synchronizer #( .STAGES(2), .WIDTH(32), .INITIAL_VAL(32'h0) ) phy_status_sync_i ( + .clk(bus_clk), .rst(1'b0), .in(phy_status), .out(phy_status_bclk) + ); + + // Regport Mux for response + regport_resp_mux #( + .WIDTH (REG_DWIDTH), + .NUM_SLAVES (2) + ) reg_resp_mux_i ( + .clk(bus_clk), .reset(bus_rst), + .sla_rd_resp({reg_rd_resp_mdio, reg_rd_resp_glob}), + .sla_rd_data({reg_rd_data_mdio, reg_rd_data_glob}), + .mst_rd_resp(reg_rd_resp), .mst_rd_data(reg_rd_data) + ); + + //----------------------------------------------------------------- + // Ethernet Specific: MDIO + //----------------------------------------------------------------- + + wire mdc, mdio_m2s, mdio_s2m, mdio_s2m_sync; + generate + if ((PROTOCOL == "10GbE" || PROTOCOL == "1GbE") && (MDIO_EN == 1)) begin + mdio_master #( + .REG_BASE (REG_ETH_MDIO_BASE), + .REG_AWIDTH (REG_AWIDTH), + .MDC_DIVIDER (8'd200) + ) mdio_master_i ( + .clk (bus_clk), + .rst (bus_rst), + .mdc (mdc), + .mdio_in (mdio_s2m_sync), + .mdio_out (mdio_m2s), + .mdio_tri (), + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_data (reg_rd_data_mdio), + .reg_rd_resp (reg_rd_resp_mdio) + ); + + // We can cross mdio_s2m into the bus_clk domain. A synchronizer is safe + // here because the bit is inherently async + synchronizer #(.INITIAL_VAL(1'b0)) mdio_s2m_sync_i ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(mdio_s2m), .out(mdio_s2m_sync) + ); + end else begin + assign mdc = 1'b0; + assign mdio_m2s = 1'b0; + assign reg_rd_resp_mdio = 1'b0; + assign reg_rd_data_mdio = 32'h0; + end + endgenerate + + generate + if (PROTOCOL == "10GbE") begin + //----------------------------------------------------------------- + // 10 Gigabit Ethernet + //----------------------------------------------------------------- + wire [63:0] xgmii_txd; + wire [7:0] xgmii_txc; + wire [63:0] xgmii_rxd; + wire [7:0] xgmii_rxc; + wire xge_phy_resetdone; + + ten_gige_phy ten_gige_phy_i + ( + // Clocks and Reset + .areset(areset | phy_ctrl_reg[0]), // Asynchronous reset for entire core. + .refclk(gt_refclk), // Transciever reference clock: 156.25MHz + .clk156(gb_refclk), // Globally buffered core clock: 156.25MHz + .dclk(misc_clk), // Management/DRP clock: 78.125MHz + .sim_speedup_control(1'b0), + // GMII Interface (client MAC <=> PCS) + .xgmii_txd(xgmii_txd), // Transmit data from client MAC. + .xgmii_txc(xgmii_txc), // Transmit control signal from client MAC. + .xgmii_rxd(xgmii_rxd), // Received Data to client MAC. + .xgmii_rxc(xgmii_rxc), // Received control signal to client MAC. + // Tranceiver Interface + .txp(txp), // Differential +ve of serial transmission from PMA to PMD. + .txn(txn), // Differential -ve of serial transmission from PMA to PMD. + .rxp(rxp), // Differential +ve for serial reception from PMD to PMA. + .rxn(rxn), // Differential -ve for serial reception from PMD to PMA. + // Management: MDIO Interface + .mdc(mdc), // Management Data Clock + .mdio_in(mdio_m2s), // Management Data In + .mdio_out(mdio_s2m), // Management Data Out + .mdio_tri(), // Management Data Tristate + .prtad(MDIO_PHYADDR), // MDIO address + // General IO's + .core_status(phy_status[7:0]), // Core status + .resetdone(xge_phy_resetdone), + .signal_detect(~sfpp_rxlos), // Input from PMD to indicate presence of optical input. (Undocumented, but it seems Xilinx expect this to be inverted.) + .tx_fault(sfpp_tx_fault), + .tx_disable(sfpp_tx_disable) + ); + + xge_mac_wrapper #( + .PORTNUM(PORTNUM), + .WISHBONE(0) + ) xge_mac_wrapper_i ( + // XGMII + .xgmii_clk(gb_refclk), + .xgmii_txd(xgmii_txd), + .xgmii_txc(xgmii_txc), + .xgmii_rxd(xgmii_rxd), + .xgmii_rxc(xgmii_rxc), + // Client FIFO Interfaces + .sys_clk(bus_clk), + .sys_rst(bus_rst), + .rx_tdata(m_axis_tdata), + .rx_tuser(m_axis_tuser), + .rx_tlast(m_axis_tlast), + .rx_tvalid(m_axis_tvalid), + .rx_tready(m_axis_tready), + .tx_tdata(c2mac_tdata), + .tx_tuser(c2mac_tuser), // Bit[3] (error) is ignored for now. + .tx_tlast(c2mac_tlast), + .tx_tvalid(c2mac_tvalid), + .tx_tready(c2mac_tready), + // Other + .phy_ready(xge_phy_resetdone), + .ctrl_tx_enable(mac_ctrl_reg[0]), + .status_crc_error(mac_status[0]), + .status_fragment_error(mac_status[1]), + .status_txdfifo_ovflow(mac_status[2]), + .status_txdfifo_udflow(mac_status[3]), + .status_rxdfifo_ovflow(mac_status[4]), + .status_rxdfifo_udflow(mac_status[5]), + .status_pause_frame_rx(mac_status[6]), + .status_local_fault(mac_status[7]), + .status_remote_fault(mac_status[8]), + .wb_ack_o(), + .wb_dat_o(), + .wb_adr_i(1'b0), + .wb_clk_i(1'b0), + .wb_cyc_i(1'b0), + .wb_dat_i(1'b0), + .wb_rst_i(1'b0), + .wb_stb_i(1'b0), + .wb_we_i (1'b0), + .wb_int_o() + ); + + assign phy_status[31:8] = 24'h0; + assign mac_status[31:9] = 23'h0; + assign link_up = phy_status_bclk[0]; + + end else if (PROTOCOL == "1GbE") begin + + //----------------------------------------------------------------- + // 1 Gigabit Ethernet + //----------------------------------------------------------------- + wire [7:0] gmii_txd, gmii_rxd; + wire gmii_tx_en, gmii_tx_er, gmii_rx_dv, gmii_rx_er; + wire gmii_clk; + wire gt0_qplloutclk, gt0_qplloutrefclk; //unused in 7-series Zynq + + assign gt0_qplloutclk = 1'b0; + assign gt0_qplloutrefclk = 1'b0; + assign sfpp_tx_disable = 1'b0; // Always on. + + one_gige_phy one_gige_phy_i + ( + .reset(areset | phy_ctrl_reg[0]), // Asynchronous reset for entire core. + .independent_clock(bus_clk), + // Tranceiver Interface + .gtrefclk(gt_refclk), // Reference clock for MGT: 125MHz, very high quality. + .gtrefclk_bufg(gb_refclk), // Reference clock routed through a BUFG + .txp(txp), // Differential +ve of serial transmission from PMA to PMD. + .txn(txn), // Differential -ve of serial transmission from PMA to PMD. + .rxp(rxp), // Differential +ve for serial reception from PMD to PMA. + .rxn(rxn), // Differential -ve for serial reception from PMD to PMA. + // GMII Interface (client MAC <=> PCS) + .gmii_clk(gmii_clk), // Clock to client MAC. + .gmii_txd(gmii_txd), // Transmit data from client MAC. + .gmii_tx_en(gmii_tx_en), // Transmit control signal from client MAC. + .gmii_tx_er(gmii_tx_er), // Transmit control signal from client MAC. + .gmii_rxd(gmii_rxd), // Received Data to client MAC. + .gmii_rx_dv(gmii_rx_dv), // Received control signal to client MAC. + .gmii_rx_er(gmii_rx_er), // Received control signal to client MAC. + // Management: MDIO Interface + .mdc(mdc), // Management Data Clock + .mdio_i(mdio_m2s), // Management Data In + .mdio_o(mdio_s2m), // Management Data Out + .mdio_t(), // Management Data Tristate + .phyaddr(MDIO_PHYADDR), // MDIO address + .configuration_vector(5'd0), // Alternative to MDIO interface. + .configuration_valid(1'b1), // Validation signal for Config vector (MUST be 1 for proper functionality...undocumented) + // General IO's + .status_vector(phy_status[15:0]), // Core status. + .signal_detect(1'b1 /*Optical module not supported*/) // Input from PMD to indicate presence of optical input. + ); + + simple_gemac_wrapper #(.RX_FLOW_CTRL(0), .PORTNUM(PORTNUM)) simple_gemac_wrapper_i + ( + .clk125(gmii_clk), + .reset(areset), + + .GMII_GTX_CLK(), + .GMII_TX_EN(gmii_tx_en), + .GMII_TX_ER(gmii_tx_er), + .GMII_TXD(gmii_txd), + .GMII_RX_CLK(gmii_clk), + .GMII_RX_DV(gmii_rx_dv), + .GMII_RX_ER(gmii_rx_er), + .GMII_RXD(gmii_rxd), + + .sys_clk(bus_clk), + .rx_tdata(m_axis_tdata), + .rx_tuser(m_axis_tuser), + .rx_tlast(m_axis_tlast), + .rx_tvalid(m_axis_tvalid), + .rx_tready(m_axis_tready), + .tx_tdata(c2mac_tdata), + .tx_tuser(c2mac_tuser), + .tx_tlast(c2mac_tlast), + .tx_tvalid(c2mac_tvalid), + .tx_tready(c2mac_tready), + + .wb_clk_i(1'b0), + .wb_rst_i(1'b0), + .wb_adr_i(8'h0), + .wb_dat_i(32'h0), + .wb_we_i(1'b0), + .wb_stb_i(1'b0), + .wb_cyc_i(1'b0), + .wb_dat_o(), + .wb_ack_o(), + .wb_int_o(), + .mdc(), + .mdio_out(1'b0), + .mdio_tri(), + .mdio_in(), + .debug_tx(), + .debug_rx() + ); + + assign phy_status[31:16] = 16'h0; + assign mac_status[31:0] = 32'h0; + assign link_up = phy_status_bclk[0]; + + assign gt_tx_out_clk_unbuf = 1'b0; + + end else if (PROTOCOL == "Aurora") begin + + //----------------------------------------------------------------- + // Aurora + //----------------------------------------------------------------- + wire user_clk, user_rst; + wire [63:0] m2p_tdata, p2m_tdata; + wire m2p_tvalid, m2p_tready, p2m_tvalid; + wire channel_up, hard_err, soft_err, mac_crit_err; + + wire bist_checker_en = mac_ctrl_reg[0]; + wire bist_gen_en = mac_ctrl_reg[1]; + wire bist_loopback_en = mac_ctrl_reg[2]; + wire [5:0] bist_gen_rate = mac_ctrl_reg[8:3]; + wire phy_areset = mac_ctrl_reg[9]; + wire mac_clear = mac_ctrl_reg[10]; + wire bist_checker_locked; + + assign sfpp_tx_disable = 1'b0; // Always on. + + aurora_phy_x1 aurora_phy_i ( + // Resets + .areset(areset | phy_areset), + // Clocks + .refclk(gt_refclk), + .init_clk(misc_clk), + .user_clk(user_clk), + .user_rst(user_rst), + // GTX Serial I/O + .tx_p(txp), + .tx_n(txn), + .rx_p(rxp), + .rx_n(rxn), + // AXI4-Stream TX Interface + .s_axis_tdata(m2p_tdata), + .s_axis_tvalid(m2p_tvalid), + .s_axis_tready(m2p_tready), + // AXI4-Stream RX Interface + .m_axis_tdata(p2m_tdata), + .m_axis_tvalid(p2m_tvalid), + // AXI4-Lite Config Interface (unused) + .s_axi_awaddr(32'h0), + .s_axi_araddr(32'h0), + .s_axi_awvalid(1'b0), + .s_axi_awready(), + .s_axi_wdata(32'h0), + .s_axi_wvalid(1'b0), + .s_axi_wstrb(1'b0), + .s_axi_wready(), + .s_axi_bvalid(), + .s_axi_bresp(), + .s_axi_bready(1'b1), + .s_axi_arready(), + .s_axi_arvalid(1'b0), + .s_axi_rdata(), + .s_axi_rvalid(), + .s_axi_rresp(), + .s_axi_rready(1'b1), + // Status and Error Reporting Interface + .channel_up(channel_up), + .hard_err(hard_err), + .soft_err(soft_err) + ); + + aurora_axis_mac #( + .PHY_ENDIANNESS ("LITTLE"), + .PACKET_MODE (1), + .MAX_PACKET_SIZE(1024), + .BIST_ENABLED (1) + ) aurora_mac_i ( + // Clocks and resets + .phy_clk(user_clk), .phy_rst(user_rst), + .sys_clk(bus_clk), .sys_rst(bus_rst), + .clear(mac_clear), + // PHY Interface (Synchronous to phy_clk) + .phy_s_axis_tdata(p2m_tdata), + .phy_s_axis_tvalid(p2m_tvalid), + .phy_m_axis_tdata(m2p_tdata), + .phy_m_axis_tvalid(m2p_tvalid), + .phy_m_axis_tready(m2p_tready), + // User Interface (Synchronous to sys_clk) + .s_axis_tdata(c2mac_tdata), + .s_axis_tlast(c2mac_tlast), + .s_axis_tvalid(c2mac_tvalid), + .s_axis_tready(c2mac_tready), + .m_axis_tdata(m_axis_tdata), + .m_axis_tlast(m_axis_tlast), + .m_axis_tvalid(m_axis_tvalid), + .m_axis_tready(m_axis_tready), + // PHY Status Inputs (Synchronous to phy_clk) + .channel_up(channel_up), + .hard_err(hard_err), + .soft_err(soft_err), + // Status and Error Outputs (Synchronous to sys_clk) + .overruns(overruns), + .soft_errors(), + .checksum_errors(checksum_errors), + .critical_err(mac_crit_err), + // BIST Interface (Synchronous to sys_clk) + .bist_gen_en(bist_gen_en), + .bist_gen_rate(bist_gen_rate), + .bist_checker_en(bist_checker_en), + .bist_loopback_en(bist_loopback_en), + .bist_checker_locked(bist_checker_locked), + .bist_checker_samps(bist_checker_samps), + .bist_checker_errors(bist_checker_errors) + ); + + assign m_axis_tuser = 4'd0; + + wire channel_up_bclk, hard_err_bclk, soft_err_bclk, mac_crit_err_bclk; + synchronizer #(.INITIAL_VAL(1'b0)) channel_up_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(channel_up), .out(channel_up_bclk)); + synchronizer #(.INITIAL_VAL(1'b0)) hard_err_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(hard_err), .out(hard_err_bclk)); + synchronizer #(.INITIAL_VAL(1'b0)) soft_err_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(soft_err), .out(soft_err_bclk)); + synchronizer #(.INITIAL_VAL(1'b0)) mac_crit_err_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(mac_crit_err), .out(mac_crit_err_bclk)); + + reg [19:0] bist_lock_latency; + always @(posedge bus_clk) begin + if (!bist_checker_en && !bist_checker_locked) + bist_lock_latency <= 20'd0; + else if (bist_checker_en && !bist_checker_locked) + bist_lock_latency <= bist_lock_latency + 20'd1; + end + + reg mac_crit_err_latch; + always @(posedge bus_clk) begin + if (bus_rst | mac_clear) begin + mac_crit_err_latch <= 1'b0; + end else begin + if (mac_crit_err_bclk) + mac_crit_err_latch <= 1'b1; + end + end + + assign phy_status = {30'd0, hard_err, channel_up}; + assign mac_status = { + 6'h0, //[31:26] + mac_crit_err_latch, //[25] + 1'b1, //[24] + 1'b0, //[23] + 1'b0, //[22] + 1'b0, //[21] + 1'b0, //[20] + bist_lock_latency[19:4], //[19:4] + bist_checker_locked, //[3] + soft_err_bclk, //[2] + hard_err_bclk, //[1] + channel_up_bclk //[0] + }; + + assign link_up = channel_up_bclk; + + end else begin + + //----------------------------------------------------------------- + // Disabled + //----------------------------------------------------------------- + + assign phy_status = 'h0; + assign mac_status = 'h0; + assign link_up = 1'b0; + + assign sfpp_tx_disable = 1'b0; // Always on. + + assign c2mac_tready = 1'b1; + assign m_axis_tdata = 64'h0; + assign m_axis_tuser = 4'h0; + assign m_axis_tlast = 1'b0; + assign m_axis_tvalid = 1'b0; + + end + endgenerate + + wire identify_enable = mac_led_ctl[0]; + wire identify_value = mac_led_ctl[1]; + + //----------------------------------------------------------------- + // Activity detector + //----------------------------------------------------------------- + wire activity_int; + + pulse_stretch act_pulse_str_i ( + .clk(bus_clk), + .rst(bus_rst | ~link_up), + .pulse((s_axis_tvalid & s_axis_tready) | (m_axis_tvalid & m_axis_tready)), + .pulse_stretched(activity_int) + ); + + always @ (posedge bus_clk) activity <= identify_enable ? identify_value : activity_int; + +endmodule diff --git a/fpga/usrp3/top/e320/n3xx_sfp_wrapper.v b/fpga/usrp3/top/e320/n3xx_sfp_wrapper.v new file mode 100644 index 000000000..5067b1727 --- /dev/null +++ b/fpga/usrp3/top/e320/n3xx_sfp_wrapper.v @@ -0,0 +1,484 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2017 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: n3xx_sfp_wrapper +// Description: +// Reduces clutter at top level. +// - Aurora: wraps up sfpp_io, axil_regport and axi_dummy +// - 1/10G: wrapper around network interface +// +////////////////////////////////////////////////////////////////////// + +module n3xx_sfp_wrapper #( + parameter PROTOCOL = "10GbE", // Must be {10GbE, 1GbE, Aurora, Disabled} + parameter DWIDTH = 32, + parameter AWIDTH = 14, + parameter [7:0] PORTNUM = 8'd0, + parameter MDIO_EN = 0, + parameter [4:0] MDIO_PHYADDR = 5'd0, + parameter [15:0] RFNOC_PROTOVER = {8'd1, 8'd0} +)( + // Resets + input areset, + input bus_rst, + + // Clocks + input gt_refclk, + input gb_refclk, + input misc_clk, + input bus_clk, + // FIXME: Merge E320 and N310 files + input user_clk, + input sync_clk, + + //Axi-lite + input s_axi_aclk, + input s_axi_aresetn, + input [AWIDTH-1:0] s_axi_awaddr, + input s_axi_awvalid, + output s_axi_awready, + + input [DWIDTH-1:0] s_axi_wdata, + input [DWIDTH/8-1:0] s_axi_wstrb, + input s_axi_wvalid, + output s_axi_wready, + + output [1:0] s_axi_bresp, + output s_axi_bvalid, + input s_axi_bready, + + input [AWIDTH-1:0] s_axi_araddr, + input s_axi_arvalid, + output s_axi_arready, + + output [DWIDTH-1:0] s_axi_rdata, + output [1:0] s_axi_rresp, + output s_axi_rvalid, + input s_axi_rready, + + // SFP high-speed IO + output txp, + output txn, + input rxp, + input rxn, + + // SFP low-speed IO + input sfpp_present_n, + input sfpp_rxlos, + input sfpp_tx_fault, + output sfpp_tx_disable, + + //GT Common + input qpllrefclklost, + input qplllock, + input qplloutclk, + input qplloutrefclk, + output qpllreset, + + //Aurora MMCM + input mmcm_locked, + output gt_pll_lock, + output gt_tx_out_clk_unbuf, + + // Vita router interface + output [63:0] e2v_tdata, + output e2v_tlast, + output e2v_tvalid, + input e2v_tready, + + input [63:0] v2e_tdata, + input v2e_tlast, + input v2e_tvalid, + output v2e_tready, + + // CPU + output [63:0] e2c_tdata, + output [7:0] e2c_tkeep, + output e2c_tlast, + output e2c_tvalid, + input e2c_tready, + + input [63:0] c2e_tdata, + input [7:0] c2e_tkeep, + input c2e_tlast, + input c2e_tvalid, + output c2e_tready, + + // MISC + output [31:0] port_info, + input [15:0] device_id, + + // Timebase Outputs + output sfp_pps, + output sfp_refclk, + + // Sideband White Rabbit Control + input wr_reset_n, + input wr_refclk, + + output wr_dac_sclk, + output wr_dac_din, + output wr_dac_clr_n, + output wr_dac_cs_n, + output wr_dac_ldac_n, + + output wr_eeprom_scl_o, + input wr_eeprom_scl_i, + output wr_eeprom_sda_o, + input wr_eeprom_sda_i, + + input wr_uart_rx, + output wr_uart_tx, + + // WR AXI Control + output wr_axi_aclk, + input wr_axi_aresetn, + input [31:0] wr_axi_awaddr, + input wr_axi_awvalid, + output wr_axi_awready, + input [DWIDTH-1:0] wr_axi_wdata, + input [DWIDTH/8-1:0] wr_axi_wstrb, + input wr_axi_wvalid, + output wr_axi_wready, + output [1:0] wr_axi_bresp, + output wr_axi_bvalid, + input wr_axi_bready, + input [31:0] wr_axi_araddr, + input wr_axi_arvalid, + output wr_axi_arready, + output [DWIDTH-1:0] wr_axi_rdata, + output [1:0] wr_axi_rresp, + output wr_axi_rvalid, + input wr_axi_rready, + output wr_axi_rlast, + + output link_up, + output activity + +); + + localparam REG_BASE_SFP_IO = 14'h0; + localparam REG_BASE_ETH_SWITCH = 14'h1000; + + // AXI4-Lite to RegPort (PS to PL Register Access) + wire reg_wr_req; + wire [AWIDTH-1:0] reg_wr_addr; + wire [DWIDTH-1:0] reg_wr_data; + wire reg_rd_req; + wire [AWIDTH-1:0] reg_rd_addr; + wire reg_rd_resp, reg_rd_resp_io, reg_rd_resp_eth_if; + wire [DWIDTH-1:0] reg_rd_data, reg_rd_data_io, reg_rd_data_eth_if; + + axil_regport_master #( + .DWIDTH (DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .AWIDTH (AWIDTH), // Width of the address bus + .WRBASE (0), // Write address base + .RDBASE (0), // Read address base + .TIMEOUT (10) // log2(timeout). Read will timeout after (2^TIMEOUT - 1) cycles + ) sfp_reg_mst_i ( + // Clock and reset + .s_axi_aclk (s_axi_aclk), + .s_axi_aresetn (s_axi_aresetn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp (s_axi_bresp), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bready (s_axi_bready), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr (s_axi_araddr), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (s_axi_rdata), + .s_axi_rresp (s_axi_rresp), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rready (s_axi_rready), + // Register port: Write port (domain: reg_clk) + .reg_clk (bus_clk), + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + // Register port: Read port (domain: reg_clk) + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_resp (reg_rd_resp), + .reg_rd_data (reg_rd_data) + ); + + // Regport Mux for response + regport_resp_mux #( + .WIDTH (DWIDTH), + .NUM_SLAVES (2) + ) reg_resp_mux_i ( + .clk(bus_clk), .reset(bus_rst), + .sla_rd_resp({reg_rd_resp_eth_if, reg_rd_resp_io}), + .sla_rd_data({reg_rd_data_eth_if, reg_rd_data_io}), + .mst_rd_resp(reg_rd_resp), .mst_rd_data(reg_rd_data) + ); + + wire [63:0] sfpo_tdata, sfpi_tdata; + wire [3:0] sfpo_tuser, sfpi_tuser; + wire sfpo_tlast, sfpi_tlast, sfpo_tvalid, sfpi_tvalid, sfpo_tready, sfpi_tready; + + generate + if (PROTOCOL != "WhiteRabbit") begin + n3xx_mgt_io_core #( + .PROTOCOL (PROTOCOL), + .REG_BASE (REG_BASE_SFP_IO), + .REG_DWIDTH (DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH (AWIDTH), // Width of the address bus + .MDIO_EN (MDIO_EN), + .MDIO_PHYADDR (MDIO_PHYADDR), + .PORTNUM (PORTNUM) + ) mgt_io_i ( + //must reset all channels on quad when sfp1 gtx core is reset + .areset (areset), + .gt_refclk (gt_refclk), + .gb_refclk (gb_refclk), + .misc_clk (misc_clk), + + .bus_rst (bus_rst), + .bus_clk (bus_clk), + + .txp (txp), + .txn (txn), + .rxp (rxp), + .rxn (rxn), + + .sfpp_rxlos (sfpp_rxlos), + .sfpp_tx_fault (sfpp_tx_fault), + .sfpp_tx_disable(sfpp_tx_disable), + + //RegPort + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_resp (reg_rd_resp_io), + .reg_rd_data (reg_rd_data_io), + + // Vita to Ethernet + .s_axis_tdata (sfpi_tdata), + .s_axis_tuser (sfpi_tuser), + .s_axis_tlast (sfpi_tlast), + .s_axis_tvalid (sfpi_tvalid), + .s_axis_tready (sfpi_tready), + + // Ethernet to Vita + .m_axis_tdata (sfpo_tdata), + .m_axis_tuser (sfpo_tuser), + .m_axis_tlast (sfpo_tlast), + .m_axis_tvalid (sfpo_tvalid), + .m_axis_tready (sfpo_tready), + + .port_info (port_info), + .link_up (link_up), + .activity (activity) + ); + + end else begin + //--------------------------------------------------------------------------------- + // White Rabbit + //--------------------------------------------------------------------------------- + + wire wr_sfp_scl, wr_sfp_sda_o, wr_sfp_sda_i; + + n3xx_wr_top #( + .g_simulation(1'b0), // in std_logic + .g_dpram_size(131072/4), + .g_dpram_initf("../../../../bin/wrpc/wrc_phy16.bram") + ) wr_inst ( + .areset_n_i (wr_reset_n), // in std_logic; -- active low reset, optional + .wr_refclk_buf_i (wr_refclk), // in std_logic; -- 20MHz VCXO after IBUFGDS + .gige_refclk_buf_i (gt_refclk), // in std_logic; -- 125 MHz MGT Ref after IBUFDS_GTE2 + .dac_sclk_o (wr_dac_sclk), // out std_logic; -- N3xx cWB-DAC-SCLK + .dac_din_o (wr_dac_din), // out std_logic; -- N3xx cWB-DAC-DIN + .dac_clr_n_o (wr_dac_clr_n), // out std_logic; -- N3xx cWB-DAC-nCLR + .dac_cs_n_o (wr_dac_cs_n), // out std_logic; -- N3xx cWB-DAC-nSYNC + .dac_ldac_n_o (wr_dac_ldac_n), // out std_logic; -- N3xx cWB-DAC-nLDAC + .LED_ACT (activity), // out std_logic; -- connect to SFP+ ACT + .LED_LINK (link_up), // out std_logic; -- connect to SFP+ LINK + .sfp_txp_o (txp), // out std_logic; + .sfp_txn_o (txn), // out std_logic; + .sfp_rxp_i (rxp), // in std_logic; + .sfp_rxn_i (rxn), // in std_logic; + .sfp_mod_def0_b (sfpp_present_n), // in std_logic; - sfp detect + .eeprom_scl_o (wr_eeprom_scl_o), + .eeprom_scl_i (wr_eeprom_scl_i), + .eeprom_sda_o (wr_eeprom_sda_o), + .eeprom_sda_i (wr_eeprom_sda_i), + .sfp_scl_o (wr_sfp_scl), + .sfp_scl_i (wr_sfp_scl), + .sfp_sda_o (wr_sfp_sda_o), + .sfp_sda_i (wr_sfp_sda_i), + .sfp_tx_fault_i (sfpp_tx_fault), // in std_logic; + .sfp_tx_disable_o (sfpp_tx_disable), // out std_logic; + .sfp_los_i (sfpp_rxlos), // in std_logic; + .wr_uart_rxd (wr_uart_rx), // in std_logic; + .wr_uart_txd (wr_uart_tx), // out std_logic; + + .s00_axi_aclk_o (wr_axi_aclk), + .s00_axi_aresetn (wr_axi_aresetn), + .s00_axi_awaddr (wr_axi_awaddr), + .s00_axi_awprot (3'b0), + .s00_axi_awvalid (wr_axi_awvalid), + .s00_axi_awready (wr_axi_awready), + .s00_axi_wdata (wr_axi_wdata), + .s00_axi_wstrb (wr_axi_wstrb), + .s00_axi_wvalid (wr_axi_wvalid), + .s00_axi_wready (wr_axi_wready), + .s00_axi_bresp (wr_axi_bresp), + .s00_axi_bvalid (wr_axi_bvalid), + .s00_axi_bready (wr_axi_bready), + .s00_axi_araddr (wr_axi_araddr), + .s00_axi_arprot (3'b0), + .s00_axi_arvalid (wr_axi_arvalid), + .s00_axi_arready (wr_axi_arready), + .s00_axi_rdata (wr_axi_rdata), + .s00_axi_rresp (wr_axi_rresp), + .s00_axi_rvalid (wr_axi_rvalid), + .s00_axi_rready (wr_axi_rready), + .s00_axi_rlast (wr_axi_rlast), + .axi_int_o (), + + .pps_o (sfp_pps), // out std_logic; + .clk_pps_o (sfp_refclk), // out std_logic; + .link_ok_o (), // out std_logic; + .clk_sys_locked_o (), // out std_logic; + .clk_dmtd_locked_o (), // out std_logic); + .wr_debug0_o (), + .wr_debug1_o () + ); + + // TEMPORARY mimic the AXGE SFP EEROM + sfp_eeprom sfp_eeprom_i ( + .clk_i(bus_clk), + .sfp_scl(wr_sfp_scl), + .sfp_sda_i(wr_sfp_sda_o), + .sfp_sda_o(wr_sfp_sda_i)); + + // Assign the port_info vector similarly to mgt_io_core + localparam [7:0] COMPAT_NUM = 8'd2; + localparam [7:0] MGT_PROTOCOL = 8'd4; + assign port_info = {COMPAT_NUM, 6'h0, activity, link_up, MGT_PROTOCOL, PORTNUM}; + + // Tie off unused outputs. + assign gt_pll_lock = 1'b0; + assign gt_tx_out_clk_unbuf = 1'b0; + end + endgenerate + + generate + // Tie off the Ethernet switch for these protocols that do not use it. + if(PROTOCOL == "Aurora" || PROTOCOL == "Disabled" || PROTOCOL == "WhiteRabbit") begin + + //set unused wires to default value + assign e2c_tdata = 64'h0; + assign e2c_tkeep = 8'h0; + assign e2c_tlast = 1'b0; + assign e2c_tvalid = 1'b0; + assign c2e_tready = 1'b1; + + assign reg_rd_resp_eth_if = 1'b0; + assign reg_rd_data_eth_if = 'h0; + + end else begin + + wire [3:0] e2c_tuser; + wire [3:0] c2e_tuser; + + // In AXI Stream, tkeep is the byte qualifier that indicates + // whether the content of the associated byte + // of TDATA is processed as part of the data stream. + // tuser as used in eth_interface is the number of valid bytes + + // Converting tuser to tkeep for ingress packets + assign e2c_tkeep = ~e2c_tlast ? 8'b1111_1111 + : (e2c_tuser == 4'd0) ? 8'b1111_1111 + : (e2c_tuser == 4'd1) ? 8'b0000_0001 + : (e2c_tuser == 4'd2) ? 8'b0000_0011 + : (e2c_tuser == 4'd3) ? 8'b0000_0111 + : (e2c_tuser == 4'd4) ? 8'b0000_1111 + : (e2c_tuser == 4'd5) ? 8'b0001_1111 + : (e2c_tuser == 4'd6) ? 8'b0011_1111 + : 8'b0111_1111; + + // Converting tkeep to tuser for egress packets + assign c2e_tuser = ~c2e_tlast ? 4'd0 + : (c2e_tkeep == 8'b1111_1111) ? 4'd0 + : (c2e_tkeep == 8'b0111_1111) ? 4'd7 + : (c2e_tkeep == 8'b0011_1111) ? 4'd6 + : (c2e_tkeep == 8'b0001_1111) ? 4'd5 + : (c2e_tkeep == 8'b0000_1111) ? 4'd4 + : (c2e_tkeep == 8'b0000_0111) ? 4'd3 + : (c2e_tkeep == 8'b0000_0011) ? 4'd2 + : (c2e_tkeep == 8'b0000_0001) ? 4'd1 + : 4'd0; + + + eth_interface #( + .PROTOVER (RFNOC_PROTOVER), + .MTU (10), + .NODE_INST (0), + .REG_AWIDTH (AWIDTH), + .BASE (REG_BASE_ETH_SWITCH) + ) eth_interface ( + .clk (bus_clk), + .reset (bus_rst), + .device_id (device_id), + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_resp (reg_rd_resp_eth_if), + .reg_rd_data (reg_rd_data_eth_if), + .my_mac (), + .my_ip (), + .my_udp_port (), + .eth_tx_tdata (sfpi_tdata), + .eth_tx_tuser (sfpi_tuser), + .eth_tx_tlast (sfpi_tlast), + .eth_tx_tvalid (sfpi_tvalid), + .eth_tx_tready (sfpi_tready), + .eth_rx_tdata (sfpo_tdata), + .eth_rx_tuser (sfpo_tuser), + .eth_rx_tlast (sfpo_tlast), + .eth_rx_tvalid (sfpo_tvalid), + .eth_rx_tready (sfpo_tready), + .e2v_tdata (e2v_tdata), + .e2v_tlast (e2v_tlast), + .e2v_tvalid (e2v_tvalid), + .e2v_tready (e2v_tready), + .v2e_tdata (v2e_tdata), + .v2e_tlast (v2e_tlast), + .v2e_tvalid (v2e_tvalid), + .v2e_tready (v2e_tready), + .e2c_tdata (e2c_tdata), + .e2c_tuser (e2c_tuser), + .e2c_tlast (e2c_tlast), + .e2c_tvalid (e2c_tvalid), + .e2c_tready (e2c_tready), + .c2e_tdata (c2e_tdata), + .c2e_tuser (c2e_tuser), + .c2e_tlast (c2e_tlast), + .c2e_tvalid (c2e_tvalid), + .c2e_tready (c2e_tready) + ); + + end + endgenerate + +endmodule // n310_sfp_wrapper diff --git a/fpga/usrp3/top/e320/setupenv.sh b/fpga/usrp3/top/e320/setupenv.sh new file mode 100644 index 000000000..76bf520ed --- /dev/null +++ b/fpga/usrp3/top/e320/setupenv.sh @@ -0,0 +1,10 @@ +#!/bin/bash + +VIVADO_VER=2019.1 +DISPLAY_NAME="USRP-E320" +REPO_BASE_PATH=$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd) + +declare -A PRODUCT_ID_MAP +PRODUCT_ID_MAP["E320"]="zynq/xc7z045/ffg900/-3" + +source $REPO_BASE_PATH/tools/scripts/setupenv_base.sh |