fpga: Update all RFNoC images

2 files changed, 46 insertions, 42 deletions

diff --git a/fpga/usrp3/top/e320/e320_rfnoc_image_core.v b/fpga/usrp3/top/e320/e320_rfnoc_image_core.v
index 928a26a60..229f6fdb2 100644
--- a/fpga/usrp3/top/e320/e320_rfnoc_image_core.v
+++ b/fpga/usrp3/top/e320/e320_rfnoc_image_core.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -13,9 +13,9 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// File generated on: 2021-05-03T08:51:10.699215
+// File generated on: 2022-03-29T22:54:33.413161
 // Source: e320_rfnoc_image_core.yml
-// Source SHA256: 8b38ab7ba86e214c213ab62a63b698739c0858fdf10fcc5b737f87a56fb04454
+// Source SHA256: ed6f477f04b43f41fc51cbc753947560d39edc7520864fb72959a7b856595f47
 //
 
 `default_nettype none
@@ -38,7 +38,7 @@ module rfnoc_image_core #(
 
   // IO ports /////////////////////////
 
-  // ctrl_port
+  // ctrlport
   output wire [   0:0] m_ctrlport_req_wr,
   output wire [   0:0] m_ctrlport_req_rd,
   output wire [  19:0] m_ctrlport_req_addr,
@@ -49,19 +49,19 @@ module rfnoc_image_core #(
   input  wire [   0:0] m_ctrlport_resp_ack,
   input  wire [   1:0] m_ctrlport_resp_status,
   input  wire [  31:0] m_ctrlport_resp_data,
-  // time_keeper
+  // time
   input  wire [  63:0] radio_time,
-  // x300_radio
-  input  wire [  63:0] radio_rx_data,
-  input  wire [   1:0] radio_rx_stb,
-  output wire [   1:0] radio_rx_running,
-  output wire [  63:0] radio_tx_data,
-  input  wire [   1:0] radio_tx_stb,
-  output wire [   1:0] radio_tx_running,
+  // radio
+  input  wire [ 255:0] radio_rx_data,
+  input  wire [   7:0] radio_rx_stb,
+  output wire [   7:0] radio_rx_running,
+  output wire [ 255:0] radio_tx_data,
+  input  wire [   7:0] radio_tx_stb,
+  output wire [   7:0] radio_tx_running,
   // dram
   input  wire [   0:0] axi_rst,
   output wire [   3:0] m_axi_awid,
-  output wire [ 127:0] m_axi_awaddr,
+  output wire [ 191:0] m_axi_awaddr,
   output wire [  31:0] m_axi_awlen,
   output wire [  11:0] m_axi_awsize,
   output wire [   7:0] m_axi_awburst,
@@ -73,8 +73,8 @@ module rfnoc_image_core #(
   output wire [   3:0] m_axi_awuser,
   output wire [   3:0] m_axi_awvalid,
   input  wire [   3:0] m_axi_awready,
-  output wire [ 255:0] m_axi_wdata,
-  output wire [  31:0] m_axi_wstrb,
+  output wire [2047:0] m_axi_wdata,
+  output wire [ 255:0] m_axi_wstrb,
   output wire [   3:0] m_axi_wlast,
   output wire [   3:0] m_axi_wuser,
   output wire [   3:0] m_axi_wvalid,
@@ -85,7 +85,7 @@ module rfnoc_image_core #(
   input  wire [   3:0] m_axi_bvalid,
   output wire [   3:0] m_axi_bready,
   output wire [   3:0] m_axi_arid,
-  output wire [ 127:0] m_axi_araddr,
+  output wire [ 191:0] m_axi_araddr,
   output wire [  31:0] m_axi_arlen,
   output wire [  11:0] m_axi_arsize,
   output wire [   7:0] m_axi_arburst,
@@ -98,7 +98,7 @@ module rfnoc_image_core #(
   output wire [   3:0] m_axi_arvalid,
   input  wire [   3:0] m_axi_arready,
   input  wire [   3:0] m_axi_rid,
-  input  wire [ 255:0] m_axi_rdata,
+  input  wire [2047:0] m_axi_rdata,
   input  wire [   7:0] m_axi_rresp,
   input  wire [   3:0] m_axi_rlast,
   input  wire [   3:0] m_axi_ruser,
@@ -679,7 +679,7 @@ module rfnoc_image_core #(
   wire              m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
   wire              m_radio0_out_1_tready, m_radio0_out_0_tready;
 
-  // ctrl_port
+  // ctrlport
   wire [   0:0] radio0_m_ctrlport_req_wr;
   wire [   0:0] radio0_m_ctrlport_req_rd;
   wire [  19:0] radio0_m_ctrlport_req_addr;
@@ -690,20 +690,22 @@ module rfnoc_image_core #(
   wire [   0:0] radio0_m_ctrlport_resp_ack;
   wire [   1:0] radio0_m_ctrlport_resp_status;
   wire [  31:0] radio0_m_ctrlport_resp_data;
-  // time_keeper
+  // time
   wire [  63:0] radio0_radio_time;
-  // x300_radio
-  wire [  63:0] radio0_radio_rx_data;
-  wire [   1:0] radio0_radio_rx_stb;
-  wire [   1:0] radio0_radio_rx_running;
-  wire [  63:0] radio0_radio_tx_data;
-  wire [   1:0] radio0_radio_tx_stb;
-  wire [   1:0] radio0_radio_tx_running;
+  // radio
+  wire [ 255:0] radio0_radio_rx_data;
+  wire [   7:0] radio0_radio_rx_stb;
+  wire [   7:0] radio0_radio_rx_running;
+  wire [ 255:0] radio0_radio_tx_data;
+  wire [   7:0] radio0_radio_tx_stb;
+  wire [   7:0] radio0_radio_tx_running;
 
   rfnoc_block_radio #(
     .THIS_PORTID         (4),
     .CHDR_W              (CHDR_W),
     .NUM_PORTS           (2),
+    .NIPC                (1),
+    .ITEM_W              (32),
     .MTU                 (MTU)
   ) b_radio0_2 (
     .rfnoc_chdr_clk      (rfnoc_chdr_clk),
@@ -763,7 +765,7 @@ module rfnoc_image_core #(
   // axi_ram
   wire [   0:0] fifo0_axi_rst;
   wire [   3:0] fifo0_m_axi_awid;
-  wire [ 127:0] fifo0_m_axi_awaddr;
+  wire [ 191:0] fifo0_m_axi_awaddr;
   wire [  31:0] fifo0_m_axi_awlen;
   wire [  11:0] fifo0_m_axi_awsize;
   wire [   7:0] fifo0_m_axi_awburst;
@@ -775,8 +777,8 @@ module rfnoc_image_core #(
   wire [   3:0] fifo0_m_axi_awuser;
   wire [   3:0] fifo0_m_axi_awvalid;
   wire [   3:0] fifo0_m_axi_awready;
-  wire [ 255:0] fifo0_m_axi_wdata;
-  wire [  31:0] fifo0_m_axi_wstrb;
+  wire [2047:0] fifo0_m_axi_wdata;
+  wire [ 255:0] fifo0_m_axi_wstrb;
   wire [   3:0] fifo0_m_axi_wlast;
   wire [   3:0] fifo0_m_axi_wuser;
   wire [   3:0] fifo0_m_axi_wvalid;
@@ -787,7 +789,7 @@ module rfnoc_image_core #(
   wire [   3:0] fifo0_m_axi_bvalid;
   wire [   3:0] fifo0_m_axi_bready;
   wire [   3:0] fifo0_m_axi_arid;
-  wire [ 127:0] fifo0_m_axi_araddr;
+  wire [ 191:0] fifo0_m_axi_araddr;
   wire [  31:0] fifo0_m_axi_arlen;
   wire [  11:0] fifo0_m_axi_arsize;
   wire [   7:0] fifo0_m_axi_arburst;
@@ -800,7 +802,7 @@ module rfnoc_image_core #(
   wire [   3:0] fifo0_m_axi_arvalid;
   wire [   3:0] fifo0_m_axi_arready;
   wire [   3:0] fifo0_m_axi_rid;
-  wire [ 255:0] fifo0_m_axi_rdata;
+  wire [2047:0] fifo0_m_axi_rdata;
   wire [   7:0] fifo0_m_axi_rresp;
   wire [   3:0] fifo0_m_axi_rlast;
   wire [   3:0] fifo0_m_axi_ruser;
@@ -810,12 +812,14 @@ module rfnoc_image_core #(
   rfnoc_block_axi_ram_fifo #(
     .THIS_PORTID         (5),
     .CHDR_W              (CHDR_W),
+    .NUM_PORTS           (2),
     .MEM_ADDR_W          (31),
     .MEM_DATA_W          (64),
     .MEM_CLK_RATE        (300e6),
     .FIFO_ADDR_BASE      ({31'h02000000, 31'h00000000}),
     .FIFO_ADDR_MASK      ({31'h01FFFFFF, 31'h01FFFFFF}),
-    .NUM_PORTS           (2),
+    .IN_FIFO_SIZE        (),
+    .OUT_FIFO_SIZE       (),
     .MTU                 (MTU)
   ) b_fifo0_3 (
     .rfnoc_chdr_clk      (rfnoc_chdr_clk),
@@ -983,13 +987,6 @@ module rfnoc_image_core #(
   assign radio0_m_ctrlport_resp_status = m_ctrlport_resp_status;
   assign radio0_m_ctrlport_resp_data = m_ctrlport_resp_data;
 
-  assign radio0_radio_rx_data = radio_rx_data;
-  assign radio0_radio_rx_stb = radio_rx_stb;
-  assign radio_rx_running = radio0_radio_rx_running;
-  assign radio_tx_data = radio0_radio_tx_data;
-  assign radio0_radio_tx_stb = radio_tx_stb;
-  assign radio_tx_running = radio0_radio_tx_running;
-
   assign fifo0_axi_rst = axi_rst;
   assign m_axi_awid = fifo0_m_axi_awid;
   assign m_axi_awaddr = fifo0_m_axi_awaddr;
@@ -1036,6 +1033,13 @@ module rfnoc_image_core #(
   assign fifo0_m_axi_rvalid = m_axi_rvalid;
   assign m_axi_rready = fifo0_m_axi_rready;
 
+  assign radio0_radio_rx_data = radio_rx_data;
+  assign radio0_radio_rx_stb = radio_rx_stb;
+  assign radio_rx_running = radio0_radio_rx_running;
+  assign radio_tx_data = radio0_radio_tx_data;
+  assign radio0_radio_tx_stb = radio_tx_stb;
+  assign radio_tx_running = radio0_radio_tx_running;
+
   // Broadcaster/Listener Connections:
   assign radio0_radio_time = radio_time;
 
diff --git a/fpga/usrp3/top/e320/e320_rfnoc_image_core.vh b/fpga/usrp3/top/e320/e320_rfnoc_image_core.vh
index 7e7b3f72d..a00d17d2c 100644
--- a/fpga/usrp3/top/e320/e320_rfnoc_image_core.vh
+++ b/fpga/usrp3/top/e320/e320_rfnoc_image_core.vh
@@ -1,5 +1,5 @@
 //
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -12,9 +12,9 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// File generated on: 2021-05-03T08:51:10.746455
+// File generated on: 2022-03-29T22:54:33.447436
 // Source: e320_rfnoc_image_core.yml
-// Source SHA256: 8b38ab7ba86e214c213ab62a63b698739c0858fdf10fcc5b737f87a56fb04454
+// Source SHA256: ed6f477f04b43f41fc51cbc753947560d39edc7520864fb72959a7b856595f47
 //
 
 `define CHDR_WIDTH     64