aboutsummaryrefslogtreecommitdiffstats
path: root/fpga/usrp3/top/b200/planahead/planahead.ppr
diff options
context:
space:
mode:
authorNicholas Corgan <nick.corgan@ettus.com>2014-02-20 06:05:38 -0800
committerNicholas Corgan <nick.corgan@ettus.com>2014-02-20 06:05:38 -0800
commit09882ad86432db5087f85764c02989dbfc70fd3f (patch)
tree303acff16086d4ecf74e2a800b1eba85e6325b71 /fpga/usrp3/top/b200/planahead/planahead.ppr
parent7fef199d194c9a63b3312845979fa353f90f4d23 (diff)
downloaduhd-09882ad86432db5087f85764c02989dbfc70fd3f.tar.gz
uhd-09882ad86432db5087f85764c02989dbfc70fd3f.tar.bz2
uhd-09882ad86432db5087f85764c02989dbfc70fd3f.zip
fpga: removed superfluous B2x0 files
Diffstat (limited to 'fpga/usrp3/top/b200/planahead/planahead.ppr')
-rw-r--r--fpga/usrp3/top/b200/planahead/planahead.ppr28
1 files changed, 0 insertions, 28 deletions
diff --git a/fpga/usrp3/top/b200/planahead/planahead.ppr b/fpga/usrp3/top/b200/planahead/planahead.ppr
deleted file mode 100644
index 706cfae4b..000000000
--- a/fpga/usrp3/top/b200/planahead/planahead.ppr
+++ /dev/null
@@ -1,28 +0,0 @@
-<?xml version="1.0"?>
-<!--Product Version: PlanAhead v14.4 (64-bit)-->
-<Project Version="4" Minor="36">
- <FileSet Dir="sources_1" File="fileset.xml"/>
- <FileSet Dir="constrs_1" File="fileset.xml"/>
- <FileSet Dir="sim_1" File="fileset.xml"/>
- <RunSet Dir="runs" File="runs.xml"/>
- <DefaultLaunch Dir="$PRUNDIR"/>
- <DefaultPromote Dir="$PROMOTEDIR"/>
- <Config>
- <Option Name="Id" Val="0f51201731ac4b37b508a9b552ac0aac"/>
- <Option Name="Part" Val="xc6slx75fgg484-3"/>
- <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
- <Option Name="TargetLanguage" Val="Verilog"/>
- <Option Name="TargetSimulator" Val="ISim"/>
- <Option Name="Board" Val=""/>
- <Option Name="SourceMgmtMode" Val="All"/>
- <Option Name="ActiveSimSet" Val="sim_1"/>
- <Option Name="CxlOverwriteLibs" Val="1"/>
- <Option Name="CxlFuncsim" Val="1"/>
- <Option Name="CxlTimesim" Val="1"/>
- <Option Name="CxlCore" Val="1"/>
- <Option Name="CxlEdk" Val="0"/>
- <Option Name="CxlExcludeCores" Val="1"/>
- <Option Name="CxlExcludeSubLibs" Val="0"/>
- </Config>
-</Project>
-