From 09882ad86432db5087f85764c02989dbfc70fd3f Mon Sep 17 00:00:00 2001
From: Nicholas Corgan <nick.corgan@ettus.com>
Date: Thu, 20 Feb 2014 06:05:38 -0800
Subject: fpga: removed superfluous B2x0 files

---
 fpga/usrp3/top/b200/planahead/planahead.ppr | 28 ----------------------------
 1 file changed, 28 deletions(-)
 delete mode 100644 fpga/usrp3/top/b200/planahead/planahead.ppr

(limited to 'fpga/usrp3/top/b200/planahead/planahead.ppr')

diff --git a/fpga/usrp3/top/b200/planahead/planahead.ppr b/fpga/usrp3/top/b200/planahead/planahead.ppr
deleted file mode 100644
index 706cfae4b..000000000
--- a/fpga/usrp3/top/b200/planahead/planahead.ppr
+++ /dev/null
@@ -1,28 +0,0 @@
-<?xml version="1.0"?>
-<!--Product Version: PlanAhead v14.4 (64-bit)-->
-<Project Version="4" Minor="36">
-	<FileSet Dir="sources_1" File="fileset.xml"/>
-	<FileSet Dir="constrs_1" File="fileset.xml"/>
-	<FileSet Dir="sim_1" File="fileset.xml"/>
-	<RunSet Dir="runs" File="runs.xml"/>
-	<DefaultLaunch Dir="$PRUNDIR"/>
-	<DefaultPromote Dir="$PROMOTEDIR"/>
-	<Config>
-		<Option Name="Id" Val="0f51201731ac4b37b508a9b552ac0aac"/>
-		<Option Name="Part" Val="xc6slx75fgg484-3"/>
-		<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
-		<Option Name="TargetLanguage" Val="Verilog"/>
-		<Option Name="TargetSimulator" Val="ISim"/>
-		<Option Name="Board" Val=""/>
-		<Option Name="SourceMgmtMode" Val="All"/>
-		<Option Name="ActiveSimSet" Val="sim_1"/>
-		<Option Name="CxlOverwriteLibs" Val="1"/>
-		<Option Name="CxlFuncsim" Val="1"/>
-		<Option Name="CxlTimesim" Val="1"/>
-		<Option Name="CxlCore" Val="1"/>
-		<Option Name="CxlEdk" Val="0"/>
-		<Option Name="CxlExcludeCores" Val="1"/>
-		<Option Name="CxlExcludeSubLibs" Val="0"/>
-	</Config>
-</Project>
-
-- 
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