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authorBen Hilburn <ben.hilburn@ettus.com>2014-05-14 11:42:19 -0700
committerBen Hilburn <ben.hilburn@ettus.com>2014-05-14 11:42:19 -0700
commit00711ba213dde8aa0a099d2b18d3da0a33e6af79 (patch)
tree612f616ebbf8080b5dc9cb5d64a8062e9aa3a498 /fpga/usrp3/top/b200/planahead/planahead.data/sim_1
parent5de0bfce3f03cc45a1eed93dc1b8df1b188b5040 (diff)
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fpga: updating b200 and x300 FPGA source code for latest images
Diffstat (limited to 'fpga/usrp3/top/b200/planahead/planahead.data/sim_1')
-rw-r--r--fpga/usrp3/top/b200/planahead/planahead.data/sim_1/fileset.xml10
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diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/sim_1/fileset.xml b/fpga/usrp3/top/b200/planahead/planahead.data/sim_1/fileset.xml
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+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+ <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ <Option Name="SrcSet" Val="sources_1"/>
+ </Config>
+ </FileSet>
+</DARoots>