diff options
| author | Ben Hilburn <ben.hilburn@ettus.com> | 2014-05-14 11:42:19 -0700 |
|---|---|---|
| committer | Ben Hilburn <ben.hilburn@ettus.com> | 2014-05-14 11:42:19 -0700 |
| commit | 00711ba213dde8aa0a099d2b18d3da0a33e6af79 (patch) | |
| tree | 612f616ebbf8080b5dc9cb5d64a8062e9aa3a498 /fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1 | |
| parent | 5de0bfce3f03cc45a1eed93dc1b8df1b188b5040 (diff) | |
| download | uhd-00711ba213dde8aa0a099d2b18d3da0a33e6af79.tar.gz uhd-00711ba213dde8aa0a099d2b18d3da0a33e6af79.tar.bz2 uhd-00711ba213dde8aa0a099d2b18d3da0a33e6af79.zip | |
fpga: updating b200 and x300 FPGA source code for latest images
Diffstat (limited to 'fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1')
4 files changed, 83 insertions, 0 deletions
diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_in.xml b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_in.xml new file mode 100644 index 000000000..d7d32c943 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_in.xml @@ -0,0 +1,25 @@ +<?xml version="1.0" encoding="UTF-8"?> +<DARoots Version="1" Minor="26"> + <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1"> + <Filter Type="Constrs"/> + <File Path="$PSRCDIR/constrs_1/imports/b200/b200.ucf"> + <FileInfo> + <Attr Name="ImportPath" Val="$PPRDIR/../b200.ucf"/> + <Attr Name="ImportTime" Val="1358988004"/> + <Attr Name="UsedInSynthesis" Val="1"/> + <Attr Name="UsedInImplementation" Val="1"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/constrs_1/imports/b200/timing.ucf"> + <FileInfo> + <Attr Name="ImportPath" Val="$PPRDIR/../timing.ucf"/> + <Attr Name="ImportTime" Val="1359506480"/> + <Attr Name="UsedInSynthesis" Val="1"/> + <Attr Name="UsedInImplementation" Val="1"/> + </FileInfo> + </File> + <Config> + <Option Name="ConstrsType" Val="UCF"/> + </Config> + </FileSet> +</DARoots> diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_out.xml b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_out.xml new file mode 100644 index 000000000..4d152cf5b --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_out.xml @@ -0,0 +1,20 @@ +<?xml version="1.0" encoding="UTF-8"?> +<DARoots Version="1" Minor="26"> + <FileSet Name="constrs_out" Type="Constrs" RelSrcDir="$PRUNDIR/impl_1/.constrs"> + <File Path="$PRUNDIR/impl_1/.constrs/b200.ucf"> + <FileInfo> + <Attr Name="UsedInSynthesis" Val="1"/> + <Attr Name="UsedInImplementation" Val="1"/> + </FileInfo> + </File> + <File Path="$PRUNDIR/impl_1/.constrs/timing.ucf"> + <FileInfo> + <Attr Name="UsedInSynthesis" Val="1"/> + <Attr Name="UsedInImplementation" Val="1"/> + </FileInfo> + </File> + <Config> + <Option Name="ConstrsType" Val="UCF"/> + </Config> + </FileSet> +</DARoots> diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/impl_1.psg b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/impl_1.psg new file mode 100644 index 000000000..147f3a950 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/impl_1.psg @@ -0,0 +1,20 @@ +<?xml version="1.0"?> +<Strategy Version="1" Minor="2"> + <StratHandle Name="ISE Defaults" Flow="ISE14"> + <Desc>ISE Defaults, including packing registers in IOs off</Desc> + </StratHandle> + <Step Id="ngdbuild"> + </Step> + <Step Id="map"> + <Option Id="FFPackEnum">3</Option> + </Step> + <Step Id="par"> + </Step> + <Step Id="trce"> + </Step> + <Step Id="xdl"> + </Step> + <Step Id="bitgen"> + </Step> +</Strategy> + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/sources.xml b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/sources.xml new file mode 100644 index 000000000..1ebdc052b --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/sources.xml @@ -0,0 +1,18 @@ +<?xml version="1.0" encoding="UTF-8"?> +<DARoots Version="1" Minor="26"> + <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1"> + <Filter Type="Srcs"/> + <File Path="$PSRCDIR/sources_1/imports/build/b200.ngc"> + <FileInfo> + <Attr Name="ImportPath" Val="$PPRDIR/../build/b200.ngc"/> + <Attr Name="ImportTime" Val="1359508205"/> + <Attr Name="UsedInSynthesis" Val="1"/> + <Attr Name="UsedInImplementation" Val="1"/> + </FileInfo> + </File> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="b200"/> + </Config> + </FileSet> +</DARoots> |