diff options
| author | Ben Hilburn <ben.hilburn@ettus.com> | 2013-10-10 10:17:27 -0700 |
|---|---|---|
| committer | Ben Hilburn <ben.hilburn@ettus.com> | 2013-10-10 10:17:27 -0700 |
| commit | 0df4b801a34697f2058b4a7b95e08d2a0576c9db (patch) | |
| tree | be10e78d1a97c037a9e7492360a178d1873b9c09 /fpga/usrp3/top/b200/coregen | |
| parent | 6e7bc850b66e8188718248b76b729c7cf9c89700 (diff) | |
| download | uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.tar.gz uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.tar.bz2 uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.zip | |
Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.
Diffstat (limited to 'fpga/usrp3/top/b200/coregen')
260 files changed, 19599 insertions, 0 deletions
diff --git a/fpga/usrp3/top/b200/coregen/.gitignore b/fpga/usrp3/top/b200/coregen/.gitignore new file mode 100644 index 000000000..5f2f0dd7d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/.gitignore @@ -0,0 +1,3 @@ +/tmp +/_xmsgs +/*.log diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.asy b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.asy new file mode 100644 index 000000000..eb4747f81 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.asy @@ -0,0 +1,9 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 b200_chipscope_icon +RECTANGLE Normal 32 32 544 864 +LINE Wide 576 112 544 112 +PIN 576 112 RIGHT 36 +PINATTR PinName control0[35:0] +PINATTR Polarity BOTH + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.ucf b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.ucf new file mode 100644 index 000000000..b83296f8e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.ucf @@ -0,0 +1,9 @@ +NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ; +TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ; +#Update Constraints +NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ; +NET "U0/iSHIFT_OUT" TIG ; +TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ; +TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ; +TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ; +TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ; diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.xdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.xdc new file mode 100644 index 000000000..903799425 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.xdc @@ -0,0 +1,7 @@ +# icon XDC +create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] +create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}] +set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}] +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2 +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1 +set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK} diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.gise b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.gise new file mode 100644 index 000000000..d2bb766ed --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.gise @@ -0,0 +1,31 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="b200_chipscope_icon.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="b200_chipscope_icon.asy" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="b200_chipscope_icon.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ncf b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ncf new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ncf diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ngc b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ngc new file mode 100644 index 000000000..d43ee8b57 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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3`=02c=57>5;h4b>5<<a?h1<75f6b83>>i?:3:17pll3;291?6=8r.2m796;I3;6>N6?m1/4>4>b79'2c<03`<26=44i7c94?=n>k0;66g9c;29?j>52900qom=:186>5<7s-3j6:74H0:1?M70l2.3?7?m6:&5b?0<a?31<75f6`83>>o1j3:17d8l:188k=4=831vnn?50;794?6|,0k1;45G1908L41c3-286<l9;%4e>0=n>00;66g9a;29?l0e2900e;m50;9l<7<722wio=4?:483>5}#1h0<56F>839K52b<,191=o84$7d90>o113:17d8n:188m3d=831b:n4?::m;6?6=3thij7>55;294~">i3=27E?72:J23a=#0:0:n;5+6g80?l0>2900e;o50;9j2g<722c=o7>5;n:1>5<<ukh36=4::183!?f2>30D<6=;I34`>"?;3;i:6*9f;08m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjm:1<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 =?=9h80e;750;9j2d<722c=n7>5;h4`>5<<g181<75rbe394?3=83:p(4o5789K5=4<@8=o7)6<:0`5?!0a2830(5751`08m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjmo1<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 =?=90:0e;750;9j2d<722c=n7>5;h4`>5<<g181<75rbed94?3=83:p(4o5789K5=4<@8=o7)6<:0`5?!0a2830(5751828m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjl:1<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ucf b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ucf new file mode 100644 index 000000000..b83296f8e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ucf @@ -0,0 +1,9 @@ +NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ; +TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ; +#Update Constraints +NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ; +NET "U0/iSHIFT_OUT" TIG ; +TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ; +TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ; +TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ; +TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ; diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.v b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.v new file mode 100644 index 000000000..30b31cca5 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.v @@ -0,0 +1,27 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : b200_chipscope_icon.v +// /___/ /\ Timestamp : Tue Feb 19 14:28:40 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: Verilog Synthesis Wrapper +/////////////////////////////////////////////////////////////////////////////// +// This wrapper is used to integrate with Project Navigator and PlanAhead + +`timescale 1ns/1ps + +module b200_chipscope_icon( + CONTROL0) /* synthesis syn_black_box syn_noprune=1 */; + + +inout [35 : 0] CONTROL0; + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.veo b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.veo new file mode 100644 index 000000000..6c82410b6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.veo @@ -0,0 +1,28 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : b200_chipscope_icon.veo +// /___/ /\ Timestamp : Tue Feb 19 14:28:40 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: ISE Instantiation template +/////////////////////////////////////////////////////////////////////////////// + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +b200_chipscope_icon YourInstanceName ( + .CONTROL0(CONTROL0) // INOUT BUS [35:0] +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xco b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xco new file mode 100644 index 000000000..2b7395488 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xco @@ -0,0 +1,56 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Tue Feb 19 22:27:58 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a +# END Select +# BEGIN Parameters +CSET component_name=b200_chipscope_icon +CSET constraint_type=external +CSET enable_jtag_bufg=true +CSET example_design=false +CSET number_control_ports=1 +CSET use_ext_bscan=false +CSET use_softbscan=false +CSET use_unused_bscan=false +CSET user_scan_chain=USER1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T02:47:25Z +# END Extra information +GENERATE +# CRC: 729764e8 diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xdc new file mode 100644 index 000000000..903799425 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xdc @@ -0,0 +1,7 @@ +# icon XDC +create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] +create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}] +set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}] +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2 +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1 +set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK} diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xise b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xise new file mode 100644 index 000000000..4a695b8b0 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xise @@ -0,0 +1,73 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="b200_chipscope_icon.ngc" xil_pn:type="FILE_NGC"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="b200_chipscope_icon.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/> + </file> + </files> + + <properties> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> + <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Module|b200_chipscope_icon" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top File" xil_pn:value="b200_chipscope_icon.ngc" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/b200_chipscope_icon" xil_pn:valueState="non-default"/> + <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_DesignName" xil_pn:value="b200_chipscope_icon" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-02-19T14:28:45" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A24BB47ADAFD196B0AED5F1EDE7080BB" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_flist.txt b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_flist.txt new file mode 100644 index 000000000..97a36c09d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_flist.txt @@ -0,0 +1,15 @@ +# Output products list for <b200_chipscope_icon> +b200_chipscope_icon.asy +b200_chipscope_icon.constraints/b200_chipscope_icon.ucf +b200_chipscope_icon.constraints/b200_chipscope_icon.xdc +b200_chipscope_icon.gise +b200_chipscope_icon.ngc +b200_chipscope_icon.ucf +b200_chipscope_icon.v +b200_chipscope_icon.veo +b200_chipscope_icon.xco +b200_chipscope_icon.xdc +b200_chipscope_icon.xise +b200_chipscope_icon_flist.txt +b200_chipscope_icon_readme.txt +b200_chipscope_icon_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_readme.txt b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_readme.txt new file mode 100644 index 000000000..c3b896f44 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_readme.txt @@ -0,0 +1,45 @@ +The following files were generated for 'b200_chipscope_icon' in directory +/home/bhilburn/xilinx/ + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * b200_chipscope_icon.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * b200_chipscope_icon.constraints/b200_chipscope_icon.ucf + * b200_chipscope_icon.constraints/b200_chipscope_icon.xdc + * b200_chipscope_icon.ngc + * b200_chipscope_icon.ucf + * b200_chipscope_icon.v + * b200_chipscope_icon.veo + * b200_chipscope_icon.xdc + * b200_chipscope_icon_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * b200_chipscope_icon.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * b200_chipscope_icon.gise + * b200_chipscope_icon.xise + +Deliver Readme: + Readme file for the IP. + + * b200_chipscope_icon_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * b200_chipscope_icon_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_xmdf.tcl b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_xmdf.tcl new file mode 100755 index 000000000..c9d1c0b14 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_xmdf.tcl @@ -0,0 +1,88 @@ +# The package naming convention is <core_name>_xmdf +package provide b200_chipscope_icon_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is <core_name>_xmdf +namespace eval ::b200_chipscope_icon_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::b200_chipscope_icon_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: <module_name> +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_chipscope_icon +} +# ::b200_chipscope_icon_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::b200_chipscope_icon_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.constraints/b200_chipscope_icon.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.constraints/b200_chipscope_icon.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.xcf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_chipscope_icon +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.asy b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.asy new file mode 100644 index 000000000..fcca7f4e0 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.asy @@ -0,0 +1,21 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 b200_chipscope_ila +RECTANGLE Normal 32 32 288 704 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName control[35:0] +PINATTR Polarity IN +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Wide 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName data[63:0] +PINATTR Polarity IN +LINE Wide 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName trig0[7:0] +PINATTR Polarity IN + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.cdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.cdc new file mode 100644 index 000000000..985834f8d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.cdc @@ -0,0 +1,83 @@ +#ChipScope Core Generator Project File Version 3.0 +#Tue Feb 19 16:52:47 PST 2013 +SignalExport.clockChannel=CLK +SignalExport.dataChannel<0000>=DATA[0] +SignalExport.dataChannel<0001>=DATA[1] +SignalExport.dataChannel<0002>=DATA[2] +SignalExport.dataChannel<0003>=DATA[3] +SignalExport.dataChannel<0004>=DATA[4] +SignalExport.dataChannel<0005>=DATA[5] +SignalExport.dataChannel<0006>=DATA[6] +SignalExport.dataChannel<0007>=DATA[7] +SignalExport.dataChannel<0008>=DATA[8] +SignalExport.dataChannel<0009>=DATA[9] +SignalExport.dataChannel<0010>=DATA[10] +SignalExport.dataChannel<0011>=DATA[11] +SignalExport.dataChannel<0012>=DATA[12] +SignalExport.dataChannel<0013>=DATA[13] +SignalExport.dataChannel<0014>=DATA[14] +SignalExport.dataChannel<0015>=DATA[15] +SignalExport.dataChannel<0016>=DATA[16] +SignalExport.dataChannel<0017>=DATA[17] +SignalExport.dataChannel<0018>=DATA[18] +SignalExport.dataChannel<0019>=DATA[19] +SignalExport.dataChannel<0020>=DATA[20] +SignalExport.dataChannel<0021>=DATA[21] +SignalExport.dataChannel<0022>=DATA[22] +SignalExport.dataChannel<0023>=DATA[23] +SignalExport.dataChannel<0024>=DATA[24] +SignalExport.dataChannel<0025>=DATA[25] +SignalExport.dataChannel<0026>=DATA[26] +SignalExport.dataChannel<0027>=DATA[27] +SignalExport.dataChannel<0028>=DATA[28] +SignalExport.dataChannel<0029>=DATA[29] +SignalExport.dataChannel<0030>=DATA[30] +SignalExport.dataChannel<0031>=DATA[31] +SignalExport.dataChannel<0032>=DATA[32] +SignalExport.dataChannel<0033>=DATA[33] +SignalExport.dataChannel<0034>=DATA[34] +SignalExport.dataChannel<0035>=DATA[35] +SignalExport.dataChannel<0036>=DATA[36] +SignalExport.dataChannel<0037>=DATA[37] +SignalExport.dataChannel<0038>=DATA[38] +SignalExport.dataChannel<0039>=DATA[39] +SignalExport.dataChannel<0040>=DATA[40] +SignalExport.dataChannel<0041>=DATA[41] +SignalExport.dataChannel<0042>=DATA[42] +SignalExport.dataChannel<0043>=DATA[43] +SignalExport.dataChannel<0044>=DATA[44] +SignalExport.dataChannel<0045>=DATA[45] +SignalExport.dataChannel<0046>=DATA[46] +SignalExport.dataChannel<0047>=DATA[47] +SignalExport.dataChannel<0048>=DATA[48] +SignalExport.dataChannel<0049>=DATA[49] +SignalExport.dataChannel<0050>=DATA[50] +SignalExport.dataChannel<0051>=DATA[51] +SignalExport.dataChannel<0052>=DATA[52] +SignalExport.dataChannel<0053>=DATA[53] +SignalExport.dataChannel<0054>=DATA[54] +SignalExport.dataChannel<0055>=DATA[55] +SignalExport.dataChannel<0056>=DATA[56] +SignalExport.dataChannel<0057>=DATA[57] +SignalExport.dataChannel<0058>=DATA[58] +SignalExport.dataChannel<0059>=DATA[59] +SignalExport.dataChannel<0060>=DATA[60] +SignalExport.dataChannel<0061>=DATA[61] +SignalExport.dataChannel<0062>=DATA[62] +SignalExport.dataChannel<0063>=DATA[63] +SignalExport.dataEqualsTrigger=false +SignalExport.dataPortWidth=64 +SignalExport.triggerChannel<0000><0000>=TRIG0[0] +SignalExport.triggerChannel<0000><0001>=TRIG0[1] +SignalExport.triggerChannel<0000><0002>=TRIG0[2] +SignalExport.triggerChannel<0000><0003>=TRIG0[3] +SignalExport.triggerChannel<0000><0004>=TRIG0[4] +SignalExport.triggerChannel<0000><0005>=TRIG0[5] +SignalExport.triggerChannel<0000><0006>=TRIG0[6] +SignalExport.triggerChannel<0000><0007>=TRIG0[7] +SignalExport.triggerPort<0000>.name=TRIG0 +SignalExport.triggerPortCount=1 +SignalExport.triggerPortIsData<0000>=false +SignalExport.triggerPortWidth<0000>=8 +SignalExport.type=ila + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.ucf b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.ucf new file mode 100644 index 000000000..e1ce12a9d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.ucf @@ -0,0 +1,17 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_b200_chipscope_ila = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; +NET "DATA<*" S; +NET "DATA<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.xdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.gise b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.gise new file mode 100644 index 000000000..991df1547 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.gise @@ -0,0 +1,31 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
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+ <!-- -->
+
+ <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
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+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
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diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ncf b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ncf new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ncf diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ngc b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ngc new file mode 100644 index 000000000..82baab030 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ucf b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ucf new file mode 100644 index 000000000..e1ce12a9d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ucf @@ -0,0 +1,17 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_b200_chipscope_ila = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; +NET "DATA<*" S; +NET "DATA<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.v b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.v new file mode 100644 index 000000000..a9abb90e8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.v @@ -0,0 +1,33 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : b200_chipscope_ila.v +// /___/ /\ Timestamp : Tue Feb 19 16:52:47 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: Verilog Synthesis Wrapper +/////////////////////////////////////////////////////////////////////////////// +// This wrapper is used to integrate with Project Navigator and PlanAhead + +`timescale 1ns/1ps + +module b200_chipscope_ila( + CONTROL, + CLK, + DATA, + TRIG0) /* synthesis syn_black_box syn_noprune=1 */; + + +inout [35 : 0] CONTROL; +input CLK; +input [63 : 0] DATA; +input [7 : 0] TRIG0; + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.veo b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.veo new file mode 100644 index 000000000..f72d6853c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.veo @@ -0,0 +1,31 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : b200_chipscope_ila.veo +// /___/ /\ Timestamp : Tue Feb 19 16:52:47 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: ISE Instantiation template +/////////////////////////////////////////////////////////////////////////////// + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +b200_chipscope_ila YourInstanceName ( + .CONTROL(CONTROL), // INOUT BUS [35:0] + .CLK(CLK), // IN + .DATA(DATA), // IN BUS [63:0] + .TRIG0(TRIG0) // IN BUS [7:0] +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xco b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xco new file mode 100644 index 000000000..ecae96127 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xco @@ -0,0 +1,141 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Wed Feb 20 00:50:54 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a +# END Select +# BEGIN Parameters +CSET check_bramcount=false +CSET component_name=b200_chipscope_ila +CSET constraint_type=external +CSET counter_width_1=Disabled +CSET counter_width_10=Disabled +CSET counter_width_11=Disabled +CSET counter_width_12=Disabled +CSET counter_width_13=Disabled +CSET counter_width_14=Disabled +CSET counter_width_15=Disabled +CSET counter_width_16=Disabled +CSET counter_width_2=Disabled +CSET counter_width_3=Disabled +CSET counter_width_4=Disabled +CSET counter_width_5=Disabled +CSET counter_width_6=Disabled +CSET counter_width_7=Disabled +CSET counter_width_8=Disabled +CSET counter_width_9=Disabled +CSET data_port_width=64 +CSET data_same_as_trigger=false +CSET disable_save_keep=false +CSET enable_storage_qualification=true +CSET enable_trigger_output_port=false +CSET example_design=false +CSET exclude_from_data_storage_1=true +CSET exclude_from_data_storage_10=true +CSET exclude_from_data_storage_11=true +CSET exclude_from_data_storage_12=true +CSET exclude_from_data_storage_13=true +CSET exclude_from_data_storage_14=true +CSET exclude_from_data_storage_15=true +CSET exclude_from_data_storage_16=true +CSET exclude_from_data_storage_2=true +CSET exclude_from_data_storage_3=true +CSET exclude_from_data_storage_4=true +CSET exclude_from_data_storage_5=true +CSET exclude_from_data_storage_6=true +CSET exclude_from_data_storage_7=true +CSET exclude_from_data_storage_8=true +CSET exclude_from_data_storage_9=true +CSET match_type_1=basic_with_edges +CSET match_type_10=basic_with_edges +CSET match_type_11=basic_with_edges +CSET match_type_12=basic_with_edges +CSET match_type_13=basic_with_edges +CSET match_type_14=basic_with_edges +CSET match_type_15=basic_with_edges +CSET match_type_16=basic_with_edges +CSET match_type_2=basic_with_edges +CSET match_type_3=basic_with_edges +CSET match_type_4=basic_with_edges +CSET match_type_5=basic_with_edges +CSET match_type_6=basic_with_edges +CSET match_type_7=basic_with_edges +CSET match_type_8=basic_with_edges +CSET match_type_9=basic_with_edges +CSET match_units_1=1 +CSET match_units_10=1 +CSET match_units_11=1 +CSET match_units_12=1 +CSET match_units_13=1 +CSET match_units_14=1 +CSET match_units_15=1 +CSET match_units_16=1 +CSET match_units_2=1 +CSET match_units_3=1 +CSET match_units_4=1 +CSET match_units_5=1 +CSET match_units_6=1 +CSET match_units_7=1 +CSET match_units_8=1 +CSET match_units_9=1 +CSET max_sequence_levels=1 +CSET number_of_trigger_ports=1 +CSET sample_data_depth=8192 +CSET sample_on=Rising +CSET trigger_port_width_1=8 +CSET trigger_port_width_10=8 +CSET trigger_port_width_11=8 +CSET trigger_port_width_12=8 +CSET trigger_port_width_13=8 +CSET trigger_port_width_14=8 +CSET trigger_port_width_15=8 +CSET trigger_port_width_16=8 +CSET trigger_port_width_2=8 +CSET trigger_port_width_3=8 +CSET trigger_port_width_4=8 +CSET trigger_port_width_5=8 +CSET trigger_port_width_6=8 +CSET trigger_port_width_7=8 +CSET trigger_port_width_8=8 +CSET trigger_port_width_9=8 +CSET use_rpms=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T02:47:40Z +# END Extra information +GENERATE +# CRC: 92d75d38 diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xise b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xise new file mode 100644 index 000000000..2f85bcdc4 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xise @@ -0,0 +1,73 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="b200_chipscope_ila.ngc" xil_pn:type="FILE_NGC"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="b200_chipscope_ila.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/> + </file> + </files> + + <properties> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> + <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Module|b200_chipscope_ila" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top File" xil_pn:value="b200_chipscope_ila.ngc" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/b200_chipscope_ila" xil_pn:valueState="non-default"/> + <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_DesignName" xil_pn:value="b200_chipscope_ila" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-02-19T16:52:50" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1246592F65CAF06BF6A1D464FDE11DBE" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_flist.txt b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_flist.txt new file mode 100644 index 000000000..4dfd1b082 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_flist.txt @@ -0,0 +1,18 @@ +# Output products list for <b200_chipscope_ila> +_xmsgs/pn_parser.xmsgs +b200_chipscope_ila.asy +b200_chipscope_ila.cdc +b200_chipscope_ila.constraints/b200_chipscope_ila.ucf +b200_chipscope_ila.constraints/b200_chipscope_ila.xdc +b200_chipscope_ila.gise +b200_chipscope_ila.ncf +b200_chipscope_ila.ngc +b200_chipscope_ila.ucf +b200_chipscope_ila.v +b200_chipscope_ila.veo +b200_chipscope_ila.xco +b200_chipscope_ila.xdc +b200_chipscope_ila.xise +b200_chipscope_ila_flist.txt +b200_chipscope_ila_readme.txt +b200_chipscope_ila_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_readme.txt b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_readme.txt new file mode 100644 index 000000000..28176abfb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_readme.txt @@ -0,0 +1,48 @@ +The following files were generated for 'b200_chipscope_ila' in directory +/home/bhilburn/code/ettus/b200_dev/fpgapriv.git/usrp3/top/b200/coregen/ + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * b200_chipscope_ila.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * b200_chipscope_ila.cdc + * b200_chipscope_ila.constraints/b200_chipscope_ila.ucf + * b200_chipscope_ila.constraints/b200_chipscope_ila.xdc + * b200_chipscope_ila.ncf + * b200_chipscope_ila.ngc + * b200_chipscope_ila.ucf + * b200_chipscope_ila.v + * b200_chipscope_ila.veo + * b200_chipscope_ila.xdc + * b200_chipscope_ila_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * b200_chipscope_ila.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * _xmsgs/pn_parser.xmsgs + * b200_chipscope_ila.gise + * b200_chipscope_ila.xise + +Deliver Readme: + Readme file for the IP. + + * b200_chipscope_ila_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * b200_chipscope_ila_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_xmdf.tcl b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_xmdf.tcl new file mode 100755 index 000000000..a0922f3ec --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_xmdf.tcl @@ -0,0 +1,87 @@ +# The package naming convention is <core_name>_xmdf +package provide b200_chipscope_ila_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is <core_name>_xmdf +namespace eval ::b200_chipscope_ila_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::b200_chipscope_ila_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: <module_name> +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_chipscope_ila +} +# ::b200_chipscope_ila_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::b200_chipscope_ila_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.cdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.constraints/b200_chipscope_ila.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.constraints/b200_chipscope_ila.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_chipscope_ila +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.asy b/fpga/usrp3/top/b200/coregen/b200_clk_gen.asy new file mode 100644 index 000000000..aad58f8d2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.asy @@ -0,0 +1,33 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 b200_clk_gen +RECTANGLE Normal 32 32 576 1088 +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName clk_in1_p +PINATTR Polarity IN +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName clk_in1_n +PINATTR Polarity IN +LINE Normal 0 432 32 432 +PIN 0 432 LEFT 36 +PINATTR PinName reset +PINATTR Polarity IN +LINE Normal 608 80 576 80 +PIN 608 80 RIGHT 36 +PINATTR PinName clk_out1 +PINATTR Polarity OUT +LINE Normal 608 176 576 176 +PIN 608 176 RIGHT 36 +PINATTR PinName clk_out2 +PINATTR Polarity OUT +LINE Normal 608 272 576 272 +PIN 608 272 RIGHT 36 +PINATTR PinName clk_out3 +PINATTR Polarity OUT +LINE Normal 608 976 576 976 +PIN 608 976 RIGHT 36 +PINATTR PinName locked +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.gise b/fpga/usrp3/top/b200/coregen/b200_clk_gen.gise new file mode 100644 index 000000000..70064d04f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.gise @@ -0,0 +1,31 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="b200_clk_gen.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="b200_clk_gen.asy" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="b200_clk_gen.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.ucf b/fpga/usrp3/top/b200/coregen/b200_clk_gen.ucf new file mode 100755 index 000000000..e3776c72b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.ucf @@ -0,0 +1,72 @@ +# file: b200_clk_gen.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +# Differential clock only needs one constraint +NET "CLK_IN1_P" TNM_NET = "CLK_IN1_P"; +TIMESPEC "TS_CLK_IN1_P" = PERIOD "CLK_IN1_P" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps; + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- +# NET "clk_int[1]" TNM_NET = "CLK_OUT1"; +# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 40.000 MHz; + +# NET "clk_int[2]" TNM_NET = "CLK_OUT2"; +# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 100.000 MHz; +# NET "clk_int[3]" TNM_NET = "CLK_OUT3"; +# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 100.000 MHz; + +# FALSE PATH constraints +PIN "RESET" TIG; + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.v b/fpga/usrp3/top/b200/coregen/b200_clk_gen.v new file mode 100755 index 000000000..bb9a57dc2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.v @@ -0,0 +1,163 @@ +// file: b200_clk_gen.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// "Output Output Phase Duty Pk-to-Pk Phase" +// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +//---------------------------------------------------------------------------- +// CLK_OUT1____40.000______0.000______50.0______200.000____150.000 +// CLK_OUT2___100.000______0.000______50.0______400.000____150.000 +// CLK_OUT3___100.000______0.000______50.0______400.000____150.000 +// +//---------------------------------------------------------------------------- +// "Input Clock Freq (MHz) Input Jitter (UI)" +//---------------------------------------------------------------------------- +// __primary__________40.000____________0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "b200_clk_gen,clk_wiz_v3_6,{component_name=b200_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=25.0,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *) +module b200_clk_gen + (// Clock in ports + input CLK_IN1_40_P, + input CLK_IN1_40_N, + // Clock out ports + output CLK_OUT1_40_int, + output CLK_OUT2_100_gpif, + output CLK_OUT3_100_bus, + // Status and control signals + input RESET, + output LOCKED + ); + + // Input buffering + //------------------------------------ + IBUFGDS clkin1_buf + (.O (clkin1), + .I (CLK_IN1_40_P), + .IB (CLK_IN1_40_N)); + + + // Clocking primitive + //------------------------------------ + + // Instantiation of the DCM primitive + // * Unused inputs are tied off + // * Unused outputs are labeled unused + wire psdone_unused; + wire locked_int; + wire [7:0] status_int; + wire clkfb; + wire clk0; + wire clkfx; + + DCM_SP + #(.CLKDV_DIVIDE (2.000), + .CLKFX_DIVIDE (2), + .CLKFX_MULTIPLY (5), + .CLKIN_DIVIDE_BY_2 ("FALSE"), + .CLKIN_PERIOD (25.0), + .CLKOUT_PHASE_SHIFT ("NONE"), + .CLK_FEEDBACK ("1X"), + .DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"), + .PHASE_SHIFT (0), + .STARTUP_WAIT ("FALSE")) + dcm_sp_inst + // Input clock + (.CLKIN (clkin1), + .CLKFB (clkfb), + // Output clocks + .CLK0 (clk0), + .CLK90 (), + .CLK180 (), + .CLK270 (), + .CLK2X (), + .CLK2X180 (), + .CLKFX (clkfx), + .CLKFX180 (), + .CLKDV (), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (locked_int), + .STATUS (status_int), + + .RST (RESET), + // Unused pin- tie low + .DSSEN (1'b0)); + + assign LOCKED = locked_int; + + // Output buffering + //----------------------------------- + assign clkfb = CLK_OUT1_40_int; + + BUFG clkout1_buf + (.O (CLK_OUT1_40_int), + .I (clk0)); + + + BUFG clkout2_buf + (.O (CLK_OUT2_100_gpif), + .I (clkfx)); + + BUFG clkout3_buf + (.O (CLK_OUT3_100_bus), + .I (clkfx)); + + + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.veo b/fpga/usrp3/top/b200/coregen/b200_clk_gen.veo new file mode 100755 index 000000000..111c02991 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.veo @@ -0,0 +1,83 @@ +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// "Output Output Phase Duty Pk-to-Pk Phase" +// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +//---------------------------------------------------------------------------- +// CLK_OUT1____40.000______0.000______50.0______200.000____150.000 +// CLK_OUT2___100.000______0.000______50.0______400.000____150.000 +// CLK_OUT3___100.000______0.000______50.0______400.000____150.000 +// +//---------------------------------------------------------------------------- +// "Input Clock Freq (MHz) Input Jitter (UI)" +//---------------------------------------------------------------------------- +// __primary__________40.000____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + b200_clk_gen instance_name + (// Clock in ports + .CLK_IN1_40_P(CLK_IN1_40_P), // IN + .CLK_IN1_40_N(CLK_IN1_40_N), // IN + // Clock out ports + .CLK_OUT1_40_int(CLK_OUT1_40_int), // OUT + .CLK_OUT2_100_gpif(CLK_OUT2_100_gpif), // OUT + .CLK_OUT3_100_bus(CLK_OUT3_100_bus), // OUT + // Status and control signals + .RESET(RESET),// IN + .LOCKED(LOCKED)); // OUT +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.xco b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xco new file mode 100644 index 000000000..96c8193b3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xco @@ -0,0 +1,269 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Fri Jan 25 20:00:48 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:clk_wiz:3.6 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 +# END Select +# BEGIN Parameters +CSET calc_done=DONE +CSET clk_in_sel_port=CLK_IN_SEL +CSET clk_out1_port=CLK_OUT1_40_int +CSET clk_out1_use_fine_ps_gui=false +CSET clk_out2_port=CLK_OUT2_100_gpif +CSET clk_out2_use_fine_ps_gui=false +CSET clk_out3_port=CLK_OUT3_100_bus +CSET clk_out3_use_fine_ps_gui=false +CSET clk_out4_port=CLK_OUT4 +CSET clk_out4_use_fine_ps_gui=false +CSET clk_out5_port=CLK_OUT5 +CSET clk_out5_use_fine_ps_gui=false +CSET clk_out6_port=CLK_OUT6 +CSET clk_out6_use_fine_ps_gui=false +CSET clk_out7_port=CLK_OUT7 +CSET clk_out7_use_fine_ps_gui=false +CSET clk_valid_port=CLK_VALID +CSET clkfb_in_n_port=CLKFB_IN_N +CSET clkfb_in_p_port=CLKFB_IN_P +CSET clkfb_in_port=CLKFB_IN +CSET clkfb_in_signaling=SINGLE +CSET clkfb_out_n_port=CLKFB_OUT_N +CSET clkfb_out_p_port=CLKFB_OUT_P +CSET clkfb_out_port=CLKFB_OUT +CSET clkfb_stopped_port=CLKFB_STOPPED +CSET clkin1_jitter_ps=250.0 +CSET clkin1_ui_jitter=0.010 +CSET clkin2_jitter_ps=100.0 +CSET clkin2_ui_jitter=0.010 +CSET clkout1_drives=BUFG +CSET clkout1_requested_duty_cycle=50.000 +CSET clkout1_requested_out_freq=40.000 +CSET clkout1_requested_phase=0.000 +CSET clkout2_drives=BUFG +CSET clkout2_requested_duty_cycle=50.000 +CSET clkout2_requested_out_freq=100.000 +CSET clkout2_requested_phase=0.000 +CSET clkout2_used=true +CSET clkout3_drives=BUFG +CSET clkout3_requested_duty_cycle=50.000 +CSET clkout3_requested_out_freq=100.000 +CSET clkout3_requested_phase=0.000 +CSET clkout3_used=true +CSET clkout4_drives=BUFG +CSET clkout4_requested_duty_cycle=50.000 +CSET clkout4_requested_out_freq=100.000 +CSET clkout4_requested_phase=0.000 +CSET clkout4_used=false +CSET clkout5_drives=BUFG +CSET clkout5_requested_duty_cycle=50.000 +CSET clkout5_requested_out_freq=100.000 +CSET clkout5_requested_phase=0.000 +CSET clkout5_used=false +CSET clkout6_drives=BUFG +CSET clkout6_requested_duty_cycle=50.000 +CSET clkout6_requested_out_freq=100.000 +CSET clkout6_requested_phase=0.000 +CSET clkout6_used=false +CSET clkout7_drives=BUFG +CSET clkout7_requested_duty_cycle=50.000 +CSET clkout7_requested_out_freq=100.000 +CSET clkout7_requested_phase=0.000 +CSET clkout7_used=false +CSET clock_mgr_type=AUTO +CSET component_name=b200_clk_gen +CSET daddr_port=DADDR +CSET dclk_port=DCLK +CSET dcm_clk_feedback=1X +CSET dcm_clk_out1_port=CLK0 +CSET dcm_clk_out2_port=CLKFX +CSET dcm_clk_out3_port=CLKFX +CSET dcm_clk_out4_port=CLK0 +CSET dcm_clk_out5_port=CLK0 +CSET dcm_clk_out6_port=CLK0 +CSET dcm_clkdv_divide=2.0 +CSET dcm_clkfx_divide=2 +CSET dcm_clkfx_multiply=5 +CSET dcm_clkgen_clk_out1_port=CLKFX +CSET dcm_clkgen_clk_out2_port=CLKFX +CSET dcm_clkgen_clk_out3_port=CLKFX +CSET dcm_clkgen_clkfx_divide=1 +CSET dcm_clkgen_clkfx_md_max=0.000 +CSET dcm_clkgen_clkfx_multiply=4 +CSET dcm_clkgen_clkfxdv_divide=2 +CSET dcm_clkgen_clkin_period=10.000 +CSET dcm_clkgen_notes=None +CSET dcm_clkgen_spread_spectrum=NONE +CSET dcm_clkgen_startup_wait=false +CSET dcm_clkin_divide_by_2=false +CSET dcm_clkin_period=25.000 +CSET dcm_clkout_phase_shift=NONE +CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS +CSET dcm_notes=None +CSET dcm_phase_shift=0 +CSET dcm_pll_cascade=NONE +CSET dcm_startup_wait=false +CSET den_port=DEN +CSET din_port=DIN +CSET dout_port=DOUT +CSET drdy_port=DRDY +CSET dwe_port=DWE +CSET feedback_source=FDBK_AUTO +CSET in_freq_units=Units_MHz +CSET in_jitter_units=Units_UI +CSET input_clk_stopped_port=INPUT_CLK_STOPPED +CSET jitter_options=UI +CSET jitter_sel=No_Jitter +CSET locked_port=LOCKED +CSET mmcm_bandwidth=OPTIMIZED +CSET mmcm_clkfbout_mult_f=4.000 +CSET mmcm_clkfbout_phase=0.000 +CSET mmcm_clkfbout_use_fine_ps=false +CSET mmcm_clkin1_period=10.000 +CSET mmcm_clkin2_period=10.000 +CSET mmcm_clkout0_divide_f=4.000 +CSET mmcm_clkout0_duty_cycle=0.500 +CSET mmcm_clkout0_phase=0.000 +CSET mmcm_clkout0_use_fine_ps=false +CSET mmcm_clkout1_divide=1 +CSET mmcm_clkout1_duty_cycle=0.500 +CSET mmcm_clkout1_phase=0.000 +CSET mmcm_clkout1_use_fine_ps=false +CSET mmcm_clkout2_divide=1 +CSET mmcm_clkout2_duty_cycle=0.500 +CSET mmcm_clkout2_phase=0.000 +CSET mmcm_clkout2_use_fine_ps=false +CSET mmcm_clkout3_divide=1 +CSET mmcm_clkout3_duty_cycle=0.500 +CSET mmcm_clkout3_phase=0.000 +CSET mmcm_clkout3_use_fine_ps=false +CSET mmcm_clkout4_cascade=false +CSET mmcm_clkout4_divide=1 +CSET mmcm_clkout4_duty_cycle=0.500 +CSET mmcm_clkout4_phase=0.000 +CSET mmcm_clkout4_use_fine_ps=false +CSET mmcm_clkout5_divide=1 +CSET mmcm_clkout5_duty_cycle=0.500 +CSET mmcm_clkout5_phase=0.000 +CSET mmcm_clkout5_use_fine_ps=false +CSET mmcm_clkout6_divide=1 +CSET mmcm_clkout6_duty_cycle=0.500 +CSET mmcm_clkout6_phase=0.000 +CSET mmcm_clkout6_use_fine_ps=false +CSET mmcm_clock_hold=false +CSET mmcm_compensation=ZHOLD +CSET mmcm_divclk_divide=1 +CSET mmcm_notes=None +CSET mmcm_ref_jitter1=0.010 +CSET mmcm_ref_jitter2=0.010 +CSET mmcm_startup_wait=false +CSET num_out_clks=3 +CSET override_dcm=false +CSET override_dcm_clkgen=false +CSET override_mmcm=false +CSET override_pll=false +CSET platform=lin64 +CSET pll_bandwidth=OPTIMIZED +CSET pll_clk_feedback=CLKFBOUT +CSET pll_clkfbout_mult=4 +CSET pll_clkfbout_phase=0.000 +CSET pll_clkin_period=10.000 +CSET pll_clkout0_divide=1 +CSET pll_clkout0_duty_cycle=0.500 +CSET pll_clkout0_phase=0.000 +CSET pll_clkout1_divide=1 +CSET pll_clkout1_duty_cycle=0.500 +CSET pll_clkout1_phase=0.000 +CSET pll_clkout2_divide=1 +CSET pll_clkout2_duty_cycle=0.500 +CSET pll_clkout2_phase=0.000 +CSET pll_clkout3_divide=1 +CSET pll_clkout3_duty_cycle=0.500 +CSET pll_clkout3_phase=0.000 +CSET pll_clkout4_divide=1 +CSET pll_clkout4_duty_cycle=0.500 +CSET pll_clkout4_phase=0.000 +CSET pll_clkout5_divide=1 +CSET pll_clkout5_duty_cycle=0.500 +CSET pll_clkout5_phase=0.000 +CSET pll_compensation=SYSTEM_SYNCHRONOUS +CSET pll_divclk_divide=1 +CSET pll_notes=None +CSET pll_ref_jitter=0.010 +CSET power_down_port=POWER_DOWN +CSET prim_in_freq=40.000 +CSET prim_in_jitter=0.010 +CSET prim_source=Differential_clock_capable_pin +CSET primary_port=CLK_IN1_40 +CSET primitive=MMCM +CSET primtype_sel=PLL_BASE +CSET psclk_port=PSCLK +CSET psdone_port=PSDONE +CSET psen_port=PSEN +CSET psincdec_port=PSINCDEC +CSET relative_inclk=REL_PRIMARY +CSET reset_port=RESET +CSET secondary_in_freq=100.000 +CSET secondary_in_jitter=0.010 +CSET secondary_port=CLK_IN2 +CSET secondary_source=Single_ended_clock_capable_pin +CSET ss_mod_freq=250 +CSET ss_mode=CENTER_HIGH +CSET status_port=STATUS +CSET summary_strings=empty +CSET use_clk_valid=false +CSET use_clkfb_stopped=false +CSET use_dyn_phase_shift=false +CSET use_dyn_reconfig=false +CSET use_freeze=false +CSET use_freq_synth=true +CSET use_inclk_stopped=false +CSET use_inclk_switchover=false +CSET use_locked=true +CSET use_max_i_jitter=false +CSET use_min_o_jitter=false +CSET use_min_power=false +CSET use_phase_alignment=true +CSET use_power_down=false +CSET use_reset=true +CSET use_spread_spectrum=false +CSET use_spread_spectrum_1=false +CSET use_status=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-05-10T12:44:55Z +# END Extra information +GENERATE +# CRC: af7323ea diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.xdc b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xdc new file mode 100755 index 000000000..d57c7eec7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xdc @@ -0,0 +1,68 @@ +# file: b200_clk_gen.xdc +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +# Differential clock only needs one constraint +create_clock -name CLK_IN1_P -period 25.0 [get_ports CLK_IN1_P] +set_propagated_clock CLK_IN1_P +set_input_jitter CLK_IN1_P 0.25 + +set_false_path -from [get_ports "RESET"] + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- + +#----------------------------------------------------------------- + +#----------------------------------------------------------------- diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.xise b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xise new file mode 100644 index 000000000..0c90c5973 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xise @@ -0,0 +1,408 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="b200_clk_gen/example_design/b200_clk_gen_exdes.ucf" xil_pn:type="FILE_UCF"> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="b200_clk_gen/example_design/b200_clk_gen_exdes.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="2"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/> + </file> + <file xil_pn:name="b200_clk_gen.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="Implementation" xil_pn:seqID="4"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/> + </file> + </files> + + <properties> + <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/> + <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/> + <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> + <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> + <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> + <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/> + <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/> + <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/> + <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/> + <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> + <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/> + <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> + <property xil_pn:name="Drive Awake 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xil_pn:valueState="default"/> + <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> + <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> + <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/> + <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/> + <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> + <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> + <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> + <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> + <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/> + <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/> + <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/> + <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> + <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> + <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/> + <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/> + <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/> + <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/> + <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> + <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> + <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> + <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> + <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> + <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/> + <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/> + <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> + <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> + <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> + <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/> + <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> + <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/> + <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/> + <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_DesignName" xil_pn:value="b200_clk_gen" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-01-25T12:01:05" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BF4ABAECC95F189A3B1A35E026FF9799" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/clk_wiz_v3_6_readme.txt b/fpga/usrp3/top/b200/coregen/b200_clk_gen/clk_wiz_v3_6_readme.txt new file mode 100644 index 000000000..19c5b73c6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/clk_wiz_v3_6_readme.txt @@ -0,0 +1,181 @@ +CHANGE LOG for LogiCORE Clocking Wizard V3.6 + + Release Date: July 25, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ + +................................................................................ + +2. DEVICE SUPPORT + + + 2.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - Spread Spectrum support for 7 series MMCME2 + + - ISE 14.2 software support + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + Resolved issue with Virtex6 MMCM instantiation for VHDL project + Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +................................................................................ + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support +07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_readme.txt b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_readme.txt new file mode 100644 index 000000000..19c5b73c6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_readme.txt @@ -0,0 +1,181 @@ +CHANGE LOG for LogiCORE Clocking Wizard V3.6 + + Release Date: July 25, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ + +................................................................................ + +2. DEVICE SUPPORT + + + 2.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - Spread Spectrum support for 7 series MMCME2 + + - ISE 14.2 software support + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + Resolved issue with Virtex6 MMCM instantiation for VHDL project + Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +................................................................................ + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support +07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html new file mode 100644 index 000000000..7176ddb81 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html @@ -0,0 +1,192 @@ +<HTML> +<HEAD> +<TITLE>clk_wiz_v3_6_vinfo</TITLE> +<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1"> +</HEAD> +<BODY> +<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1"> +CHANGE LOG for LogiCORE Clocking Wizard V3.6 + + Release Date: July 25, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A> + +For system requirements: + + <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A> + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 +solution. For the latest core updates, see the product page at: + + <A HREF="http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/">www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/</A> + +................................................................................ + +2. DEVICE SUPPORT + + + 2.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - Spread Spectrum support for 7 series MMCME2 + + - ISE 14.2 software support + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + Resolved issue with Virtex6 MMCM instantiation for VHDL project + Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A> + + +................................................................................ + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A> +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support +07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + +</FONT> +</PRE> +</BODY> +</HTML> diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/pg065_clk_wiz.pdf b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/pg065_clk_wiz.pdf Binary files differnew file mode 100644 index 000000000..a7daa6089 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/pg065_clk_wiz.pdf diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.ucf b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.ucf new file mode 100755 index 000000000..62c243978 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.ucf @@ -0,0 +1,73 @@ +# file: b200_clk_gen_exdes.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +# Differential clock only needs one constraint +NET "CLK_IN1_P" TNM_NET = "CLK_IN1_P"; +TIMESPEC "TS_CLK_IN1_P" = PERIOD "CLK_IN1_P" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps; + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- +# NET "clk_int[1]" TNM_NET = "CLK_OUT1"; +# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 40.000 MHz; + +# NET "clk_int[2]" TNM_NET = "CLK_OUT2"; +# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 100.000 MHz; +# NET "clk_int[3]" TNM_NET = "CLK_OUT3"; +# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 100.000 MHz; + +# FALSE PATH constraints +PIN "COUNTER_RESET" TIG; +PIN "RESET" TIG; + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.v b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.v new file mode 100755 index 000000000..e22b83072 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.v @@ -0,0 +1,180 @@ +// file: b200_clk_gen_exdes.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard example design +//---------------------------------------------------------------------------- +// This example design instantiates the created clocking network, where each +// output clock drives a counter. The high bit of each counter is ported. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +module b200_clk_gen_exdes + #( + parameter TCQ = 100 + ) + (// Clock in ports + input CLK_IN1_P, + input CLK_IN1_N, + // Reset that only drives logic in example design + input COUNTER_RESET, + output [3:1] CLK_OUT, + // High bits of counters driven by clocks + output [3:1] COUNT, + // Status and control signals + input RESET, + output LOCKED + ); + + // Parameters for the counters + //------------------------------- + // Counter width + localparam C_W = 16; + // Number of counters + localparam NUM_C = 3; + genvar count_gen; + // When the clock goes out of lock, reset the counters + wire reset_int = !LOCKED || RESET || COUNTER_RESET; + + reg [NUM_C:1] rst_sync; + reg [NUM_C:1] rst_sync_int; + reg [NUM_C:1] rst_sync_int1; + reg [NUM_C:1] rst_sync_int2; + + + // Declare the clocks and counters + wire [NUM_C:1] clk_int; + wire [NUM_C:1] clk_n; + wire [NUM_C:1] clk; + reg [C_W-1:0] counter [NUM_C:1]; + + // Instantiation of the clocking network + //-------------------------------------- + b200_clk_gen clknetwork + (// Clock in ports + .CLK_IN1_40_P (CLK_IN1_P), + .CLK_IN1_40_N (CLK_IN1_N), + // Clock out ports + .CLK_OUT1_40_int (clk_int[1]), + .CLK_OUT2_100_gpif (clk_int[2]), + .CLK_OUT3_100_bus (clk_int[3]), + // Status and control signals + .RESET (RESET), + .LOCKED (LOCKED)); + +genvar clk_out_pins; + +generate + for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1) + begin: gen_outclk_oddr + assign clk_n[clk_out_pins] = ~clk[clk_out_pins]; + + ODDR2 clkout_oddr + (.Q (CLK_OUT[clk_out_pins1]), + .C0 (clk[clk_out_pins]), + .C1 (clk_n[clk_out_pins]), + .CE (1'b1), + .D0 (1'b1), + .D1 (1'b0), + .R (1'b0), + .S (1'b0)); + end +endgenerate + + // Connect the output clocks to the design + //----------------------------------------- + assign clk[1] = clk_int[1]; + assign clk[2] = clk_int[2]; + assign clk[3] = clk_int[3]; + + + // Reset synchronizer + //----------------------------------- + generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1 + always @(posedge reset_int or posedge clk[count_gen]) begin + if (reset_int) begin + rst_sync[count_gen] <= 1'b1; + rst_sync_int[count_gen]<= 1'b1; + rst_sync_int1[count_gen]<= 1'b1; + rst_sync_int2[count_gen]<= 1'b1; + end + else begin + rst_sync[count_gen] <= 1'b0; + rst_sync_int[count_gen] <= rst_sync[count_gen]; + rst_sync_int1[count_gen] <= rst_sync_int[count_gen]; + rst_sync_int2[count_gen] <= rst_sync_int1[count_gen]; + end + end + end + endgenerate + + + // Output clock sampling + //----------------------------------- + generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters + + always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin + if (rst_sync_int2[count_gen]) begin + counter[count_gen] <= #TCQ { C_W { 1'b 0 } }; + end else begin + counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1; + end + end + // alias the high bit of each counter to the corresponding + // bit in the output bus + assign COUNT[count_gen] = counter[count_gen][C_W-1]; + end + endgenerate + + + + + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.xdc b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.xdc new file mode 100755 index 000000000..dc0aad84c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.xdc @@ -0,0 +1,70 @@ +# file: b200_clk_gen_exdes.xdc +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +# Differential clock only needs one constraint +create_clock -name CLK_IN1_P -period 25.0 [get_ports CLK_IN1_P] +set_propagated_clock CLK_IN1_P +set_input_jitter CLK_IN1_P 0.25 + +# FALSE PATH constraint added on COUNTER_RESET +set_false_path -from [get_ports "COUNTER_RESET"] +set_false_path -from [get_ports "RESET"] + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- + +#----------------------------------------------------------------- + +#----------------------------------------------------------------- diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.bat new file mode 100755 index 000000000..32e315065 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.bat @@ -0,0 +1,90 @@ +REM file: implement.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM ----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the clocking wizard +REM ----------------------------------------------------------------------------- + +REM Clean up the results directory +rmdir /S /Q results +mkdir results + +REM Copy unisim_comp.v file to results directory +copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\ + +REM Synthesize the Verilog Wrapper Files +echo 'Synthesizing Clocking Wizard design with XST' +xst -ifn xst.scr +move b200_clk_gen_exdes.ngc results\ + +REM Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\b200_clk_gen_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' +ngdbuild -uc b200_clk_gen_exdes.ucf b200_clk_gen_exdes + +echo 'Running map' +map -timing -pr b b200_clk_gen_exdes -o mapped.ncd + +echo 'Running par' +par -w mapped.ncd routed mapped.pcf + +echo 'Running trce' +trce -e 10 routed -o routed mapped.pcf + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level model for the clocking wizard example design' +netgen -ofmt verilog -sim -sdf_anno false -tm b200_clk_gen_exdes -w routed.ncd routed.v +cd .. + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.sh new file mode 100755 index 000000000..d33e6c5f5 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.sh @@ -0,0 +1,91 @@ +#!/bin/sh +# file: implement.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the clocking wizard +#----------------------------------------------------------------------------- + +# Clean up the results directory +rm -rf results +mkdir results + +# Copy unisim_comp.v file to results directory +cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/ + +# Synthesize the Verilog Wrapper Files +echo 'Synthesizing Clocking Wizard design with XST' +xst -ifn xst.scr +mv b200_clk_gen_exdes.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/b200_clk_gen_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' +ngdbuild -uc b200_clk_gen_exdes.ucf b200_clk_gen_exdes + +echo 'Running map' +map -timing b200_clk_gen_exdes -o mapped.ncd + +echo 'Running par' +par -w mapped.ncd routed mapped.pcf + +echo 'Running trce' +trce -e 10 routed -o routed mapped.pcf + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level model for the clocking wizard example design' +netgen -ofmt verilog -sim -sdf_anno false -tm b200_clk_gen_exdes -w routed.ncd routed.v + +cd .. diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.bat new file mode 100755 index 000000000..8ac771810 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.bat @@ -0,0 +1,58 @@ +REM file: planAhead_ise.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the clocking wizard +REM----------------------------------------------------------------------------- + +del \f results +mkdir results +cd results + +planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.sh new file mode 100755 index 000000000..6c8c837d3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.sh @@ -0,0 +1,59 @@ +#!/bin/sh +# file: planAhead_ise.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the clocking wizard +#----------------------------------------------------------------------------- + +rm -rf results +mkdir results +cd results + +planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.tcl new file mode 100755 index 000000000..b87b6e4d5 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.tcl @@ -0,0 +1,78 @@ +# file: planAhead_ise.tcl +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +set projDir [file dirname [info script]] +set projName b200_clk_gen +set topName b200_clk_gen_exdes +set device xc6slx75csg484-2 + +create_project $projName $projDir/results/$projName -part $device + +set_property design_mode RTL [get_filesets sources_1] + +## Source files +#set verilogSources [glob $srcDir/*.v] +import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/b200_clk_gen_exdes.v +import_files -fileset [get_filesets sources_1] -force -norecurse ../../../b200_clk_gen.v + + +#UCF file +import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/b200_clk_gen_exdes.ucf + +set_property top $topName [get_property srcset [current_run]] + +launch_runs -runs synth_1 +wait_on_run synth_1 + +set_property add_step Bitgen [get_runs impl_1] +launch_runs -runs impl_1 +wait_on_run impl_1 + + + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.bat new file mode 100755 index 000000000..42273f5d4 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.bat @@ -0,0 +1,58 @@ +REM file: planAhead_rdn.sh +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the XADC wizard +REM----------------------------------------------------------------------------- + +del \f results +mkdir results +cd results + +planAhead -mode batch -source ..\planAhead_rdn.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.sh new file mode 100755 index 000000000..f4c14729e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.sh @@ -0,0 +1,57 @@ +#!/bin/sh +# file: planAhead_rdn.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the XADC wizard +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +planAhead -mode batch -source ../planAhead_rdn.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.tcl new file mode 100755 index 000000000..5449fa5fb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.tcl @@ -0,0 +1,69 @@ +# file : planAhead_rdn.tcl +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +set device xc6slx75csg484-2 +set projName b200_clk_gen +set design b200_clk_gen +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module b200_clk_gen_exdes +set_property top b200_clk_gen_exdes [get_property srcset [current_run]] +add_files -norecurse {../../../b200_clk_gen.v} +add_files -norecurse {../../example_design/b200_clk_gen_exdes.v} +import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/b200_clk_gen_exdes.xdc} +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module b200_clk_gen_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module b200_clk_gen_exdes -file routed.v +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.prj b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.prj new file mode 100755 index 000000000..51a950151 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.prj @@ -0,0 +1,2 @@ +verilog work ../../b200_clk_gen.v +verilog work ../example_design/b200_clk_gen_exdes.v diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.scr b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.scr new file mode 100755 index 000000000..ae0a09163 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.scr @@ -0,0 +1,9 @@ +run +-ifmt MIXED +-top b200_clk_gen_exdes +-p xc6slx75-csg484-2 +-ifn xst.prj +-ofn b200_clk_gen_exdes +-keep_hierarchy soft +-equivalent_register_removal no +-max_fanout 65535 diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/b200_clk_gen_tb.v b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/b200_clk_gen_tb.v new file mode 100755 index 000000000..f7dba4105 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/b200_clk_gen_tb.v @@ -0,0 +1,146 @@ +// file: b200_clk_gen_tb.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard demonstration testbench +//---------------------------------------------------------------------------- +// This demonstration testbench instantiates the example design for the +// clocking wizard. Input clocks are toggled, which cause the clocking +// network to lock and the counters to increment. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +`define wait_lock @(posedge LOCKED) + +module b200_clk_gen_tb (); + + // Clock to Q delay of 100ps + localparam TCQ = 100; + + + // timescale is 1ps/1ps + localparam ONE_NS = 1000; + localparam PHASE_ERR_MARGIN = 100; // 100ps + // how many cycles to run + localparam COUNT_PHASE = 1024; + // we'll be using the period in many locations + localparam time PER1 = 25.0*ONE_NS; + localparam time PER1_1 = PER1/2; + localparam time PER1_2 = PER1 - PER1/2; + + // Declare the input clock signals + reg CLK_IN1 = 1; + wire CLK_IN1_P = CLK_IN1; + wire CLK_IN1_N = ~CLK_IN1; + + // The high bits of the sampling counters + wire [3:1] COUNT; + // Status and control signals + reg RESET = 0; + wire LOCKED; + reg COUNTER_RESET = 0; +wire [3:1] CLK_OUT; +//Freq Check using the M & D values setting and actual Frequency generated + + + // Input clock generation + //------------------------------------ + always begin + CLK_IN1 = #PER1_1 ~CLK_IN1; + CLK_IN1 = #PER1_2 ~CLK_IN1; + end + + // Test sequence + reg [15*8-1:0] test_phase = ""; + initial begin + // Set up any display statements using time to be readable + $timeformat(-12, 2, "ps", 10); + COUNTER_RESET = 0; + test_phase = "reset"; + RESET = 1; + #(PER1*6); + RESET = 0; + test_phase = "wait lock"; + `wait_lock; + #(PER1*6); + COUNTER_RESET = 1; + #(PER1*20) + COUNTER_RESET = 0; + + test_phase = "counting"; + #(PER1*COUNT_PHASE); + + $display("SIMULATION PASSED"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + + // Instantiation of the example design containing the clock + // network and sampling counters + //--------------------------------------------------------- + b200_clk_gen_exdes + #( + .TCQ (TCQ) + ) dut + (// Clock in ports + .CLK_IN1_P (CLK_IN1_P), + .CLK_IN1_N (CLK_IN1_N), + // Reset for logic in example design + .COUNTER_RESET (COUNTER_RESET), + .CLK_OUT (CLK_OUT), + // High bits of the counters + .COUNT (COUNT), + // Status and control signals + .RESET (RESET), + .LOCKED (LOCKED)); + +// Freq Check + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simcmds.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simcmds.tcl new file mode 100755 index 000000000..f22f9e447 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simcmds.tcl @@ -0,0 +1,8 @@ +# file: simcmds.tcl + +# create the simulation script +vcd dumpfile isim.vcd +vcd dumpvars -m /b200_clk_gen_tb -l 0 +wave add / +run 50000ns +quit diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.bat new file mode 100755 index 000000000..227a07e0c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.bat @@ -0,0 +1,59 @@ +REM file: simulate_isim.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +vlogcomp -work work %XILINX%\verilog\src\glbl.v +vlogcomp -work work ..\..\..\b200_clk_gen.v +vlogcomp -work work ..\..\example_design\b200_clk_gen_exdes.v +vlogcomp -work work ..\b200_clk_gen_tb.v + +REM compile the project +fuse work.b200_clk_gen_tb work.glbl -L unisims_ver -o b200_clk_gen_isim.exe + +REM run the simulation script +.\b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.sh new file mode 100755 index 000000000..db1b8cc4b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.sh @@ -0,0 +1,61 @@ +# file: simulate_isim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# lin64 +# create the project +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work ../../../b200_clk_gen.v +vlogcomp -work work ../../example_design/b200_clk_gen_exdes.v +vlogcomp -work work ../b200_clk_gen_tb.v + +# compile the project +fuse work.b200_clk_gen_tb work.glbl -L unisims_ver -o b200_clk_gen_isim.exe + +# run the simulation script +./b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.bat new file mode 100755 index 000000000..86e433ecb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.bat @@ -0,0 +1,61 @@ +REM file: simulate_mti.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM set up the working directory +vlib work + +REM compile all of the files +vlog -work work %XILINX%\verilog\src\glbl.v +vlog -work work ..\..\..\b200_clk_gen.v +vlog -work work ..\..\example_design\b200_clk_gen_exdes.v +vlog -work work ..\b200_clk_gen_tb.v + +REM run the simulation +vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.b200_clk_gen_tb work.glbl + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.do b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.do new file mode 100755 index 000000000..fbb4124b9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.do @@ -0,0 +1,65 @@ +# file: simulate_mti.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $env(XILINX)/verilog/src/glbl.v +vlog -work work ../../../b200_clk_gen.v +vlog -work work ../../example_design/b200_clk_gen_exdes.v +vlog -work work ../b200_clk_gen_tb.v + +# run the simulation +vsim -t ps -voptargs="+acc" -L unisims_ver work.b200_clk_gen_tb work.glbl +do wave.do +log b200_clk_gen_tb/dut/counter +log -r /* +run 50000ns diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.sh new file mode 100755 index 000000000..1d9455134 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.sh @@ -0,0 +1,61 @@ +#/bin/sh +# file: simulate_mti.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $XILINX/verilog/src/glbl.v +vlog -work work ../../../b200_clk_gen.v +vlog -work work ../../example_design/b200_clk_gen_exdes.v +vlog -work work ../b200_clk_gen_tb.v + +# run the simulation +vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.b200_clk_gen_tb work.glbl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_ncsim.sh new file mode 100755 index 000000000..eeb5b9712 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_ncsim.sh @@ -0,0 +1,62 @@ +#/bin/sh +# file: simulate_ncsim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +mkdir work + +# compile all of the files +ncvlog -work work ${XILINX}/verilog/src/glbl.v +ncvlog -work work ../../../b200_clk_gen.v +ncvlog -work work ../../example_design/b200_clk_gen_exdes.v +ncvlog -work work ../b200_clk_gen_tb.v + +# elaborate and run the simulation +ncelab -work work -access +wc work.b200_clk_gen_tb work.glbl +ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.b200_clk_gen_tb diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_vcs.sh new file mode 100755 index 000000000..66b2cfb09 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_vcs.sh @@ -0,0 +1,72 @@ +#!/bin/sh +# file: simulate_vcs.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# remove old files +rm -rf simv* csrc DVEfiles AN.DB + +# compile all of the files +# Note that -sverilog is not strictly required- You can +# remove the -sverilog if you change the type of the +# localparam for the periods in the testbench file to +# [63:0] from time +vlogan -sverilog \ + ${XILINX}/verilog/src/glbl.v \ + ../../../b200_clk_gen.v \ + ../../example_design/b200_clk_gen_exdes.v \ + ../b200_clk_gen_tb.v + +# prepare the simulation +vcs +vcs+lic+wait -debug b200_clk_gen_tb glbl + +# run the simulation +./simv -ucli -i ucli_commands.key + +# launch the viewer +dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/ucli_commands.key b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/ucli_commands.key new file mode 100755 index 000000000..d35a8a813 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/ucli_commands.key @@ -0,0 +1,5 @@ +call {$vcdpluson} +call {$vcdplusmemon(b200_clk_gen_tb.dut.counter)} +run +call {$vcdplusclose} +quit diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/vcs_session.tcl new file mode 100755 index 000000000..b751d0624 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/vcs_session.tcl @@ -0,0 +1,18 @@ +gui_open_window Wave +gui_sg_create b200_clk_gen_group +gui_list_add_group -id Wave.1 {b200_clk_gen_group} +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.test_phase} +gui_set_radix -radix {ascii} -signals {b200_clk_gen_tb.test_phase} +gui_sg_addsignal -group b200_clk_gen_group {{Input_clocks}} -divider +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.CLK_IN1} +gui_sg_addsignal -group b200_clk_gen_group {{Output_clocks}} -divider +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.dut.clk} +gui_list_expand -id Wave.1 b200_clk_gen_tb.dut.clk +gui_sg_addsignal -group b200_clk_gen_group {{Status_control}} -divider +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.RESET} +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.LOCKED} +gui_sg_addsignal -group b200_clk_gen_group {{Counters}} -divider +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.COUNT} +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.dut.counter} +gui_list_expand -id Wave.1 b200_clk_gen_tb.dut.counter +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.do b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.do new file mode 100755 index 000000000..f05bb5c2e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.do @@ -0,0 +1,60 @@ +# file: wave.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +add wave -noupdate -format Literal -radix ascii /b200_clk_gen_tb/test_phase +add wave -noupdate -divider {Input clocks} +add wave -noupdate -format Logic /b200_clk_gen_tb/CLK_IN1 +add wave -noupdate -divider {Output clocks} +add wave -noupdate -format Literal -expand /b200_clk_gen_tb/dut/clk +add wave -noupdate -divider Status/control +add wave -noupdate -format Logic /b200_clk_gen_tb/RESET +add wave -noupdate -format Logic /b200_clk_gen_tb/LOCKED +add wave -noupdate -divider Counters +add wave -noupdate -format Literal -radix hexadecimal /b200_clk_gen_tb/COUNT +add wave -noupdate -format Literal -radix hexadecimal -expand /b200_clk_gen_tb/dut/counter diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.sv b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.sv new file mode 100755 index 000000000..4bce3bcba --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.sv @@ -0,0 +1,119 @@ +# file: wave.sv +# +# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# Get the windows set up +# +if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} { + window geometry "Design Browser 1" 1054x819+536+322 +} +window target "Design Browser 1" on +browser using {Design Browser 1} +browser set \ + -scope nc::b200_clk_gen_tb +browser yview see nc::b200_clk_gen_tb +browser timecontrol set -lock 0 + +if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} { + window geometry "Waveform 1" 1010x600+0+541 +} +window target "Waveform 1" on +waveform using {Waveform 1} +waveform sidebar visibility partial +waveform set \ + -primarycursor TimeA \ + -signalnames name \ + -signalwidth 175 \ + -units ns \ + -valuewidth 75 +cursor set -using TimeA -time 0 +waveform baseline set -time 0 +waveform xview limits 0 20000n + +# +# Define signal groups +# +catch {group new -name {Output clocks} -overlay 0} +catch {group new -name {Status/control} -overlay 0} +catch {group new -name {Counters} -overlay 0} + +set id [waveform add -signals [list {nc::b200_clk_gen_tb.CLK_IN1}]] + +group using {Output clocks} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {b200_clk_gen_tb.dut.clk[1]} \ + {b200_clk_gen_tb.dut.clk[2]} \ {b200_clk_gen_tb.dut.clk[3]} +group using {Counters} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {b200_clk_gen_tb.dut.counter[1]} \ + {b200_clk_gen_tb.dut.counter[2]} \ {b200_clk_gen_tb.dut.counter[3]} +group using {Status/control} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {nc::b200_clk_gen_tb.RESET} {nc::b200_clk_gen_tb.LOCKED} + + +set id [waveform add -signals [list {nc::b200_clk_gen_tb.COUNT} ]] + +set id [waveform add -signals [list {nc::b200_clk_gen_tb.test_phase} ]] +waveform format $id -radix %a + +set groupId [waveform add -groups {{Input clocks}}] +set groupId [waveform add -groups {{Output clocks}}] +set groupId [waveform add -groups {{Status/control}}] +set groupId [waveform add -groups {{Counters}}] diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/b200_clk_gen_tb.v b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/b200_clk_gen_tb.v new file mode 100755 index 000000000..4d0d01cb0 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/b200_clk_gen_tb.v @@ -0,0 +1,160 @@ +// file: b200_clk_gen_tb.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard demonstration testbench +//---------------------------------------------------------------------------- +// This demonstration testbench instantiates the example design for the +// clocking wizard. Input clocks are toggled, which cause the clocking +// network to lock and the counters to increment. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +`define wait_lock @(posedge LOCKED) + +module b200_clk_gen_tb (); + + // Clock to Q delay of 100ps + localparam TCQ = 100; + + + // timescale is 1ps/1ps + localparam ONE_NS = 1000; + localparam PHASE_ERR_MARGIN = 100; // 100ps + // how many cycles to run + localparam COUNT_PHASE = 1024; + // we'll be using the period in many locations + localparam time PER1 = 25.0*ONE_NS; + localparam time PER1_1 = PER1/2; + localparam time PER1_2 = PER1 - PER1/2; + + // Declare the input clock signals + reg CLK_IN1 = 1; + wire CLK_IN1_P = CLK_IN1; + wire CLK_IN1_N = ~CLK_IN1; + + // The high bits of the sampling counters + wire [3:1] COUNT; + // Status and control signals + reg RESET = 0; + wire LOCKED; + reg COUNTER_RESET = 0; +wire [3:1] CLK_OUT; +//Freq Check using the M & D values setting and actual Frequency generated + + reg [13:0] timeout_counter = 14'b00000000000000; + + // Input clock generation + //------------------------------------ + always begin + CLK_IN1 = #PER1_1 ~CLK_IN1; + CLK_IN1 = #PER1_2 ~CLK_IN1; + end + + // Test sequence + reg [15*8-1:0] test_phase = ""; + initial begin + // Set up any display statements using time to be readable + $timeformat(-12, 2, "ps", 10); + $display ("Timing checks are not valid"); + COUNTER_RESET = 0; + test_phase = "reset"; + RESET = 1; + #(PER1*6); + RESET = 0; + test_phase = "wait lock"; + `wait_lock; + #(PER1*6); + COUNTER_RESET = 1; + #(PER1*19.5) + COUNTER_RESET = 0; + #(PER1*1) + $display ("Timing checks are valid"); + test_phase = "counting"; + #(PER1*COUNT_PHASE); + + $display("SIMULATION PASSED"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + + + always@(posedge CLK_IN1) begin + timeout_counter <= timeout_counter + 1'b1; + if (timeout_counter == 14'b10000000000000) begin + if (LOCKED != 1'b1) begin + $display("ERROR : NO LOCK signal"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + end + end + + // Instantiation of the example design containing the clock + // network and sampling counters + //--------------------------------------------------------- + b200_clk_gen_exdes + dut + (// Clock in ports + .CLK_IN1_P (CLK_IN1_P), + .CLK_IN1_N (CLK_IN1_N), + // Reset for logic in example design + .COUNTER_RESET (COUNTER_RESET), + .CLK_OUT (CLK_OUT), + // High bits of the counters + .COUNT (COUNT), + // Status and control signals + .RESET (RESET), + .LOCKED (LOCKED)); + + +// Freq Check + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/sdf_cmd_file b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/sdf_cmd_file new file mode 100755 index 000000000..0e8696ce6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/sdf_cmd_file @@ -0,0 +1,2 @@ +COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", +SCOPE = b200_clk_gen_tb.dut; diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simcmds.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simcmds.tcl new file mode 100755 index 000000000..00e00dd03 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simcmds.tcl @@ -0,0 +1,9 @@ +# file: simcmds.tcl + +# create the simulation script +vcd dumpfile isim.vcd +vcd dumpvars -m /b200_clk_gen_tb -l 0 +wave add / +run 50000ns +quit + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_isim.sh new file mode 100755 index 000000000..edf149164 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_isim.sh @@ -0,0 +1,62 @@ +# file: simulate_isim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# create the project +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work ../../implement/results/routed.v +vlogcomp -work work b200_clk_gen_tb.v + +# compile the project +fuse work.b200_clk_gen_tb work.glbl -L secureip -L simprims_ver -o b200_clk_gen_isim.exe + +# run the simulation script +./b200_clk_gen_isim.exe -tclbatch simcmds.tcl -sdfmax /b200_clk_gen_tb/dut=../../implement/results/routed.sdf + +# run the simulation script +#./b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.bat new file mode 100755 index 000000000..b759f9529 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.bat @@ -0,0 +1,59 @@ +REM file: simulate_mti.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM +# set up the working directory +set work work +vlib work + +REM compile all of the files +vlog -work work %XILINX%\verilog\src\glbl.v +vlog -work work ..\..\implement\results\routed.v +vlog -work work b200_clk_gen_tb.v + +REM run the simulation +vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.do b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.do new file mode 100755 index 000000000..cfe22dc41 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.do @@ -0,0 +1,65 @@ +# file: simulate_mti.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $env(XILINX)/verilog/src/glbl.v +vlog -work work ../../implement/results/routed.v +vlog -work work b200_clk_gen_tb.v + +# run the simulation +vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb/dut=../../implement/results/routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl +#do wave.do +#log -r /* +run 50000ns + + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.sh new file mode 100755 index 000000000..497db4bbd --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.sh @@ -0,0 +1,61 @@ +#/bin/sh +# file: simulate_mti.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $XILINX/verilog/src/glbl.v +vlog -work work ../../implement/results/routed.v +vlog -work work b200_clk_gen_tb.v + +# run the simulation +vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb/dut=../../implement/results/routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_ncsim.sh new file mode 100755 index 000000000..8dd610f57 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_ncsim.sh @@ -0,0 +1,64 @@ +#!/bin/sh +# file: simulate_ncsim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +mkdir work + +# compile all of the files +ncvlog -work work ${XILINX}/verilog/src/glbl.v +ncvlog -work work ../../implement/results/routed.v +ncvlog -work work b200_clk_gen_tb.v + +# elaborate and run the simulation +ncsdfc ../../implement/results/routed.sdf + +ncelab -work work -access +wc -pulse_r 10 -nonotifier work.b200_clk_gen_tb work.glbl -sdf_cmd_file sdf_cmd_file +ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.b200_clk_gen_tb + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_vcs.sh new file mode 100755 index 000000000..3566700b2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_vcs.sh @@ -0,0 +1,72 @@ +#!/bin/sh +# file: simulate_vcs.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# remove old files +rm -rf simv* csrc DVEfiles AN.DB + +# compile all of the files +# Note that -sverilog is not strictly required- You can +# remove the -sverilog if you change the type of the +# localparam for the periods in the testbench file to +# [63:0] from time + vlogan -sverilog \ + b200_clk_gen_tb.v \ + ../../implement/results/routed.v + + +# prepare the simulation +vcs -sdf max:b200_clk_gen_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \ + +libext+.v -debug b200_clk_gen_tb.v ../../implement/results/routed.v + +# run the simulation +./simv -ucli -i ucli_commands.key + +# launch the viewer +#dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/ucli_commands.key b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/ucli_commands.key new file mode 100755 index 000000000..0548d1733 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/ucli_commands.key @@ -0,0 +1,5 @@ + +call {$vcdpluson} +run 50000ns +call {$vcdplusclose} +quit diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/vcs_session.tcl new file mode 100755 index 000000000..1438f6bed --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/vcs_session.tcl @@ -0,0 +1 @@ +gui_open_window Wave diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/wave.do b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/wave.do new file mode 100755 index 000000000..048ce6aa6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/wave.do @@ -0,0 +1,72 @@ +# file: wave.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /b200_clk_gen_tb/CLK_IN1 +add wave -noupdate /b200_clk_gen_tb/COUNT +add wave -noupdate /b200_clk_gen_tb/LOCKED +add wave -noupdate /b200_clk_gen_tb/RESET +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {3223025 ps} 0} +configure wave -namecolwidth 238 +configure wave -valuecolwidth 107 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {74848022 ps} diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen_flist.txt b/fpga/usrp3/top/b200/coregen/b200_clk_gen_flist.txt new file mode 100644 index 000000000..044c06a12 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen_flist.txt @@ -0,0 +1,53 @@ +# Output products list for <b200_clk_gen> +b200_clk_gen/clk_wiz_v3_6_readme.txt +b200_clk_gen/doc/clk_wiz_v3_6_readme.txt +b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html +b200_clk_gen/doc/pg065_clk_wiz.pdf +b200_clk_gen/example_design/b200_clk_gen_exdes.ucf +b200_clk_gen/example_design/b200_clk_gen_exdes.v +b200_clk_gen/example_design/b200_clk_gen_exdes.xdc +b200_clk_gen/implement/implement.bat +b200_clk_gen/implement/implement.sh +b200_clk_gen/implement/planAhead_ise.bat +b200_clk_gen/implement/planAhead_ise.sh +b200_clk_gen/implement/planAhead_ise.tcl +b200_clk_gen/implement/planAhead_rdn.bat +b200_clk_gen/implement/planAhead_rdn.sh +b200_clk_gen/implement/planAhead_rdn.tcl +b200_clk_gen/implement/xst.prj +b200_clk_gen/implement/xst.scr +b200_clk_gen/simulation/b200_clk_gen_tb.v +b200_clk_gen/simulation/functional/simcmds.tcl +b200_clk_gen/simulation/functional/simulate_isim.bat +b200_clk_gen/simulation/functional/simulate_isim.sh +b200_clk_gen/simulation/functional/simulate_mti.bat +b200_clk_gen/simulation/functional/simulate_mti.do +b200_clk_gen/simulation/functional/simulate_mti.sh +b200_clk_gen/simulation/functional/simulate_ncsim.sh +b200_clk_gen/simulation/functional/simulate_vcs.sh +b200_clk_gen/simulation/functional/ucli_commands.key +b200_clk_gen/simulation/functional/vcs_session.tcl +b200_clk_gen/simulation/functional/wave.do +b200_clk_gen/simulation/functional/wave.sv +b200_clk_gen/simulation/timing/b200_clk_gen_tb.v +b200_clk_gen/simulation/timing/sdf_cmd_file +b200_clk_gen/simulation/timing/simcmds.tcl +b200_clk_gen/simulation/timing/simulate_isim.sh +b200_clk_gen/simulation/timing/simulate_mti.bat +b200_clk_gen/simulation/timing/simulate_mti.do +b200_clk_gen/simulation/timing/simulate_mti.sh +b200_clk_gen/simulation/timing/simulate_ncsim.sh +b200_clk_gen/simulation/timing/simulate_vcs.sh +b200_clk_gen/simulation/timing/ucli_commands.key +b200_clk_gen/simulation/timing/vcs_session.tcl +b200_clk_gen/simulation/timing/wave.do +b200_clk_gen.asy +b200_clk_gen.gise +b200_clk_gen.ucf +b200_clk_gen.v +b200_clk_gen.veo +b200_clk_gen.xco +b200_clk_gen.xdc +b200_clk_gen.xise +b200_clk_gen_flist.txt +b200_clk_gen_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen_xmdf.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen_xmdf.tcl new file mode 100755 index 000000000..58f510c56 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen_xmdf.tcl @@ -0,0 +1,144 @@ +# The package naming convention is <core_name>_xmdf +package provide b200_clk_gen_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is <core_name>_xmdf +namespace eval ::b200_clk_gen_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::b200_clk_gen_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: <module_name> +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_clk_gen +} +# ::b200_clk_gen_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::b200_clk_gen_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/clk_wiz_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/example_design/b200_clk_gen_exdes.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/doc/clk_wiz_ds709.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/doc/clk_wiz_gsg521.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/example_design/b200_clk_gen_exdes.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/b200_clk_gen_tb.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simcmds.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/wave.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/wave.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.ejp +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_clk_gen +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.asy b/fpga/usrp3/top/b200/coregen/chipscope_icon.asy new file mode 100644 index 000000000..a5c9ce410 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.asy @@ -0,0 +1,13 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 chipscope_icon +RECTANGLE Normal 32 32 544 864 +LINE Wide 576 112 544 112 +PIN 576 112 RIGHT 36 +PINATTR PinName control0[35:0] +PINATTR Polarity BOTH +LINE Wide 576 144 544 144 +PIN 576 144 RIGHT 36 +PINATTR PinName control1[35:0] +PINATTR Polarity BOTH + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.ucf b/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.ucf new file mode 100644 index 000000000..b83296f8e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.ucf @@ -0,0 +1,9 @@ +NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ; +TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ; +#Update Constraints +NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ; +NET "U0/iSHIFT_OUT" TIG ; +TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ; +TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ; +TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ; +TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.xdc b/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.xdc new file mode 100644 index 000000000..903799425 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.xdc @@ -0,0 +1,7 @@ +# icon XDC +create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] +create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}] +set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}] +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2 +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1 +set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK} diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.gise b/fpga/usrp3/top/b200/coregen/chipscope_icon.gise new file mode 100644 index 000000000..a4f878755 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.gise @@ -0,0 +1,31 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="chipscope_icon.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="chipscope_icon.asy" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="chipscope_icon.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.ncf b/fpga/usrp3/top/b200/coregen/chipscope_icon.ncf new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.ncf diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.ngc b/fpga/usrp3/top/b200/coregen/chipscope_icon.ngc new file mode 100644 index 000000000..58d57c1e1 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.ucf b/fpga/usrp3/top/b200/coregen/chipscope_icon.ucf new file mode 100644 index 000000000..b83296f8e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.ucf @@ -0,0 +1,9 @@ +NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ; +TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ; +#Update Constraints +NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ; +NET "U0/iSHIFT_OUT" TIG ; +TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ; +TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ; +TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ; +TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.v b/fpga/usrp3/top/b200/coregen/chipscope_icon.v new file mode 100644 index 000000000..2fa3203dd --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.v @@ -0,0 +1,29 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_icon.v +// /___/ /\ Timestamp : Fri Mar 08 11:51:37 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: Verilog Synthesis Wrapper +/////////////////////////////////////////////////////////////////////////////// +// This wrapper is used to integrate with Project Navigator and PlanAhead + +`timescale 1ns/1ps + +module chipscope_icon( + CONTROL0, + CONTROL1) /* synthesis syn_black_box syn_noprune=1 */; + + +inout [35 : 0] CONTROL0; +inout [35 : 0] CONTROL1; + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.veo b/fpga/usrp3/top/b200/coregen/chipscope_icon.veo new file mode 100644 index 000000000..777580b34 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.veo @@ -0,0 +1,29 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_icon.veo +// /___/ /\ Timestamp : Fri Mar 08 11:51:37 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: ISE Instantiation template +/////////////////////////////////////////////////////////////////////////////// + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +chipscope_icon YourInstanceName ( + .CONTROL0(CONTROL0), // INOUT BUS [35:0] + .CONTROL1(CONTROL1) // INOUT BUS [35:0] +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.xco b/fpga/usrp3/top/b200/coregen/chipscope_icon.xco new file mode 100644 index 000000000..69906ce4d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.xco @@ -0,0 +1,56 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Fri Mar 8 19:51:09 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a +# END Select +# BEGIN Parameters +CSET component_name=chipscope_icon +CSET constraint_type=external +CSET enable_jtag_bufg=true +CSET example_design=false +CSET number_control_ports=2 +CSET use_ext_bscan=false +CSET use_softbscan=false +CSET use_unused_bscan=false +CSET user_scan_chain=USER1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T02:47:25Z +# END Extra information +GENERATE +# CRC: 865957ec diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.xdc b/fpga/usrp3/top/b200/coregen/chipscope_icon.xdc new file mode 100644 index 000000000..903799425 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.xdc @@ -0,0 +1,7 @@ +# icon XDC +create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] +create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}] +set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}] +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2 +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1 +set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK} diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.xise b/fpga/usrp3/top/b200/coregen/chipscope_icon.xise new file mode 100644 index 000000000..49d561436 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.xise @@ -0,0 +1,73 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="chipscope_icon.ngc" xil_pn:type="FILE_NGC"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="chipscope_icon.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/> + </file> + </files> + + <properties> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> + <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Module|chipscope_icon" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top File" xil_pn:value="chipscope_icon.ngc" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/chipscope_icon" xil_pn:valueState="non-default"/> + <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_icon" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-08T11:51:40" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BD46AAD29AD5653980780005171DAA9E" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon_flist.txt b/fpga/usrp3/top/b200/coregen/chipscope_icon_flist.txt new file mode 100644 index 000000000..435dc80e2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon_flist.txt @@ -0,0 +1,16 @@ +# Output products list for <chipscope_icon> +_xmsgs/pn_parser.xmsgs +chipscope_icon.asy +chipscope_icon.constraints/chipscope_icon.ucf +chipscope_icon.constraints/chipscope_icon.xdc +chipscope_icon.gise +chipscope_icon.ngc +chipscope_icon.ucf +chipscope_icon.v +chipscope_icon.veo +chipscope_icon.xco +chipscope_icon.xdc +chipscope_icon.xise +chipscope_icon_flist.txt +chipscope_icon_readme.txt +chipscope_icon_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon_readme.txt b/fpga/usrp3/top/b200/coregen/chipscope_icon_readme.txt new file mode 100644 index 000000000..ac93ce5a1 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon_readme.txt @@ -0,0 +1,46 @@ +The following files were generated for 'chipscope_icon' in directory +/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/ + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * chipscope_icon.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * chipscope_icon.constraints/chipscope_icon.ucf + * chipscope_icon.constraints/chipscope_icon.xdc + * chipscope_icon.ngc + * chipscope_icon.ucf + * chipscope_icon.v + * chipscope_icon.veo + * chipscope_icon.xdc + * chipscope_icon_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * chipscope_icon.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * _xmsgs/pn_parser.xmsgs + * chipscope_icon.gise + * chipscope_icon.xise + +Deliver Readme: + Readme file for the IP. + + * chipscope_icon_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * chipscope_icon_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon_xmdf.tcl b/fpga/usrp3/top/b200/coregen/chipscope_icon_xmdf.tcl new file mode 100755 index 000000000..241f4d5ae --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon_xmdf.tcl @@ -0,0 +1,88 @@ +# The package naming convention is <core_name>_xmdf +package provide chipscope_icon_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is <core_name>_xmdf +namespace eval ::chipscope_icon_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::chipscope_icon_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: <module_name> +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_icon +} +# ::chipscope_icon_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::chipscope_icon_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xcf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_icon +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.asy b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.asy new file mode 100644 index 000000000..5342fbe4f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 chipscope_ila_128 +RECTANGLE Normal 32 32 288 704 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName control[35:0] +PINATTR Polarity IN +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Wide 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName trig0[127:0] +PINATTR Polarity IN + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.cdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.cdc new file mode 100644 index 000000000..be4f8951b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.cdc @@ -0,0 +1,144 @@ +#ChipScope Core Generator Project File Version 3.0 +#Fri Mar 08 11:53:53 PST 2013 +SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 +SignalExport.bus<0000>.name=TRIG0 +SignalExport.bus<0000>.offset=0.0 +SignalExport.bus<0000>.precision=0 +SignalExport.bus<0000>.radix=Bin +SignalExport.bus<0000>.scaleFactor=1.0 +SignalExport.clockChannel=CLK +SignalExport.dataEqualsTrigger=true +SignalExport.triggerChannel<0000><0000>=TRIG0[0] +SignalExport.triggerChannel<0000><0001>=TRIG0[1] +SignalExport.triggerChannel<0000><0002>=TRIG0[2] +SignalExport.triggerChannel<0000><0003>=TRIG0[3] +SignalExport.triggerChannel<0000><0004>=TRIG0[4] +SignalExport.triggerChannel<0000><0005>=TRIG0[5] +SignalExport.triggerChannel<0000><0006>=TRIG0[6] +SignalExport.triggerChannel<0000><0007>=TRIG0[7] +SignalExport.triggerChannel<0000><0008>=TRIG0[8] +SignalExport.triggerChannel<0000><0009>=TRIG0[9] +SignalExport.triggerChannel<0000><0010>=TRIG0[10] +SignalExport.triggerChannel<0000><0011>=TRIG0[11] +SignalExport.triggerChannel<0000><0012>=TRIG0[12] +SignalExport.triggerChannel<0000><0013>=TRIG0[13] +SignalExport.triggerChannel<0000><0014>=TRIG0[14] +SignalExport.triggerChannel<0000><0015>=TRIG0[15] +SignalExport.triggerChannel<0000><0016>=TRIG0[16] +SignalExport.triggerChannel<0000><0017>=TRIG0[17] +SignalExport.triggerChannel<0000><0018>=TRIG0[18] +SignalExport.triggerChannel<0000><0019>=TRIG0[19] +SignalExport.triggerChannel<0000><0020>=TRIG0[20] +SignalExport.triggerChannel<0000><0021>=TRIG0[21] +SignalExport.triggerChannel<0000><0022>=TRIG0[22] +SignalExport.triggerChannel<0000><0023>=TRIG0[23] +SignalExport.triggerChannel<0000><0024>=TRIG0[24] +SignalExport.triggerChannel<0000><0025>=TRIG0[25] +SignalExport.triggerChannel<0000><0026>=TRIG0[26] +SignalExport.triggerChannel<0000><0027>=TRIG0[27] +SignalExport.triggerChannel<0000><0028>=TRIG0[28] +SignalExport.triggerChannel<0000><0029>=TRIG0[29] +SignalExport.triggerChannel<0000><0030>=TRIG0[30] +SignalExport.triggerChannel<0000><0031>=TRIG0[31] +SignalExport.triggerChannel<0000><0032>=TRIG0[32] +SignalExport.triggerChannel<0000><0033>=TRIG0[33] +SignalExport.triggerChannel<0000><0034>=TRIG0[34] +SignalExport.triggerChannel<0000><0035>=TRIG0[35] +SignalExport.triggerChannel<0000><0036>=TRIG0[36] +SignalExport.triggerChannel<0000><0037>=TRIG0[37] +SignalExport.triggerChannel<0000><0038>=TRIG0[38] +SignalExport.triggerChannel<0000><0039>=TRIG0[39] +SignalExport.triggerChannel<0000><0040>=TRIG0[40] +SignalExport.triggerChannel<0000><0041>=TRIG0[41] +SignalExport.triggerChannel<0000><0042>=TRIG0[42] +SignalExport.triggerChannel<0000><0043>=TRIG0[43] +SignalExport.triggerChannel<0000><0044>=TRIG0[44] +SignalExport.triggerChannel<0000><0045>=TRIG0[45] +SignalExport.triggerChannel<0000><0046>=TRIG0[46] +SignalExport.triggerChannel<0000><0047>=TRIG0[47] +SignalExport.triggerChannel<0000><0048>=TRIG0[48] +SignalExport.triggerChannel<0000><0049>=TRIG0[49] +SignalExport.triggerChannel<0000><0050>=TRIG0[50] +SignalExport.triggerChannel<0000><0051>=TRIG0[51] +SignalExport.triggerChannel<0000><0052>=TRIG0[52] +SignalExport.triggerChannel<0000><0053>=TRIG0[53] +SignalExport.triggerChannel<0000><0054>=TRIG0[54] +SignalExport.triggerChannel<0000><0055>=TRIG0[55] +SignalExport.triggerChannel<0000><0056>=TRIG0[56] +SignalExport.triggerChannel<0000><0057>=TRIG0[57] +SignalExport.triggerChannel<0000><0058>=TRIG0[58] +SignalExport.triggerChannel<0000><0059>=TRIG0[59] +SignalExport.triggerChannel<0000><0060>=TRIG0[60] +SignalExport.triggerChannel<0000><0061>=TRIG0[61] +SignalExport.triggerChannel<0000><0062>=TRIG0[62] +SignalExport.triggerChannel<0000><0063>=TRIG0[63] +SignalExport.triggerChannel<0000><0064>=TRIG0[64] +SignalExport.triggerChannel<0000><0065>=TRIG0[65] +SignalExport.triggerChannel<0000><0066>=TRIG0[66] +SignalExport.triggerChannel<0000><0067>=TRIG0[67] +SignalExport.triggerChannel<0000><0068>=TRIG0[68] +SignalExport.triggerChannel<0000><0069>=TRIG0[69] +SignalExport.triggerChannel<0000><0070>=TRIG0[70] +SignalExport.triggerChannel<0000><0071>=TRIG0[71] +SignalExport.triggerChannel<0000><0072>=TRIG0[72] +SignalExport.triggerChannel<0000><0073>=TRIG0[73] +SignalExport.triggerChannel<0000><0074>=TRIG0[74] +SignalExport.triggerChannel<0000><0075>=TRIG0[75] +SignalExport.triggerChannel<0000><0076>=TRIG0[76] +SignalExport.triggerChannel<0000><0077>=TRIG0[77] +SignalExport.triggerChannel<0000><0078>=TRIG0[78] +SignalExport.triggerChannel<0000><0079>=TRIG0[79] +SignalExport.triggerChannel<0000><0080>=TRIG0[80] +SignalExport.triggerChannel<0000><0081>=TRIG0[81] +SignalExport.triggerChannel<0000><0082>=TRIG0[82] +SignalExport.triggerChannel<0000><0083>=TRIG0[83] +SignalExport.triggerChannel<0000><0084>=TRIG0[84] +SignalExport.triggerChannel<0000><0085>=TRIG0[85] +SignalExport.triggerChannel<0000><0086>=TRIG0[86] +SignalExport.triggerChannel<0000><0087>=TRIG0[87] +SignalExport.triggerChannel<0000><0088>=TRIG0[88] +SignalExport.triggerChannel<0000><0089>=TRIG0[89] +SignalExport.triggerChannel<0000><0090>=TRIG0[90] +SignalExport.triggerChannel<0000><0091>=TRIG0[91] +SignalExport.triggerChannel<0000><0092>=TRIG0[92] +SignalExport.triggerChannel<0000><0093>=TRIG0[93] +SignalExport.triggerChannel<0000><0094>=TRIG0[94] +SignalExport.triggerChannel<0000><0095>=TRIG0[95] +SignalExport.triggerChannel<0000><0096>=TRIG0[96] +SignalExport.triggerChannel<0000><0097>=TRIG0[97] +SignalExport.triggerChannel<0000><0098>=TRIG0[98] +SignalExport.triggerChannel<0000><0099>=TRIG0[99] +SignalExport.triggerChannel<0000><0100>=TRIG0[100] +SignalExport.triggerChannel<0000><0101>=TRIG0[101] +SignalExport.triggerChannel<0000><0102>=TRIG0[102] +SignalExport.triggerChannel<0000><0103>=TRIG0[103] +SignalExport.triggerChannel<0000><0104>=TRIG0[104] +SignalExport.triggerChannel<0000><0105>=TRIG0[105] +SignalExport.triggerChannel<0000><0106>=TRIG0[106] +SignalExport.triggerChannel<0000><0107>=TRIG0[107] +SignalExport.triggerChannel<0000><0108>=TRIG0[108] +SignalExport.triggerChannel<0000><0109>=TRIG0[109] +SignalExport.triggerChannel<0000><0110>=TRIG0[110] +SignalExport.triggerChannel<0000><0111>=TRIG0[111] +SignalExport.triggerChannel<0000><0112>=TRIG0[112] +SignalExport.triggerChannel<0000><0113>=TRIG0[113] +SignalExport.triggerChannel<0000><0114>=TRIG0[114] +SignalExport.triggerChannel<0000><0115>=TRIG0[115] +SignalExport.triggerChannel<0000><0116>=TRIG0[116] +SignalExport.triggerChannel<0000><0117>=TRIG0[117] +SignalExport.triggerChannel<0000><0118>=TRIG0[118] +SignalExport.triggerChannel<0000><0119>=TRIG0[119] +SignalExport.triggerChannel<0000><0120>=TRIG0[120] +SignalExport.triggerChannel<0000><0121>=TRIG0[121] +SignalExport.triggerChannel<0000><0122>=TRIG0[122] +SignalExport.triggerChannel<0000><0123>=TRIG0[123] +SignalExport.triggerChannel<0000><0124>=TRIG0[124] +SignalExport.triggerChannel<0000><0125>=TRIG0[125] +SignalExport.triggerChannel<0000><0126>=TRIG0[126] +SignalExport.triggerChannel<0000><0127>=TRIG0[127] +SignalExport.triggerPort<0000>.name=TRIG0 +SignalExport.triggerPortCount=1 +SignalExport.triggerPortIsData<0000>=true +SignalExport.triggerPortWidth<0000>=128 +SignalExport.type=ila + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.ucf new file mode 100644 index 000000000..736db76a7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.ucf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_chipscope_ila_128 = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise new file mode 100644 index 000000000..3af396d70 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise @@ -0,0 +1,31 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="chipscope_ila_128.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="chipscope_ila_128.asy" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="chipscope_ila_128.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ncf b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ncf new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ncf diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ngc b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ngc new file mode 100644 index 000000000..b5e78e4fd --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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7c22;?i7Ej64:Jg3g=#::h1hhh4$0g3>7=n;=0;66g<5;29?l512900e>650;9j<5<722cij7>5;n070?6=3th8<=4?:683>5}#:l?1>8l4He;7?Mb0j2.9?o4keg9'5`6=:2c887>5;h16>5<<a:<1<75f3983>>o?83:17dli:188k7232900qo<ie;293?6=8r.9i84=5c9K`<2<@m=i7)<<b;ffb>"6m9097d=;:188m63=831b?;4?::k0<?6=3`2;6=44icd94?=h:=>1<75rb3db>5<0290;w)<j5;06f>Nc1=1Ch:l4$31a>aca3-;n<7<4i2694?=n;<0;66g<6;29?l5?2900e5>50;9jfc<722e9894?::a6c>=83=1<7>t$3g6>73e3An286Fk7c9'66d=lll0(<k?:39j71<722c897>5;h15>5<<a:21<75f8183>>oen3:17b<;4;29?xd5n?0;6:4?:1y'6`3=:<h0Di7;;If4f>"5;k0oik5+1d296>o4<3:17d=::188m60=831b?54?::k;4?6=3`hm6=44o367>5<<uk8m87>57;294~"5m<099o5Gd868La1e3-88n7jjf:&2a5<53`9?6=44i2794?=n;?0;66g<8;29?l>72900eoh50;9l612=831vn?h=:184>5<7s-8n97<:b:Jg=1=Ol>h0(?=m:ege?!7b8380e>:50;9j70<722c8:7>5;h1;>5<<a1:1<75fbg83>>i5<=0;66sm2g294?1=83:p(?k::37a?Mb><2Bo;o5+22`9```<,8o;6?5f3583>>o4=3:17d=9:188m6>=831b4=4?::kab?6=3f8?87>5;|`1a`<72>0;6=u+2d7960d<@m3?7Ej8b:&17g<cmo1/=h>52:k00?6=3`9>6=44i2494?=n;10;66g70;29?lda2900c?:;:188yg4bk3:1;7>50z&1a0<5=k1Ch4:4He5a?!44j3nnj6*>e181?l532900e>;50;9j73<722c847>5;h:3>5<<akl1<75`25694?=zj;oj6=48:183!4b=38>n6Fk959K`2d<,;9i6iki;%3f4?4<a:>1<75f3483>>o4>3:17d=7:188m=6=831bnk4?::m101<722wi>h650;594?6|,;o>6?;m;If:0>Nc?k1/>>l5ddd8 4c72;1b?94?::k01?6=3`9=6=44i2:94?=n090;66gmf;29?j43<3:17pl<e383>2<729q/>h;524`8La?33An<n6*=3c8gac=#9l:1>6g<4;29?l522900e>850;9j7=<722c3<7>5;h`e>5<<g;>?6=44}c1f4?6=?3:1<v*=e4811g=Ol0>0Di9m;%00f?bbn2.:i=4=;h17>5<<a:?1<75f3783>>o403:17d6?:188mg`=831d>9:50;9~f6bb290<6=4?{%0f1?42j2Bo595Gd6`8 75e2mom7)?j0;08m62=831b?84?::k02?6=3`936=44i9294?=njo0;66a=4583>>{e;mi1<7950;2x 7c22;?i7Ej64:Jg3g=#::h1hhh4$0g3>7=n;=0;66g<5;29?l512900e>650;9j<5<722cij7>5;n070?6=3th8hl4?:683>5}#:l?1>8l4He;7?Mb0j2.9?o4keg9'5`6=:2c887>5;h16>5<<a:<1<75f3983>>o?83:17dli:188k7232900qo=k8;293?6=8r.9i84=5c9K`<2<@m=i7)<<b;ffb>"6m9097d=;:188m63=831b?;4?::k0<?6=3`2;6=44icd94?=h:=>1<75rb2f5>5<0290;w)<j5;06f>Nc1=1Ch:l4$31a>aca3-;n<7<4i2694?=n;<0;66g<6;29?l5?2900e5>50;9jfc<722e9894?::a7a2=83=1<7>t$3g6>73e3An286Fk7c9'66d=lll0(<k?:39j71<722c897>5;h15>5<<a:21<75f8183>>oen3:17b<;4;29?xd4l;0;6:4?:1y'6`3=:<h0Di7;;If4f>"5;k0oik5+1d296>o4<3:17d=::188m60=831b?54?::k;4?6=3`hm6=44o367>5<<uk9o<7>57;294~"5m<099o5Gd868La1e3-88n7jjf:&2a5<53`9?6=44i2794?=n;?0;66g<8;29?l>72900eoh50;9l612=831vn>ml:184>5<7s-8n97<:b:Jg=1=Ol>h0(?=m:ege?!7b8380e>:50;9j70<722c8:7>5;h1;>5<<a1:1<75fbg83>>i5<=0;66sm3bc94?1=83:p(?k::37a?Mb><2Bo;o5+22`9```<,8o;6?5f3583>>o4=3:17d=9:188m6>=831b4=4?::kab?6=3f8?87>5;|`0g=<72>0;6=u+2d7960d<@m3?7Ej8b:&17g<cmo1/=h>52:k00?6=3`9>6=44i2494?=n;10;66g70;29?lda2900c?:;:188yg5d>3:1;7>50z&1a0<5=k1Ch4:4He5a?!44j3nnj6*>e181?l532900e>;50;9j73<722c847>5;h:3>5<<akl1<75`25694?=zj:i?6=48:183!4b=38>n6Fk959K`2d<,;9i6iki;%3f4?4<a:>1<75f3483>>o4>3:17d=7:188m=6=831bnk4?::m101<722wi?n<50;594?6|,;o>6?;m;If:0>Nc?k1/>>l5ddd8 4c72;1b?94?::k01?6=3`9=6=44i2:94?=n090;66gmf;29?j43<3:17pl<c183>2<729q/>h;524`8La?33An<n6*=3c8gac=#9l:1>6g<4;29?l522900e>850;9j7=<722c3<7>5;h`e>5<<g;>?6=44}c1aa?6=?3:1<v*=e4811g=Ol0>0Di9m;%00f?bbn2.:i=4=;h17>5<<a:?1<75f3783>>o403:17d6?:188mg`=831d>9:50;9~f6dd290<6=4?{%0f1?42j2Bo595Gd6`8 75e2mom7)?j0;08m62=831b?84?::k02?6=3`936=44i9294?=njo0;66a=4583>>{e;kk1<7950;2x 7c22;?i7Ej64:Jg3g=#::h1hhh4$0g3>7=n;=0;66g<5;29?l512900e>650;9j<5<722cij7>5;n070?6=3th8n;4?:683>5}#:l?1>8l4He;7?Mb0j2.9?o4keg9'5`6=:2c887>5;h16>5<<a:<1<75f3983>>o?83:17dli:188k7232900qo=m4;293?6=8r.9i84=5c9K`<2<@m=i7)<<b;ffb>"6m9097d=;:188m63=831b?;4?::k0<?6=3`2;6=44icd94?=h:=>1<75rb2`1>5<0290;w)<j5;06f>Nc1=1Ch:l4$31a>aca3-;n<7<4i2694?=n;<0;66g<6;29?l5?2900e5>50;9jfc<722e9894?::a7g6=83=1<7>t$3g6>73e3An286Fk7c9'66d=lll0(<k?:39j71<722c897>5;h15>5<<a:21<75f8183>>oen3:17b<;4;29?xd4il0;6:4?:1y'6`3=:<h0Di7;;If4f>"5;k0oik5+1d296>o4<3:17d=::188m60=831b?54?::k;4?6=3`hm6=44o367>5<<uk9jo7>57;294~"5m<099o5Gd868La1e3-88n7jjf:&2a5<53`9?6=44i2794?=n;?0;66g<8;29?l>72900eoh50;9l612=831vn>on:184>5<7s-8n97<:b:Jg=1=Ol>h0(?=m:ege?!7b8380e>:50;9j70<722c8:7>5;h1;>5<<a1:1<75fbg83>>i5<=0;66sm3`:94?1=83:p(?k::37a?Mb><2Bo;o5+22`9```<,8o;6?5f3583>>o4=3:17d=9:188m6>=831b4=4?::kab?6=3f8?87>5;|`0e3<72>0;6=u+2d7960d<@m3?7Ej8b:&17g<cmo1/=h>52:k00?6=3`9>6=44i2494?=n;10;66g70;29?lda2900c?:;:188yg5f<3:1;7>50z&1a0<5=k1Ch4:4He5a?!44j3nnj6*>e181?l532900e>;50;9j73<722c847>5;h:3>5<<akl1<75`25694?=zj:k;6=48:183!4b=38>n6Fk959K`2d<,;9i6iki;%3f4?4<a:>1<75f3483>>o4>3:17d=7:188m=6=831bnk4?::m101<722wi?4k50;594?6|,;o>6?;m;If:0>Nc?k1/>>l5ddd8 4c72;1b?94?::k01?6=3`9=6=44i2:94?=n090;66gmf;29?j43<3:17pl<9b83>2<729q/>h;524`8La?33An<n6*=3c8gac=#9l:1>6g<4;29?l522900e>850;9j7=<722c3<7>5;h`e>5<<g;>?6=44}c1:e?6=?3:1<v*=e4811g=Ol0>0Di9m;%00f?bbn2.:i=4=;h17>5<<a:?1<75f3783>>o403:17d6?:188mg`=831d>9:50;9~f6??290<6=4?{%0f1?42j2Bo595Gd6`8 75e2mom7)?j0;08m62=831b?84?::k02?6=3`936=44i9294?=njo0;66a=4583>>{e;0<1<7950;2x 7c22;?i7Ej64:Jg3g=#::h1hhh4$0g3>7=n;=0;66g<5;29?l512900e>650;9j<5<722cij7>5;n070?6=3th8594?:683>5}#:l?1>8l4He;7?Mb0j2.9?o4keg9'5`6=:2c887>5;h16>5<<a:<1<75f3983>>o?83:17dli:188k7232900qo=62;293?6=8r.9i84=5c9K`<2<@m=i7)<<b;ffb>"6m9097d=;:188m63=831b?;4?::k0<?6=3`2;6=44icd94?=h:=>1<75rb2;3>5<0290;w)<j5;06f>Nc1=1Ch:l4$31a>aca3-;n<7<4i2694?=n;<0;66g<6;29?l5?2900e5>50;9jfc<722e9894?::a7=c=83=1<7>t$3g6>73e3An286Fk7c9'66d=lll0(<k?:39j71<722c897>5;h15>5<<a:21<75f8183>>oen3:17b<;4;29?xd40h0;6:4?:1y'6`3=:<h0Di7;;If4f>"5;k0oik5+1d296>o4<3:17d=::188m60=831b?54?::k;4?6=3`hm6=44o367>5<<uk9347>57;294~"5m<099o5Gd868La1e3-88n7jjf:&2a5<53`9?6=44i2794?=n;?0;66g<8;29?l>72900eoh50;9l612=831vn>69:184>5<7s-8n97<:b:Jg=1=Ol>h0(?=m:ege?!7b8380e>:50;9j70<722c8:7>5;h1;>5<<a1:1<75fbg83>>i5<=0;66sm39694?1=83:p(?k::37a?Mb><2Bo;o5+22`9```<,8o;6?5f3583>>o4=3:17d=9:188m6>=831b4=4?::kab?6=3f8?87>5;|`0<7<72>0;6=u+2d7960d<@m3?7Ej8b:&17g<cmo1/=h>52:k00?6=3`9>6=44i2494?=n;10;66g70;29?lda2900c?:;:188yg5?83:1;7>50z&1a0<5=k1Ch4:4He5a?!44j3nnj6*>e181?l532900e>;50;9j73<722c847>5;h:3>5<<akl1<75`25694?=zj:=n6=48:183!4b=38>n6Fk959K`2d<,;9i6iki;%3f4?4<a:>1<75f3483>>o4>3:17d=7:188m=6=831bnk4?::m101<722wi?:m50;594?6|,;o>6?;m;If:0>Nc?k1/>>l5ddd8 4c72;1b?94?::k01?6=3`9=6=44i2:94?=n090;66gmf;29?j43<3:17pl<7`83>2<729q/>h;524`8La?33An<n6*=3c8gac=#9l:1>6g<4;29?l522900e>850;9j7=<722c3<7>5;h`e>5<<g;>?6=44}c14<?6=?3:1<v*=e4811g=Ol0>0Di9m;%00f?bbn2.:i=4=;h17>5<<a:?1<75f3783>>o403:17d6?:188mg`=831d>9:50;9~f613290<6=4?{%0f1?42j2Bo595Gd6`8 75e2mom7)?j0;08m62=831b?84?::k02?6=3`936=44i9294?=njo0;66a=4583>>{e;>81<7950;2x 7c22;?i7Ej64:Jg3g=#::h1hhh4$0g3>7=n;=0;66g<5;29?l512900e>650;9j<5<722cij7>5;n070?6=3th8;=4?:683>5}#:l?1>8l4He;7?Mb0j2.9?o4keg9'5`6=:2c887>5;h16>5<<a:<1<75f3983>>o?83:17dli:188k7232900qo=9e;293?6=8r.9i84=5c9K`<2<@m=i7)<<b;ffb>"6m9097d=;:188m63=831b?;4?::k0<?6=3`2;6=44icd94?=h:=>1<75rb24`>5<0290;w)<j5;06f>Nc1=1Ch:l4$31a>aca3-;n<7<4i2694?=n;<0;66g<6;29?l5?2900e5>50;9jfc<722e9894?::a73g=83=1<7>t$3g6>73e3An286Fk7c9'66d=lll0(<k?:39j71<722c897>5;h15>5<<a:21<75f8183>>oen3:17b<;4;29?xd4>10;6:4?:1y'6`3=:<h0Di7;;If4f>"5;k0oik5+1d296>o4<3:17d=::188m60=831b?54?::k;4?6=3`hm6=44o367>5<<uk9=:7>57;294~"5m<099o5Gd868La1e3-88n7jjf:&2a5<53`9?6=44i2794?=n;?0;66g<8;29?l>72900eoh50;9l612=831vn>8;:184>5<7s-8n97<:b:Jg=1=Ol>h0(?=m:ege?!7b8380e>:50;9j70<722c8:7>5;h1;>5<<a1:1<75fbg83>>i5<=0;66sm37094?1=83:p(?k::37a?Mb><2Bo;o5+22`9```<,8o;6?5f3583>>o4=3:17d=9:188m6>=831b4=4?::kab?6=3f8?87>5;|`01`<72>0;6=u+2d7960d<@m3?7Ej8b:&17g<cmo1/=h>52:k00?6=3`9>6=44i2494?=n;10;66g70;29?lda2900c?:;:188yg52k3:1;7>50z&1a0<5=k1Ch4:4He5a?!44j3nnj6*>e181?l532900e>;50;9j73<722c847>5;h:3>5<<akl1<75`25694?=zj:?j6=48:183!4b=38>n6Fk959K`2d<,;9i6iki;%3f4?4<a:>1<75f3483>>o4>3:17d=7:188m=6=831bnk4?::m101<722wi?8650;594?6|,;o>6?;m;If:0>Nc?k1/>>l5ddd8 4c72;1b?94?::k01?6=3`9=6=44i2:94?=n090;66gmf;29?j43<3:17pl<5783>2<729q/>h;524`8La?33An<n6*=3c8gac=#9l:1>6g<4;29?l522900e>850;9j7=<722c3<7>5;h`e>5<<g;>?6=44}c160?6=?3:1<v*=e4811g=Ol0>0Di9m;%00f?bbn2.:i=4=;h17>5<<a:?1<75f3783>>o403:17d6?:188mg`=831d>9:50;9~f635290<6=4?{%0f1?42j2Bo595Gd6`8 75e2mom7)?j0;08m62=831b?84?::k02?6=3`936=44i9294?=njo0;66a=4583>>{e;<:1<7950;2x 7c22;?i7Ej64:Jg3g=#::h1hhh4$0g3>7=n;=0;66g<5;29?l512900e>650;9j<5<722cij7>5;n070?6=3th88h4?:683>5}#:l?1>8l4He;7?Mb0j2.9?o4keg9'5`6=:2c887>5;h16>5<<a:<1<75f3983>>o?83:17dli:188k7232900qo=;c;293?6=8r.9i84=5c9K`<2<@m=i7)<<b;ffb>"6m9097d=;:188m63=831b?;4?::k0<?6=3`2;6=44icd94?=h:=>1<75rb26;>5<0290;w)<j5;06f>Nc1=1Ch:l4$31a>aca3-;n<7<4i2694?=n;<0;66g<6;29?l5?2900e5>50;9jfc<722e9894?::a710=83=1<7>t$3g6>73e3An286Fk7c9'66d=lll0(<k?:39j71<722c897>5;h15>5<<a:21<75f8183>>oen3:17b<;4;29?xd4<=0;6:4?:1y'6`3=:<h0Di7;;If4f>"5;k0oik5+1d296>o4<3:17d=::188m60=831b?54?::k;4?6=3`hm6=44o367>5<<uk9?>7>57;294~"5m<099o5Gd868La1e3-88n7jjf:&2a5<53`9?6=44i2794?=n;?0;66g<8;29?l>72900eoh50;9l612=831vn>:?:184>5<7s-8n97<:b:Jg=1=Ol>h0(?=m:ege?!7b8380e>:50;9j70<722c8:7>5;h1;>5<<a1:1<75fbg83>>i5<=0;66sm32g94?1=83:p(?k::37a?Mb><2Bo;o5+22`9```<,8o;6?5f3583>>o4=3:17d=9:188m6>=831b4=4?::kab?6=3f8?87>5;|`07f<72>0;6=u+2d7960d<@m3?7Ej8b:&17g<cmo1/=h>52:k00?6=3`9>6=44i2494?=n;10;66g70;29?lda2900c?:;:188yg54i3:1;7>50z&1a0<5=k1Ch4:4He5a?!44j3nnj6*>e181?l532900e>;50;9j73<722c847>5;h:3>5<<akl1<75`25694?=zj:936=48:183!4b=38>n6Fk959K`2d<,;9i6iki;%3f4?4<a:>1<75f3483>>o4>3:17d=7:188m=6=831bnk4?::m101<722wi?>850;594?6|,;o>6?;m;If:0>Nc?k1/>>l5ddd8 4c72;1b?94?::k01?6=3`9=6=44i2:94?=n090;66gmf;29?j43<3:17pl<3383>2<729q/>h;524`8La?33An<n6*=3c8gac=#9l:1>6g<4;29?l522900e>850;9j7=<722c3<7>5;h`e>5<<g;>?6=44}c104?6=?3:1<v*=e4811g=Ol0>0Di9m;%00f?bbn2.:i=4=;h17>5<<a:?1<75f3783>>o403:17d6?:188mg`=831d>9:50;9~f64b290<6=4?{%0f1?42j2Bo595Gd6`8 75e2mom7)?j0;08m62=831b?84?::k02?6=3`936=44i9294?=njo0;66a=4583>>{e;;i1<7950;2x 7c22;?i7Ej64:Jg3g=#::h1hhh4$0g3>7=n;=0;66g<5;29?l512900e>650;9j<5<722cij7>5;n070?6=3th8>l4?:683>5}#:l?1>8l4He;7?Mb0j2.9?o4keg9'5`6=:2c887>5;h16>5<<a:<1<75f3983>>o?83:17dli:188k7232900qo==8;293?6=8r.9i84=5c9K`<2<@m=i7)<<b;ffb>"6m9097d=;:188m63=831b?;4?::k0<?6=3`2;6=44icd94?=h:=>1<75rb205>5<0290;w)<j5;06f>Nc1=1Ch:l4$31a>aca3-;n<7<4i2694?=n;<0;66g<6;29?l5?2900e5>50;9jfc<722e9894?::a772=83=1<7>t$3g6>73e3An286Fk7c9'66d=lll0(<k?:39j71<722c897>5;h15>5<<a:21<75f8183>>oen3:17b<;4;29?xd49;0;6:4?:1y'6`3=:<h0Di7;;If4f>"5;k0oik5+1d296>o4<3:17d=::188m60=831b?54?::k;4?6=3`hm6=44o367>5<<uk8mo7>57;294~"5m<099o5Gd868La1e3-88n7jjf:&2a5<53`9?6=44i2794?=n;?0;66g<8;29?l>72900eoh50;9l612=831vn>k;:184>5<7s-8n97<:b:Jg=1=Ol>h0(?=m:ege?!7b8380e>:50;9j70<722c8:7>5;h1;>5<<a1:1<75fbg83>>i5<=0;66sm3bg94?1=83:p(?k::37a?Mb><2Bo;o5+22`9```<,8o;6?5f3583>>o4=3:17d=9:188m6>=831b4=4?::kab?6=3f8?87>5;|`0f=<72>0;6=u+2d7960d<@m3?7Ej8b:&17g<cmo1/=h>52:k00?6=3`9>6=44i2494?=n;10;66g70;29?lda2900c?:;:188yg5f:3:1;7>50z&1a0<5=k1Ch4:4He5a?!44j3nnj6*>e181?l532900e>;50;9j73<722c847>5;h:3>5<<akl1<75`25694?=zj:2h6=48:183!4b=38>n6Fk959K`2d<,;9i6iki;%3f4?4<a:>1<75f3483>>o4>3:17d=7:188m=6=831bnk4?::m101<722wi?:850;594?6|,;o>6?;m;If:0>Nc?k1/>>l5ddd8 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75e2mom7)?j0;38m2d=831b;i4?::kab?6=3f8?87>5;|`;5=<72=0;6=u+2d795f6<@m3?7Ej8b:&17g<cmo1/=h>51:k4f?6=3`=o6=44icd94?=h:=>1<75rb935>5<3290;w)<j5;3`7>Nc1=1Ch:l4$31a>aca3-;n<7?4i6`94?=njo0;66g=4683>>i5<=0;66sm7g694?3=83:p(?k::0`e?Mb><2Bo;o5+22`9```<,8o;6<5f7c83>>o0l3:17d79:188mg`=831d>9:50;9~f2ca290?6=4?{%0f1?7d;2Bo595Gd6`8 75e2mom7)?j0;38m2d=831bnk4?::k102<722e9894?::a3c5=83?1<7>t$3g6>4da3An286Fk7c9'66d=lll0(<k?:09j3g<722c<h7>5;h;5>5<<akl1<75`25694?=zj>l96=4;:183!4b=3;h<6Fk959K`2d<,;9i6iki;%3f4?7<a>h1<75f7e83>>oen3:17b<;4;29?xd?>=0;694?:1y'6`3=9j:0Di7;;If4f>"5;k0oik5+1d295>o0j3:17d9k:188mg`=831d>9:50;9~f2cf290?6=4?{%0f1?45=2Bo595Gd6`8 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7c228i;7Ej64:Jg3g=#::h1hhh4$0g3>4=n?k0;66g8d;29?lda2900c?:;:188yg02<3:187>50z&1a0<6k91Ch4:4He5a?!44j3nnj6*>e182?l1e2900e:j50;9jfc<722e9894?::a205=83>1<7>t$3g6>4e73An286Fk7c9'66d=lll0(<k?:09j3g<722c<h7>5;h`e>5<<g;>?6=44}c466?6=<3:1<v*=e482g5=Ol0>0Di9m;%00f?bbn2.:i=4>;h5a>5<<a>n1<75fbg83>>i5<=0;66sm64394?2=83:p(?k::0a3?Mb><2Bo;o5+22`9```<,8o;6<5f7c83>>o0l3:17dli:188k7232900qo8:0;290?6=8r.9i84>c19K`<2<@m=i7)<<b;ffb>"6m90:7d9m:188m2b=831bnk4?::m101<722wi:9h50;694?6|,;o>6<m?;If:0>Nc?k1/>>l5ddd8 4c7281b;o4?::k4`?6=3`hm6=44o367>5<<uk<?i7>54;294~"5m<0:o=5Gd868La1e3-88n7jjf:&2a5<63`=i6=44i6f94?=njo0;66a=4583>>{e>==1<7:50;2x 7c228i;7Ej64:Jg3g=#::h1hhh4$0g3>4=n?k0;66g8d;29?lda2900c?:;:188yg00;3:187>50z&1a0<6k:1Ch4:4He5a?!44j3nnj6*>e182?l1e2900eoh50;9j611=831d>9:50;9~f312290?6=4?{%0f1?7d;2Bo595Gd6`8 75e2mom7)?j0;38m2d=831bnk4?::k102<722e9894?::a226=83>1<7>t$3g6>4e43An286Fk7c9'66d=lll0(<k?:09j3g<722cij7>5;h073?6=3f8?87>5;|`537<72=0;6=u+2d795f5<@m3?7Ej8b:&17g<cmo1/=h>51:k4f?6=3`hm6=44i364>5<<g;>?6=44}c45`?6=<3:1<v*=e482g6=Ol0>0Di9m;%00f?bbn2.:i=4>;h5a>5<<akl1<75f25594?=h:=>1<75rb74e>5<3290;w)<j5;3`7>Nc1=1Ch:l4$31a>aca3-;n<7?4i6`94?=njo0;66g=4683>>i5<=0;66sm67c94?2=83:p(?k::0a0?Mb><2Bo;o5+22`9```<,8o;6<5f7c83>>oen3:17d<;7;29?j43<3:17pl96b83>1<729q/>h;51b18La?33An<n6*=3c8gac=#9l:1=6g8b;29?lda2900e?:8:188k7232900qo897;290?6=8r.9i84>c29K`<2<@m=i7)<<b;ffb>"6m90:7d9m:188mg`=831b>9950;9l612=831vn;86:187>5<7s-8n97?l3:Jg=1=Ol>h0(?=m:ege?!7b83;0e:l50;9jfc<722c98:4?::m101<722wi:;:50;694?6|,;o>6<m<;If:0>Nc?k1/>>l5ddd8 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7272:n0b?=i:598yg15n3:1m7>50z&1a0<5=l1Ch4:4He5a?_1f28q8>7s+22`9```<,8o;695f8183>>oen3:17d9k:188k7232900c?:9:188m6c=83.98=4<d:l17c<732c8o7>5$363>6b<f;9m6<54i2`94?"5<908h6`=3g81?>o4i3:1(?:?:2f8j75a2:10e>750;&105<4l2d9?k4;;:a366=8331<7>t$3g6>73c3An286Fk7c9'66d=lll0(<k?:39j71<722c897>5;h15>5<<a:21<75f7e83>>o?83:17dli:188k7232900c?:::188yg16<3:187>50z&1a0<5;91Ch4:4He5a?!44j3nnj6g8f;29?le42900e?;;:188k7402900qo9>5;290?6=8r.9i84=319K`<2<@m=i7)<<b;ffb>o0n3:17dm<:188m7332900c?<8:188yg16>3:187>50z&1a0<5;91Ch4:4He5a?!44j3nnj6g8f;29?le42900e?;;:188k7402900qo9>7;290?6=8r.9i84=319K`<2<@m=i7)<<b;ffb>o0n3:17dm<:188m7332900c?<8:188yg1603:187>50z&1a0<5;91Ch4:4He5a?!44j3nnj6g8f;29?le42900e?;;:188k7402900qo9>9;29e?6=8r.9i84=5d9K`<2<@m=i7W9n:0y06?{#::h1hhh4$0g3>1=n090;66gmf;29?l1c2900c?:;:188k7212900e>k50;&105<4l2d9?k4?;:k0g?6=,;>;6>j4n31e>4=<a:h1<7*=4180`>h5;o0976g<a;29 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4c728i0e<j=:188k75f2900qo:8c;291?6=8r.9i84>c59K`<2<@m=i7)<<b;ffb>"6m90:7d9m:188m2b=831bnk4?::k102<722e9894?::a0=6=83?1<7>t$3g6>4e33An286Fk7c9'66d=lll0(<k?:09j3g<722c<h7>5;h`e>5<<a;><6=44o367>5<<uk>387>55;294~"5m<0:o95Gd868La1e3-88n7jjf:&2a5<63`=i6=44i6f94?=njo0;66g=4683>>i5<=0;66sm49:94?3=83:p(?k::0a7?Mb><2Bo;o5+22`9```<,8o;6<5f7c83>>o0l3:17dli:188m7202900c?:;:188yg2?k3:197>50z&1a0<6k=1Ch4:4He5a?!44j3nnj6*>e182?l1e2900e:j50;9jfc<722c98:4?::m101<722wi84>50;794?6|,;o>6<m;;If:0>Nc?k1/>>l5ddd8 4c7281b;o4?::k4`?6=3`hm6=44i364>5<<g;>?6=44}c6:0?6==3:1<v*=e482g1=Ol0>0Di9m;%00f?bbn2.:i=4>;h5a>5<<a>n1<75fbg83>>o5<>0;66a=4583>>{e<0=1<7;50;2x 7c228i?7Ej64:Jg3g=#::h1hhh4$0g3>4=n?k0;66g8d;29?lda2900e?:8:188k7232900qo:n3;291?6=8r.9i84>c59K`<2<@m=i7)<<b;ffb>"6m90:7d9m:188m2b=831bnk4?::k102<722e9894?::a0d2=83?1<7>t$3g6>4e33An286Fk7c9'66d=lll0(<k?:09j3g<722c<h7>5;h`e>5<<a;><6=44o367>5<<uk>j97>55;294~"5m<0:o95Gd868La1e3-88n7jjf:&2a5<63`=i6=44i6f94?=njo0;66g=4683>>i5<=0;66sm4`494?3=83:p(?k::0a7?Mb><2Bo;o5+22`9```<,8o;6<5f7c83>>o0l3:17dli:188m7202900c?:;:188yg2f?3:197>50z&1a0<6k=1Ch4:4He5a?!44j3nnj6*>e182?l1e2900e:j50;9jfc<722c98:4?::m101<722wi8l650;794?6|,;o>6<m;;If:0>Nc?k1/>>l5ddd8 4c7281b;o4?::k4`?6=3`hm6=44i364>5<<g;>?6=44}c6b=?6==3:1<v*=e482g1=Ol0>0Di9m;%00f?bbn2.:i=4>;h5a>5<<a>n1<75fbg83>>o5<>0;66a=4583>>{e<hk1<7;50;2x 7c228i?7Ej64:Jg3g=#::h1hhh4$0g3>4=n?k0;66g8d;29?lda2900e?:8:188k7232900qo9k5;290?6=8r.9i84=2b9K`<2<@m=i7)?j0;3bb>o6l;0;66g>d283>>o6l=0;66a=3`83>>{e=?:1<7850;2x 7c22;8n7Ej64:Jg3g=#9l:146g>d383>>o6l:0;66g>d583>>o6l<0;66g>d783>>i5;h0;66sm57394?3=83:p(?k::30g?Mb><2Bo;o5+1d29`>o6l;0;66g>d283>>o6l=0;66g>d483>>i5;h0;66sm57094?1=83:p(?k::30e?Mb><2Bo;o5+1d29a>o6l;0;66g>d283>>o6l=0;66g>d483>>o6l?0;66g>d683>>i5;h0;66sm57194?1=83:p(?k::30e?Mb><2Bo;o5+1d29a>o6l;0;66g>d283>>o6l=0;66g>d483>>o6l?0;66g>d683>>i5;h0;66sm57694?0=83:p(?k::30f?Mb><2Bo;o5+1d295fg<a8n96=44i0f0>5<<a8n?6=44i0f6>5<<a8n=6=44o31b>5<<uk2;?7>57;294~"5m<09>k5Gd868La1e3-;n<7?l7:k2`7<722c:h>4?::k2`1<722c:h84?::k2`3<722c:h:4?::m17d<722wi4=m50;194?6|,;o>6?<m;If:0>Nc?k1/=h>5109j5a4=831b=i=50;9l66g=831vn5>k:184>5<7s-8n97<=f:Jg=1=Ol>h0(<k?:0`:?l7c:3:17d?k3;29?l7c<3:17d?k5;29?l7c>3:17d?k7;29?j44i3:17pl71383>3<729q/>h;523g8La?33An<n6*>e18`4>o6l;0;66g>d283>>o6l=0;66g>d483>>o6l?0;66a=3`83>>{e0891<7950;2x 7c22;8m7Ej64:Jg3g=#9l:1=nk4i0f1>5<<a8n86=44i0f7>5<<a8n>6=44i0f5>5<<a8n<6=44o31b>5<<uk2:87>57;294~"5m<09>k5Gd868La1e3-;n<7m4i0f1>5<<a8n86=44i0f7>5<<a8n>6=44i0f5>5<<a8n<6=44o31b>5<<uk2;47>57;294~"5m<09>k5Gd868La1e3-;n<7?ld:k2`7<722c:h>4?::k2`1<722c:h84?::k2`3<722c:h:4?::m17d<722wi4=750;694?6|,;o>6?<l;If:0>Nc?k1/=h>51`d8m4b52900e<j<:188m4b32900c?=n:188yg>7j3:1;7>50z&1a0<5:o1Ch4:4He5a?!7b83=27d?k2;29?l7c;3:17d?k4;29?l7c=3:17d?k6;29?l7c?3:17b<<a;29?xd0nl0;694?:1y'6`3=9j90Di7;;If4f>"5;k0oik5+1d295>o0j3:17dli:188m7202900c?:;:188yg>783:187>50z&1a0<6k:1Ch4:4He5a?!44j3nnj6*>e182?l1e2900eoh50;9j611=831d>9:50;9~f=6629086=4?{%0f1?45j2Bo595Gd6`8 4c728kn7)<;1;fb4>o6l;0;66g>d283>>i5;h0;66sm87794?2=83:p(?k::0a0?Mb><2Bo;o5+22`9```<,8o;6<5f7c83>>oen3:17d<;7;29?j43<3:17pl76783>6<729q/>h;523`8La?33An<n6*>e182e`=n9m81<75f1e194?=h::k1<75rb6g6>5<3290;w)<j5;3`7>Nc1=1Ch:l4$31a>aca3-;n<7?4i6`94?=njo0;66g=4683>>i5<=0;66sm7d494?5=83:p(?k::30a?Mb><2Bo;o5+1d295dc<a8n96=44i0f0>5<<g;9j6=44}c:24?6=>3:1<v*=e4816`=Ol0>0Di9m;%3f4?7d92c:h?4?::k2`6<722c:h94?::k2`0<722c:h;4?::m17d<722wi4<?50;794?6|,;o>6?<k;If:0>Nc?k1/=h>51b48m4b52900e<j<:188m4b32900e<j::188k75f2900qo6?f;293?6=8r.9i84=2g9K`<2<@m=i7)?j0;3`g>o6l;0;66g>d283>>o6l=0;66g>d483>>o6l?0;66g>d683>>i5;h0;66smbe394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66smc8;94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek021<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc8594?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek0<1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc8794?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek0>1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc8194?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek081<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc8294?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek1l1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc9g94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek1n1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc9a94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek1h1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc9c94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek131<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc9:94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek1=1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc9794?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek1>1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc9194?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek181<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc9394?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek1:1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc6d94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek>o1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc6f94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek>i1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcg;94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{eko21<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcg594?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{eko<1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcg794?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{eko>1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcg194?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{eko81<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcg394?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{eko:1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcdg94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekln1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcda94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{eklh1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcdc94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekl31<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcd:94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekl=1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcd494?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekl?1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcd194?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekl81<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcd394?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekl:1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smced94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekmo1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcef94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekmi1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smce`94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekmk1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smce:94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekm=1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smce494?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekm?1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smce694?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekm91<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smce094?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekm;1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smce294?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekjl1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcbf94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekji1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcb`94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekjk1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcb;94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekj21<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcb594?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekj<1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcb794?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekj>1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcb094?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekj;1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcb294?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekkl1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smccg94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekkn1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcca94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekkh1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smccc94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekk31<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcc594?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekk<1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcc794?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekk>1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcc194?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekk81<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcc394?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekk:1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc`d94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekho1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc`a94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekhh1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc`c94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekh31<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc`:94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekh=1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc`494?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekh?1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc`694?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekh91<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc`394?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekh:1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc8d94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek0o1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc8f94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek0i1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc8`94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek0k1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc8394?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek1<1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcgc94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekll1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcd694?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekm31<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcbg94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekj91<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcc:94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekhn1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc`094?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek>h1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66sm91d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm89d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8ba94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8df94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8cc94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8ca94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8cf94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8cg94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8cd94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8bc94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8bf94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8bg94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8bd94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8ec94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8ea94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8ef94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8eg94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8ed94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8dc94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8da94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8dg94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8dd94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8gc94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8ga94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8gf94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8gg94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8gd94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8``94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm7g294?2=83:p(?k::0`f?Mb><2Bo;o5+1d295>"5;k0oik5f7c83>>o>>3:17dli:188k7232900qo9i1;290?6=8r.9i84>bd9K`<2<@m=i7)?j0;38 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ucf new file mode 100644 index 000000000..736db76a7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ucf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_chipscope_ila_128 = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.v b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.v new file mode 100644 index 000000000..20690c1dd --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.v @@ -0,0 +1,31 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_ila_128.v +// /___/ /\ Timestamp : Fri Mar 08 11:53:53 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: Verilog Synthesis Wrapper +/////////////////////////////////////////////////////////////////////////////// +// This wrapper is used to integrate with Project Navigator and PlanAhead + +`timescale 1ns/1ps + +module chipscope_ila_128( + CONTROL, + CLK, + TRIG0) /* synthesis syn_black_box syn_noprune=1 */; + + +inout [35 : 0] CONTROL; +input CLK; +input [127 : 0] TRIG0; + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.veo b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.veo new file mode 100644 index 000000000..ba0ec8116 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.veo @@ -0,0 +1,30 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_ila_128.veo +// /___/ /\ Timestamp : Fri Mar 08 11:53:53 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: ISE Instantiation template +/////////////////////////////////////////////////////////////////////////////// + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +chipscope_ila_128 YourInstanceName ( + .CONTROL(CONTROL), // INOUT BUS [35:0] + .CLK(CLK), // IN + .TRIG0(TRIG0) // IN BUS [127:0] +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xco b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xco new file mode 100644 index 000000000..41a6a11be --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xco @@ -0,0 +1,141 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Fri Mar 8 19:52:17 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a +# END Select +# BEGIN Parameters +CSET check_bramcount=false +CSET component_name=chipscope_ila_128 +CSET constraint_type=external +CSET counter_width_1=Disabled +CSET counter_width_10=Disabled +CSET counter_width_11=Disabled +CSET counter_width_12=Disabled +CSET counter_width_13=Disabled +CSET counter_width_14=Disabled +CSET counter_width_15=Disabled +CSET counter_width_16=Disabled +CSET counter_width_2=Disabled +CSET counter_width_3=Disabled +CSET counter_width_4=Disabled +CSET counter_width_5=Disabled +CSET counter_width_6=Disabled +CSET counter_width_7=Disabled +CSET counter_width_8=Disabled +CSET counter_width_9=Disabled +CSET data_port_width=0 +CSET data_same_as_trigger=true +CSET disable_save_keep=false +CSET enable_storage_qualification=true +CSET enable_trigger_output_port=false +CSET example_design=false +CSET exclude_from_data_storage_1=false +CSET exclude_from_data_storage_10=false +CSET exclude_from_data_storage_11=false +CSET exclude_from_data_storage_12=false +CSET exclude_from_data_storage_13=false +CSET exclude_from_data_storage_14=false +CSET exclude_from_data_storage_15=false +CSET exclude_from_data_storage_16=false +CSET exclude_from_data_storage_2=false +CSET exclude_from_data_storage_3=false +CSET exclude_from_data_storage_4=false +CSET exclude_from_data_storage_5=false +CSET exclude_from_data_storage_6=false +CSET exclude_from_data_storage_7=false +CSET exclude_from_data_storage_8=false +CSET exclude_from_data_storage_9=false +CSET match_type_1=basic_with_edges +CSET match_type_10=basic_with_edges +CSET match_type_11=basic_with_edges +CSET match_type_12=basic_with_edges +CSET match_type_13=basic_with_edges +CSET match_type_14=basic_with_edges +CSET match_type_15=basic_with_edges +CSET match_type_16=basic_with_edges +CSET match_type_2=basic_with_edges +CSET match_type_3=basic_with_edges +CSET match_type_4=basic_with_edges +CSET match_type_5=basic_with_edges +CSET match_type_6=basic_with_edges +CSET match_type_7=basic_with_edges +CSET match_type_8=basic_with_edges +CSET match_type_9=basic_with_edges +CSET match_units_1=1 +CSET match_units_10=1 +CSET match_units_11=1 +CSET match_units_12=1 +CSET match_units_13=1 +CSET match_units_14=1 +CSET match_units_15=1 +CSET match_units_16=1 +CSET match_units_2=1 +CSET match_units_3=1 +CSET match_units_4=1 +CSET match_units_5=1 +CSET match_units_6=1 +CSET match_units_7=1 +CSET match_units_8=1 +CSET match_units_9=1 +CSET max_sequence_levels=1 +CSET number_of_trigger_ports=1 +CSET sample_data_depth=1024 +CSET sample_on=Rising +CSET trigger_port_width_1=128 +CSET trigger_port_width_10=8 +CSET trigger_port_width_11=8 +CSET trigger_port_width_12=8 +CSET trigger_port_width_13=8 +CSET trigger_port_width_14=8 +CSET trigger_port_width_15=8 +CSET trigger_port_width_16=8 +CSET trigger_port_width_2=8 +CSET trigger_port_width_3=8 +CSET trigger_port_width_4=8 +CSET trigger_port_width_5=8 +CSET trigger_port_width_6=8 +CSET trigger_port_width_7=8 +CSET trigger_port_width_8=8 +CSET trigger_port_width_9=8 +CSET use_rpms=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T02:47:40Z +# END Extra information +GENERATE +# CRC: 194c140a diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise new file mode 100644 index 000000000..b5d414354 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise @@ -0,0 +1,73 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="chipscope_ila_128.ngc" xil_pn:type="FILE_NGC"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="chipscope_ila_128.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/> + </file> + </files> + + <properties> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> + <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Module|chipscope_ila_128" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top File" xil_pn:value="chipscope_ila_128.ngc" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/chipscope_ila_128" xil_pn:valueState="non-default"/> + <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_ila_128" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-08T11:53:54" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9340B6BAD141C451B74411D3998AD5A4" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128_flist.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_flist.txt new file mode 100644 index 000000000..7ee610500 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_flist.txt @@ -0,0 +1,18 @@ +# Output products list for <chipscope_ila_128> +_xmsgs/pn_parser.xmsgs +chipscope_ila_128.asy +chipscope_ila_128.cdc +chipscope_ila_128.constraints/chipscope_ila_128.ucf +chipscope_ila_128.constraints/chipscope_ila_128.xdc +chipscope_ila_128.gise +chipscope_ila_128.ncf +chipscope_ila_128.ngc +chipscope_ila_128.ucf +chipscope_ila_128.v +chipscope_ila_128.veo +chipscope_ila_128.xco +chipscope_ila_128.xdc +chipscope_ila_128.xise +chipscope_ila_128_flist.txt +chipscope_ila_128_readme.txt +chipscope_ila_128_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128_readme.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_readme.txt new file mode 100644 index 000000000..395331e42 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_readme.txt @@ -0,0 +1,48 @@ +The following files were generated for 'chipscope_ila_128' in directory +/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/ + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * chipscope_ila_128.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * chipscope_ila_128.cdc + * chipscope_ila_128.constraints/chipscope_ila_128.ucf + * chipscope_ila_128.constraints/chipscope_ila_128.xdc + * chipscope_ila_128.ncf + * chipscope_ila_128.ngc + * chipscope_ila_128.ucf + * chipscope_ila_128.v + * chipscope_ila_128.veo + * chipscope_ila_128.xdc + * chipscope_ila_128_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * chipscope_ila_128.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * _xmsgs/pn_parser.xmsgs + * chipscope_ila_128.gise + * chipscope_ila_128.xise + +Deliver Readme: + Readme file for the IP. + + * chipscope_ila_128_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * chipscope_ila_128_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128_xmdf.tcl b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_xmdf.tcl new file mode 100755 index 000000000..e4af2b327 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_xmdf.tcl @@ -0,0 +1,87 @@ +# The package naming convention is <core_name>_xmdf +package provide chipscope_ila_128_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is <core_name>_xmdf +namespace eval ::chipscope_ila_128_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::chipscope_ila_128_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: <module_name> +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_ila_128 +} +# ::chipscope_ila_128_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::chipscope_ila_128_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.cdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.constraints/chipscope_ila_128.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.constraints/chipscope_ila_128.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_ila_128 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.asy b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.asy new file mode 100644 index 000000000..3eef48558 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 chipscope_ila_256 +RECTANGLE Normal 32 32 288 704 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName control[35:0] +PINATTR Polarity IN +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Wide 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName trig0[255:0] +PINATTR Polarity IN + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.cdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.cdc new file mode 100644 index 000000000..562f53ff9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.cdc @@ -0,0 +1,272 @@ +#ChipScope Core Generator Project File Version 3.0 +#Fri Mar 08 16:13:02 PST 2013 +SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 +SignalExport.bus<0000>.name=TRIG0 +SignalExport.bus<0000>.offset=0.0 +SignalExport.bus<0000>.precision=0 +SignalExport.bus<0000>.radix=Bin +SignalExport.bus<0000>.scaleFactor=1.0 +SignalExport.clockChannel=CLK +SignalExport.dataEqualsTrigger=true +SignalExport.triggerChannel<0000><0000>=TRIG0[0] +SignalExport.triggerChannel<0000><0001>=TRIG0[1] +SignalExport.triggerChannel<0000><0002>=TRIG0[2] +SignalExport.triggerChannel<0000><0003>=TRIG0[3] +SignalExport.triggerChannel<0000><0004>=TRIG0[4] +SignalExport.triggerChannel<0000><0005>=TRIG0[5] +SignalExport.triggerChannel<0000><0006>=TRIG0[6] +SignalExport.triggerChannel<0000><0007>=TRIG0[7] +SignalExport.triggerChannel<0000><0008>=TRIG0[8] +SignalExport.triggerChannel<0000><0009>=TRIG0[9] +SignalExport.triggerChannel<0000><0010>=TRIG0[10] +SignalExport.triggerChannel<0000><0011>=TRIG0[11] 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+SignalExport.type=ila + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.ucf new file mode 100644 index 000000000..b458eed9c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.ucf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_chipscope_ila_256 = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise new file mode 100644 index 000000000..6305e6288 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise @@ -0,0 +1,31 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="chipscope_ila_256.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="chipscope_ila_256.asy" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="chipscope_ila_256.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ncf b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ncf new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ncf diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ngc b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ngc new file mode 100644 index 000000000..e6dfef4e8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ucf new file mode 100644 index 000000000..b458eed9c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ucf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_chipscope_ila_256 = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.v b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.v new file mode 100644 index 000000000..2f0ec9349 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.v @@ -0,0 +1,31 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_ila_256.v +// /___/ /\ Timestamp : Fri Mar 08 16:13:02 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: Verilog Synthesis Wrapper +/////////////////////////////////////////////////////////////////////////////// +// This wrapper is used to integrate with Project Navigator and PlanAhead + +`timescale 1ns/1ps + +module chipscope_ila_256( + CONTROL, + CLK, + TRIG0) /* synthesis syn_black_box syn_noprune=1 */; + + +inout [35 : 0] CONTROL; +input CLK; +input [255 : 0] TRIG0; + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.veo b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.veo new file mode 100644 index 000000000..201512ffb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.veo @@ -0,0 +1,30 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_ila_256.veo +// /___/ /\ Timestamp : Fri Mar 08 16:13:02 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: ISE Instantiation template +/////////////////////////////////////////////////////////////////////////////// + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +chipscope_ila_256 YourInstanceName ( + .CONTROL(CONTROL), // INOUT BUS [35:0] + .CLK(CLK), // IN + .TRIG0(TRIG0) // IN BUS [255:0] +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xco b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xco new file mode 100644 index 000000000..4272296fc --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xco @@ -0,0 +1,141 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Sat Mar 9 00:11:24 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a +# END Select +# BEGIN Parameters +CSET check_bramcount=false +CSET component_name=chipscope_ila_256 +CSET constraint_type=external +CSET counter_width_1=Disabled +CSET counter_width_10=Disabled +CSET counter_width_11=Disabled +CSET counter_width_12=Disabled +CSET counter_width_13=Disabled +CSET counter_width_14=Disabled +CSET counter_width_15=Disabled +CSET counter_width_16=Disabled +CSET counter_width_2=Disabled +CSET counter_width_3=Disabled +CSET counter_width_4=Disabled +CSET counter_width_5=Disabled +CSET counter_width_6=Disabled +CSET counter_width_7=Disabled +CSET counter_width_8=Disabled +CSET counter_width_9=Disabled +CSET data_port_width=0 +CSET data_same_as_trigger=true +CSET disable_save_keep=false +CSET enable_storage_qualification=true +CSET enable_trigger_output_port=false +CSET example_design=false +CSET exclude_from_data_storage_1=false +CSET exclude_from_data_storage_10=false +CSET exclude_from_data_storage_11=false +CSET exclude_from_data_storage_12=false +CSET exclude_from_data_storage_13=false +CSET exclude_from_data_storage_14=false +CSET exclude_from_data_storage_15=false +CSET exclude_from_data_storage_16=false +CSET exclude_from_data_storage_2=false +CSET exclude_from_data_storage_3=false +CSET exclude_from_data_storage_4=false +CSET exclude_from_data_storage_5=false +CSET exclude_from_data_storage_6=false +CSET exclude_from_data_storage_7=false +CSET exclude_from_data_storage_8=false +CSET exclude_from_data_storage_9=false +CSET match_type_1=basic_with_edges +CSET match_type_10=basic_with_edges +CSET match_type_11=basic_with_edges +CSET match_type_12=basic_with_edges +CSET match_type_13=basic_with_edges +CSET match_type_14=basic_with_edges +CSET match_type_15=basic_with_edges +CSET match_type_16=basic_with_edges +CSET match_type_2=basic_with_edges +CSET match_type_3=basic_with_edges +CSET match_type_4=basic_with_edges +CSET match_type_5=basic_with_edges +CSET match_type_6=basic_with_edges +CSET match_type_7=basic_with_edges +CSET match_type_8=basic_with_edges +CSET match_type_9=basic_with_edges +CSET match_units_1=1 +CSET match_units_10=1 +CSET match_units_11=1 +CSET match_units_12=1 +CSET match_units_13=1 +CSET match_units_14=1 +CSET match_units_15=1 +CSET match_units_16=1 +CSET match_units_2=1 +CSET match_units_3=1 +CSET match_units_4=1 +CSET match_units_5=1 +CSET match_units_6=1 +CSET match_units_7=1 +CSET match_units_8=1 +CSET match_units_9=1 +CSET max_sequence_levels=1 +CSET number_of_trigger_ports=1 +CSET sample_data_depth=1024 +CSET sample_on=Rising +CSET trigger_port_width_1=256 +CSET trigger_port_width_10=8 +CSET trigger_port_width_11=8 +CSET trigger_port_width_12=8 +CSET trigger_port_width_13=8 +CSET trigger_port_width_14=8 +CSET trigger_port_width_15=8 +CSET trigger_port_width_16=8 +CSET trigger_port_width_2=8 +CSET trigger_port_width_3=8 +CSET trigger_port_width_4=8 +CSET trigger_port_width_5=8 +CSET trigger_port_width_6=8 +CSET trigger_port_width_7=8 +CSET trigger_port_width_8=8 +CSET trigger_port_width_9=8 +CSET use_rpms=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T02:47:40Z +# END Extra information +GENERATE +# CRC: b8a8f4bd diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise new file mode 100644 index 000000000..f8c51bac1 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise @@ -0,0 +1,73 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="chipscope_ila_256.ngc" xil_pn:type="FILE_NGC"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="chipscope_ila_256.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/> + </file> + </files> + + <properties> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> + <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Module|chipscope_ila_256" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top File" xil_pn:value="chipscope_ila_256.ngc" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/chipscope_ila_256" xil_pn:valueState="non-default"/> + <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_ila_256" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-08T16:13:04" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="2F48FC702B99E05DB4E13DA9BB134584" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256_flist.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_flist.txt new file mode 100644 index 000000000..da4f99bbe --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_flist.txt @@ -0,0 +1,18 @@ +# Output products list for <chipscope_ila_256> +_xmsgs/pn_parser.xmsgs +chipscope_ila_256.asy +chipscope_ila_256.cdc +chipscope_ila_256.constraints/chipscope_ila_256.ucf +chipscope_ila_256.constraints/chipscope_ila_256.xdc +chipscope_ila_256.gise +chipscope_ila_256.ncf +chipscope_ila_256.ngc +chipscope_ila_256.ucf +chipscope_ila_256.v +chipscope_ila_256.veo +chipscope_ila_256.xco +chipscope_ila_256.xdc +chipscope_ila_256.xise +chipscope_ila_256_flist.txt +chipscope_ila_256_readme.txt +chipscope_ila_256_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256_readme.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_readme.txt new file mode 100644 index 000000000..764247d3b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_readme.txt @@ -0,0 +1,53 @@ +The following files were generated for 'chipscope_ila_256' in directory +/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/ + +ISE file generator: + Add description here... + + * chipscope_ila_32_flist.txt + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * chipscope_ila_256.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * chipscope_ila_256.cdc + * chipscope_ila_256.constraints/chipscope_ila_256.ucf + * chipscope_ila_256.constraints/chipscope_ila_256.xdc + * chipscope_ila_256.ncf + * chipscope_ila_256.ngc + * chipscope_ila_256.ucf + * chipscope_ila_256.v + * chipscope_ila_256.veo + * chipscope_ila_256.xdc + * chipscope_ila_256_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * chipscope_ila_256.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * _xmsgs/pn_parser.xmsgs + * chipscope_ila_256.gise + * chipscope_ila_256.xise + +Deliver Readme: + Readme file for the IP. + + * chipscope_ila_256_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * chipscope_ila_256_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256_xmdf.tcl b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_xmdf.tcl new file mode 100755 index 000000000..1fb67dd98 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_xmdf.tcl @@ -0,0 +1,87 @@ +# The package naming convention is <core_name>_xmdf +package provide chipscope_ila_256_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is <core_name>_xmdf +namespace eval ::chipscope_ila_256_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::chipscope_ila_256_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: <module_name> +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_ila_256 +} +# ::chipscope_ila_256_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::chipscope_ila_256_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.cdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.constraints/chipscope_ila_256.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.constraints/chipscope_ila_256.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_ila_256 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.asy b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.asy new file mode 100644 index 000000000..69e989c04 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 chipscope_ila_32 +RECTANGLE Normal 32 32 288 704 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName control[35:0] +PINATTR Polarity IN +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Wide 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName trig0[31:0] +PINATTR Polarity IN + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.cdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.cdc new file mode 100644 index 000000000..d0ba2170c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.cdc @@ -0,0 +1,48 @@ +#ChipScope Core Generator Project File Version 3.0 +#Fri Mar 08 11:59:29 PST 2013 +SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 +SignalExport.bus<0000>.name=TRIG0 +SignalExport.bus<0000>.offset=0.0 +SignalExport.bus<0000>.precision=0 +SignalExport.bus<0000>.radix=Bin +SignalExport.bus<0000>.scaleFactor=1.0 +SignalExport.clockChannel=CLK +SignalExport.dataEqualsTrigger=true +SignalExport.triggerChannel<0000><0000>=TRIG0[0] +SignalExport.triggerChannel<0000><0001>=TRIG0[1] +SignalExport.triggerChannel<0000><0002>=TRIG0[2] +SignalExport.triggerChannel<0000><0003>=TRIG0[3] +SignalExport.triggerChannel<0000><0004>=TRIG0[4] +SignalExport.triggerChannel<0000><0005>=TRIG0[5] +SignalExport.triggerChannel<0000><0006>=TRIG0[6] +SignalExport.triggerChannel<0000><0007>=TRIG0[7] +SignalExport.triggerChannel<0000><0008>=TRIG0[8] +SignalExport.triggerChannel<0000><0009>=TRIG0[9] +SignalExport.triggerChannel<0000><0010>=TRIG0[10] +SignalExport.triggerChannel<0000><0011>=TRIG0[11] +SignalExport.triggerChannel<0000><0012>=TRIG0[12] +SignalExport.triggerChannel<0000><0013>=TRIG0[13] +SignalExport.triggerChannel<0000><0014>=TRIG0[14] +SignalExport.triggerChannel<0000><0015>=TRIG0[15] +SignalExport.triggerChannel<0000><0016>=TRIG0[16] +SignalExport.triggerChannel<0000><0017>=TRIG0[17] +SignalExport.triggerChannel<0000><0018>=TRIG0[18] +SignalExport.triggerChannel<0000><0019>=TRIG0[19] +SignalExport.triggerChannel<0000><0020>=TRIG0[20] +SignalExport.triggerChannel<0000><0021>=TRIG0[21] +SignalExport.triggerChannel<0000><0022>=TRIG0[22] +SignalExport.triggerChannel<0000><0023>=TRIG0[23] +SignalExport.triggerChannel<0000><0024>=TRIG0[24] +SignalExport.triggerChannel<0000><0025>=TRIG0[25] +SignalExport.triggerChannel<0000><0026>=TRIG0[26] +SignalExport.triggerChannel<0000><0027>=TRIG0[27] +SignalExport.triggerChannel<0000><0028>=TRIG0[28] +SignalExport.triggerChannel<0000><0029>=TRIG0[29] +SignalExport.triggerChannel<0000><0030>=TRIG0[30] +SignalExport.triggerChannel<0000><0031>=TRIG0[31] +SignalExport.triggerPort<0000>.name=TRIG0 +SignalExport.triggerPortCount=1 +SignalExport.triggerPortIsData<0000>=true +SignalExport.triggerPortWidth<0000>=32 +SignalExport.type=ila + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.ucf new file mode 100644 index 000000000..228071c37 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.ucf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_chipscope_ila_32 = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise new file mode 100644 index 000000000..4bc01d034 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise @@ -0,0 +1,31 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="chipscope_ila_32.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="chipscope_ila_32.asy" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="chipscope_ila_32.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ncf b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ncf new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ncf diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ngc b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ngc new file mode 100644 index 000000000..29677d942 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ucf new file mode 100644 index 000000000..228071c37 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ucf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_chipscope_ila_32 = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.v b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.v new file mode 100644 index 000000000..5c409080b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.v @@ -0,0 +1,31 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_ila_32.v +// /___/ /\ Timestamp : Fri Mar 08 11:59:29 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: Verilog Synthesis Wrapper +/////////////////////////////////////////////////////////////////////////////// +// This wrapper is used to integrate with Project Navigator and PlanAhead + +`timescale 1ns/1ps + +module chipscope_ila_32( + CONTROL, + CLK, + TRIG0) /* synthesis syn_black_box syn_noprune=1 */; + + +inout [35 : 0] CONTROL; +input CLK; +input [31 : 0] TRIG0; + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.veo b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.veo new file mode 100644 index 000000000..c949fbe7f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.veo @@ -0,0 +1,30 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_ila_32.veo +// /___/ /\ Timestamp : Fri Mar 08 11:59:29 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: ISE Instantiation template +/////////////////////////////////////////////////////////////////////////////// + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +chipscope_ila_32 YourInstanceName ( + .CONTROL(CONTROL), // INOUT BUS [35:0] + .CLK(CLK), // IN + .TRIG0(TRIG0) // IN BUS [31:0] +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xco b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xco new file mode 100644 index 000000000..15047431b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xco @@ -0,0 +1,141 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Fri Mar 8 19:57:57 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a +# END Select +# BEGIN Parameters +CSET check_bramcount=false +CSET component_name=chipscope_ila_32 +CSET constraint_type=external +CSET counter_width_1=Disabled +CSET counter_width_10=Disabled +CSET counter_width_11=Disabled +CSET counter_width_12=Disabled +CSET counter_width_13=Disabled +CSET counter_width_14=Disabled +CSET counter_width_15=Disabled +CSET counter_width_16=Disabled +CSET counter_width_2=Disabled +CSET counter_width_3=Disabled +CSET counter_width_4=Disabled +CSET counter_width_5=Disabled +CSET counter_width_6=Disabled +CSET counter_width_7=Disabled +CSET counter_width_8=Disabled +CSET counter_width_9=Disabled +CSET data_port_width=0 +CSET data_same_as_trigger=true +CSET disable_save_keep=false +CSET enable_storage_qualification=true +CSET enable_trigger_output_port=false +CSET example_design=false +CSET exclude_from_data_storage_1=false +CSET exclude_from_data_storage_10=false +CSET exclude_from_data_storage_11=false +CSET exclude_from_data_storage_12=false +CSET exclude_from_data_storage_13=false +CSET exclude_from_data_storage_14=false +CSET exclude_from_data_storage_15=false +CSET exclude_from_data_storage_16=false +CSET exclude_from_data_storage_2=false +CSET exclude_from_data_storage_3=false +CSET exclude_from_data_storage_4=false +CSET exclude_from_data_storage_5=false +CSET exclude_from_data_storage_6=false +CSET exclude_from_data_storage_7=false +CSET exclude_from_data_storage_8=false +CSET exclude_from_data_storage_9=false +CSET match_type_1=basic_with_edges +CSET match_type_10=basic_with_edges +CSET match_type_11=basic_with_edges +CSET match_type_12=basic_with_edges +CSET match_type_13=basic_with_edges +CSET match_type_14=basic_with_edges +CSET match_type_15=basic_with_edges +CSET match_type_16=basic_with_edges +CSET match_type_2=basic_with_edges +CSET match_type_3=basic_with_edges +CSET match_type_4=basic_with_edges +CSET match_type_5=basic_with_edges +CSET match_type_6=basic_with_edges +CSET match_type_7=basic_with_edges +CSET match_type_8=basic_with_edges +CSET match_type_9=basic_with_edges +CSET match_units_1=1 +CSET match_units_10=1 +CSET match_units_11=1 +CSET match_units_12=1 +CSET match_units_13=1 +CSET match_units_14=1 +CSET match_units_15=1 +CSET match_units_16=1 +CSET match_units_2=1 +CSET match_units_3=1 +CSET match_units_4=1 +CSET match_units_5=1 +CSET match_units_6=1 +CSET match_units_7=1 +CSET match_units_8=1 +CSET match_units_9=1 +CSET max_sequence_levels=1 +CSET number_of_trigger_ports=1 +CSET sample_data_depth=1024 +CSET sample_on=Rising +CSET trigger_port_width_1=32 +CSET trigger_port_width_10=8 +CSET trigger_port_width_11=8 +CSET trigger_port_width_12=8 +CSET trigger_port_width_13=8 +CSET trigger_port_width_14=8 +CSET trigger_port_width_15=8 +CSET trigger_port_width_16=8 +CSET trigger_port_width_2=8 +CSET trigger_port_width_3=8 +CSET trigger_port_width_4=8 +CSET trigger_port_width_5=8 +CSET trigger_port_width_6=8 +CSET trigger_port_width_7=8 +CSET trigger_port_width_8=8 +CSET trigger_port_width_9=8 +CSET use_rpms=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T02:47:40Z +# END Extra information +GENERATE +# CRC: aad58d16 diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise new file mode 100644 index 000000000..9a9fb9459 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise @@ -0,0 +1,73 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="chipscope_ila_32.ngc" xil_pn:type="FILE_NGC"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="chipscope_ila_32.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/> + </file> + </files> + + <properties> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> + <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Module|chipscope_ila_32" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top File" xil_pn:value="chipscope_ila_32.ngc" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/chipscope_ila_32" xil_pn:valueState="non-default"/> + <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_ila_32" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-08T11:59:31" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="99488C9B3579739424DA923B35D96093" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32_flist.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_flist.txt new file mode 100644 index 000000000..0a88237f8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_flist.txt @@ -0,0 +1,18 @@ +# Output products list for <chipscope_ila_32> +_xmsgs/pn_parser.xmsgs +chipscope_ila_32.asy +chipscope_ila_32.cdc +chipscope_ila_32.constraints/chipscope_ila_32.ucf +chipscope_ila_32.constraints/chipscope_ila_32.xdc +chipscope_ila_32.gise +chipscope_ila_32.ncf +chipscope_ila_32.ngc +chipscope_ila_32.ucf +chipscope_ila_32.v +chipscope_ila_32.veo +chipscope_ila_32.xco +chipscope_ila_32.xdc +chipscope_ila_32.xise +chipscope_ila_32_flist.txt +chipscope_ila_32_readme.txt +chipscope_ila_32_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32_readme.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_readme.txt new file mode 100644 index 000000000..231b5d1ad --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_readme.txt @@ -0,0 +1,48 @@ +The following files were generated for 'chipscope_ila_32' in directory +/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/ + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * chipscope_ila_32.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * chipscope_ila_32.cdc + * chipscope_ila_32.constraints/chipscope_ila_32.ucf + * chipscope_ila_32.constraints/chipscope_ila_32.xdc + * chipscope_ila_32.ncf + * chipscope_ila_32.ngc + * chipscope_ila_32.ucf + * chipscope_ila_32.v + * chipscope_ila_32.veo + * chipscope_ila_32.xdc + * chipscope_ila_32_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * chipscope_ila_32.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * _xmsgs/pn_parser.xmsgs + * chipscope_ila_32.gise + * chipscope_ila_32.xise + +Deliver Readme: + Readme file for the IP. + + * chipscope_ila_32_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * chipscope_ila_32_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32_xmdf.tcl b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_xmdf.tcl new file mode 100755 index 000000000..f3617c66c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_xmdf.tcl @@ -0,0 +1,87 @@ +# The package naming convention is <core_name>_xmdf +package provide chipscope_ila_32_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is <core_name>_xmdf +namespace eval ::chipscope_ila_32_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::chipscope_ila_32_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: <module_name> +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_ila_32 +} +# ::chipscope_ila_32_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::chipscope_ila_32_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.cdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.constraints/chipscope_ila_32.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.constraints/chipscope_ila_32.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_ila_32 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + diff --git a/fpga/usrp3/top/b200/coregen/coregen.cgp b/fpga/usrp3/top/b200/coregen/coregen.cgp new file mode 100644 index 000000000..de5a5aaeb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/coregen.cgp @@ -0,0 +1,10 @@ +SET busformat = BusFormatAngleBracketNotRipped +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET package = fgg484 +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.asy b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.asy new file mode 100644 index 000000000..fd6eef6f7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_4k_2clk +RECTANGLE Normal 32 32 800 4064 +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Normal 0 208 32 208 +PIN 0 208 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Wide 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName din[71:0] +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 464 32 464 +PIN 0 464 LEFT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 0 624 32 624 +PIN 0 624 LEFT 36 +PINATTR PinName wr_data_count[9:0] +PINATTR Polarity OUT +LINE Normal 832 240 800 240 +PIN 832 240 RIGHT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Wide 832 272 800 272 +PIN 832 272 RIGHT 36 +PINATTR PinName dout[71:0] +PINATTR Polarity OUT +LINE Normal 832 304 800 304 +PIN 832 304 RIGHT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 832 496 800 496 +PIN 832 496 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 832 656 800 656 +PIN 832 656 RIGHT 36 +PINATTR PinName rd_data_count[9:0] +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise new file mode 100644 index 000000000..c631a4815 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise @@ -0,0 +1,31 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_4k_2clk.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_4k_2clk.asy" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_4k_2clk.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ncf b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ncf new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ncf diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ngc b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ngc new file mode 100644 index 000000000..b379066c6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.v b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.v new file mode 100644 index 000000000..5724dd553 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.v @@ -0,0 +1,491 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2013 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file fifo_4k_2clk.v when simulating +// the core, fifo_4k_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module fifo_4k_2clk( + rst, + wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + empty, + rd_data_count, + wr_data_count +); + +input rst; +input wr_clk; +input rd_clk; +input [71 : 0] din; +input wr_en; +input rd_en; +output [71 : 0] dout; +output full; +output empty; +output [9 : 0] rd_data_count; +output [9 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V9_3 #( + .C_ADD_NGC_CONSTRAINT(0), + .C_APPLICATION_TYPE_AXIS(0), + .C_APPLICATION_TYPE_RACH(0), + .C_APPLICATION_TYPE_RDCH(0), + .C_APPLICATION_TYPE_WACH(0), + .C_APPLICATION_TYPE_WDCH(0), + .C_APPLICATION_TYPE_WRCH(0), + .C_AXI_ADDR_WIDTH(32), + .C_AXI_ARUSER_WIDTH(1), + .C_AXI_AWUSER_WIDTH(1), + .C_AXI_BUSER_WIDTH(1), + .C_AXI_DATA_WIDTH(64), + .C_AXI_ID_WIDTH(4), + .C_AXI_RUSER_WIDTH(1), + .C_AXI_TYPE(0), + .C_AXI_WUSER_WIDTH(1), + .C_AXIS_TDATA_WIDTH(64), + .C_AXIS_TDEST_WIDTH(4), + .C_AXIS_TID_WIDTH(8), + .C_AXIS_TKEEP_WIDTH(4), + .C_AXIS_TSTRB_WIDTH(4), + .C_AXIS_TUSER_WIDTH(4), + .C_AXIS_TYPE(0), + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(9), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(72), + .C_DIN_WIDTH_AXIS(1), + .C_DIN_WIDTH_RACH(32), + .C_DIN_WIDTH_RDCH(64), + .C_DIN_WIDTH_WACH(32), + .C_DIN_WIDTH_WDCH(64), + .C_DIN_WIDTH_WRCH(2), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(72), + .C_ENABLE_RLOCS(0), + .C_ENABLE_RST_SYNC(1), + .C_ERROR_INJECTION_TYPE(0), + .C_ERROR_INJECTION_TYPE_AXIS(0), + .C_ERROR_INJECTION_TYPE_RACH(0), + .C_ERROR_INJECTION_TYPE_RDCH(0), + .C_ERROR_INJECTION_TYPE_WACH(0), + .C_ERROR_INJECTION_TYPE_WDCH(0), + .C_ERROR_INJECTION_TYPE_WRCH(0), + .C_FAMILY("spartan6"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_AXI_ARUSER(0), + .C_HAS_AXI_AWUSER(0), + .C_HAS_AXI_BUSER(0), + .C_HAS_AXI_RD_CHANNEL(0), + .C_HAS_AXI_RUSER(0), + .C_HAS_AXI_WR_CHANNEL(0), + .C_HAS_AXI_WUSER(0), + .C_HAS_AXIS_TDATA(0), + .C_HAS_AXIS_TDEST(0), + .C_HAS_AXIS_TID(0), + .C_HAS_AXIS_TKEEP(0), + .C_HAS_AXIS_TLAST(0), + .C_HAS_AXIS_TREADY(1), + .C_HAS_AXIS_TSTRB(0), + .C_HAS_AXIS_TUSER(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_DATA_COUNTS_AXIS(0), + .C_HAS_DATA_COUNTS_RACH(0), + .C_HAS_DATA_COUNTS_RDCH(0), + .C_HAS_DATA_COUNTS_WACH(0), + .C_HAS_DATA_COUNTS_WDCH(0), + .C_HAS_DATA_COUNTS_WRCH(0), + .C_HAS_INT_CLK(0), + .C_HAS_MASTER_CE(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_PROG_FLAGS_AXIS(0), + .C_HAS_PROG_FLAGS_RACH(0), + .C_HAS_PROG_FLAGS_RDCH(0), + .C_HAS_PROG_FLAGS_WACH(0), + .C_HAS_PROG_FLAGS_WDCH(0), + .C_HAS_PROG_FLAGS_WRCH(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SLAVE_CE(0), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_IMPLEMENTATION_TYPE_AXIS(1), + .C_IMPLEMENTATION_TYPE_RACH(1), + .C_IMPLEMENTATION_TYPE_RDCH(1), + .C_IMPLEMENTATION_TYPE_WACH(1), + .C_IMPLEMENTATION_TYPE_WDCH(1), + .C_IMPLEMENTATION_TYPE_WRCH(1), + .C_INIT_WR_PNTR_VAL(0), + .C_INTERFACE_TYPE(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x72"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_EMPTY_TYPE_AXIS(0), + .C_PROG_EMPTY_TYPE_RACH(0), + .C_PROG_EMPTY_TYPE_RDCH(0), + .C_PROG_EMPTY_TYPE_WACH(0), + .C_PROG_EMPTY_TYPE_WDCH(0), + .C_PROG_EMPTY_TYPE_WRCH(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(511), + .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023), + .C_PROG_FULL_THRESH_NEGATE_VAL(510), + .C_PROG_FULL_TYPE(0), + .C_PROG_FULL_TYPE_AXIS(0), + .C_PROG_FULL_TYPE_RACH(0), + .C_PROG_FULL_TYPE_RDCH(0), + .C_PROG_FULL_TYPE_WACH(0), + .C_PROG_FULL_TYPE_WDCH(0), + .C_PROG_FULL_TYPE_WRCH(0), + .C_RACH_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(10), + .C_RD_DEPTH(512), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(9), + .C_RDCH_TYPE(0), + .C_REG_SLICE_MODE_AXIS(0), + .C_REG_SLICE_MODE_RACH(0), + .C_REG_SLICE_MODE_RDCH(0), + .C_REG_SLICE_MODE_WACH(0), + .C_REG_SLICE_MODE_WDCH(0), + .C_REG_SLICE_MODE_WRCH(0), + .C_SYNCHRONIZER_STAGE(2), + .C_UNDERFLOW_LOW(0), + .C_USE_COMMON_OVERFLOW(0), + .C_USE_COMMON_UNDERFLOW(0), + .C_USE_DEFAULT_SETTINGS(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_ECC_AXIS(0), + .C_USE_ECC_RACH(0), + .C_USE_ECC_RDCH(0), + .C_USE_ECC_WACH(0), + .C_USE_ECC_WDCH(0), + .C_USE_ECC_WRCH(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(1), + .C_VALID_LOW(0), + .C_WACH_TYPE(0), + .C_WDCH_TYPE(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(10), + .C_WR_DEPTH(512), + .C_WR_DEPTH_AXIS(1024), + .C_WR_DEPTH_RACH(16), + .C_WR_DEPTH_RDCH(1024), + .C_WR_DEPTH_WACH(16), + .C_WR_DEPTH_WDCH(1024), + .C_WR_DEPTH_WRCH(16), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(9), + .C_WR_PNTR_WIDTH_AXIS(10), + .C_WR_PNTR_WIDTH_RACH(4), + .C_WR_PNTR_WIDTH_RDCH(10), + .C_WR_PNTR_WIDTH_WACH(4), + .C_WR_PNTR_WIDTH_WDCH(10), + .C_WR_PNTR_WIDTH_WRCH(4), + .C_WR_RESPONSE_LATENCY(1), + .C_WRCH_TYPE(0) + ) + inst ( + .RST(rst), + .WR_CLK(wr_clk), + .RD_CLK(rd_clk), + .DIN(din), + .WR_EN(wr_en), + .RD_EN(rd_en), + .DOUT(dout), + .FULL(full), + .EMPTY(empty), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .BACKUP(), + .BACKUP_MARKER(), + .CLK(), + .SRST(), + .WR_RST(), + .RD_RST(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .INT_CLK(), + .INJECTDBITERR(), + .INJECTSBITERR(), + .ALMOST_FULL(), + .WR_ACK(), + .OVERFLOW(), + .ALMOST_EMPTY(), + .VALID(), + .UNDERFLOW(), + .DATA_COUNT(), + .PROG_FULL(), + .PROG_EMPTY(), + .SBITERR(), + .DBITERR(), + .M_ACLK(), + .S_ACLK(), + .S_ARESETN(), + .M_ACLK_EN(), + .S_ACLK_EN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWLOCK(), + .S_AXI_AWCACHE(), + .S_AXI_AWPROT(), + .S_AXI_AWQOS(), + .S_AXI_AWREGION(), + .S_AXI_AWUSER(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WID(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WUSER(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BUSER(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .M_AXI_AWID(), + .M_AXI_AWADDR(), + .M_AXI_AWLEN(), + .M_AXI_AWSIZE(), + .M_AXI_AWBURST(), + .M_AXI_AWLOCK(), + .M_AXI_AWCACHE(), + .M_AXI_AWPROT(), + .M_AXI_AWQOS(), + .M_AXI_AWREGION(), + .M_AXI_AWUSER(), + .M_AXI_AWVALID(), + .M_AXI_AWREADY(), + .M_AXI_WID(), + .M_AXI_WDATA(), + .M_AXI_WSTRB(), + .M_AXI_WLAST(), + .M_AXI_WUSER(), + .M_AXI_WVALID(), + .M_AXI_WREADY(), + .M_AXI_BID(), + .M_AXI_BRESP(), + .M_AXI_BUSER(), + .M_AXI_BVALID(), + .M_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARLOCK(), + .S_AXI_ARCACHE(), + .S_AXI_ARPROT(), + .S_AXI_ARQOS(), + .S_AXI_ARREGION(), + .S_AXI_ARUSER(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RUSER(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .M_AXI_ARID(), + .M_AXI_ARADDR(), + .M_AXI_ARLEN(), + .M_AXI_ARSIZE(), + .M_AXI_ARBURST(), + .M_AXI_ARLOCK(), + .M_AXI_ARCACHE(), + .M_AXI_ARPROT(), + .M_AXI_ARQOS(), + .M_AXI_ARREGION(), + .M_AXI_ARUSER(), + .M_AXI_ARVALID(), + .M_AXI_ARREADY(), + .M_AXI_RID(), + .M_AXI_RDATA(), + .M_AXI_RRESP(), + .M_AXI_RLAST(), + .M_AXI_RUSER(), + .M_AXI_RVALID(), + .M_AXI_RREADY(), + .S_AXIS_TVALID(), + .S_AXIS_TREADY(), + .S_AXIS_TDATA(), + .S_AXIS_TSTRB(), + .S_AXIS_TKEEP(), + .S_AXIS_TLAST(), + .S_AXIS_TID(), + .S_AXIS_TDEST(), + .S_AXIS_TUSER(), + .M_AXIS_TVALID(), + .M_AXIS_TREADY(), + .M_AXIS_TDATA(), + .M_AXIS_TSTRB(), + .M_AXIS_TKEEP(), + .M_AXIS_TLAST(), + .M_AXIS_TID(), + .M_AXIS_TDEST(), + .M_AXIS_TUSER(), + .AXI_AW_INJECTSBITERR(), + .AXI_AW_INJECTDBITERR(), + .AXI_AW_PROG_FULL_THRESH(), + .AXI_AW_PROG_EMPTY_THRESH(), + .AXI_AW_DATA_COUNT(), + .AXI_AW_WR_DATA_COUNT(), + .AXI_AW_RD_DATA_COUNT(), + .AXI_AW_SBITERR(), + .AXI_AW_DBITERR(), + .AXI_AW_OVERFLOW(), + .AXI_AW_UNDERFLOW(), + .AXI_AW_PROG_FULL(), + .AXI_AW_PROG_EMPTY(), + .AXI_W_INJECTSBITERR(), + .AXI_W_INJECTDBITERR(), + .AXI_W_PROG_FULL_THRESH(), + .AXI_W_PROG_EMPTY_THRESH(), + .AXI_W_DATA_COUNT(), + .AXI_W_WR_DATA_COUNT(), + .AXI_W_RD_DATA_COUNT(), + .AXI_W_SBITERR(), + .AXI_W_DBITERR(), + .AXI_W_OVERFLOW(), + .AXI_W_UNDERFLOW(), + .AXI_B_INJECTSBITERR(), + .AXI_W_PROG_FULL(), + .AXI_W_PROG_EMPTY(), + .AXI_B_INJECTDBITERR(), + .AXI_B_PROG_FULL_THRESH(), + .AXI_B_PROG_EMPTY_THRESH(), + .AXI_B_DATA_COUNT(), + .AXI_B_WR_DATA_COUNT(), + .AXI_B_RD_DATA_COUNT(), + .AXI_B_SBITERR(), + .AXI_B_DBITERR(), + .AXI_B_OVERFLOW(), + .AXI_B_UNDERFLOW(), + .AXI_AR_INJECTSBITERR(), + .AXI_B_PROG_FULL(), + .AXI_B_PROG_EMPTY(), + .AXI_AR_INJECTDBITERR(), + .AXI_AR_PROG_FULL_THRESH(), + .AXI_AR_PROG_EMPTY_THRESH(), + .AXI_AR_DATA_COUNT(), + .AXI_AR_WR_DATA_COUNT(), + .AXI_AR_RD_DATA_COUNT(), + .AXI_AR_SBITERR(), + .AXI_AR_DBITERR(), + .AXI_AR_OVERFLOW(), + .AXI_AR_UNDERFLOW(), + .AXI_AR_PROG_FULL(), + .AXI_AR_PROG_EMPTY(), + .AXI_R_INJECTSBITERR(), + .AXI_R_INJECTDBITERR(), + .AXI_R_PROG_FULL_THRESH(), + .AXI_R_PROG_EMPTY_THRESH(), + .AXI_R_DATA_COUNT(), + .AXI_R_WR_DATA_COUNT(), + .AXI_R_RD_DATA_COUNT(), + .AXI_R_SBITERR(), + .AXI_R_DBITERR(), + .AXI_R_OVERFLOW(), + .AXI_R_UNDERFLOW(), + .AXIS_INJECTSBITERR(), + .AXI_R_PROG_FULL(), + .AXI_R_PROG_EMPTY(), + .AXIS_INJECTDBITERR(), + .AXIS_PROG_FULL_THRESH(), + .AXIS_PROG_EMPTY_THRESH(), + .AXIS_DATA_COUNT(), + .AXIS_WR_DATA_COUNT(), + .AXIS_RD_DATA_COUNT(), + .AXIS_SBITERR(), + .AXIS_DBITERR(), + .AXIS_OVERFLOW(), + .AXIS_UNDERFLOW(), + .AXIS_PROG_FULL(), + .AXIS_PROG_EMPTY() + ); + +// synthesis translate_on + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.veo b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.veo new file mode 100644 index 000000000..12c025d5d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.veo @@ -0,0 +1,79 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2013 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ + +/******************************************************************************* +* Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 * +* * +* Rev 1. The FIFO Generator is a parameterizable first-in/first-out * +* memory queue generator. Use it to generate resource and performance * +* optimized FIFOs with common or independent read/write clock domains, * +* and optional fixed or programmable full and empty flags and * +* handshaking signals. Choose from a selection of memory resource * +* types for implementation. Optional Hamming code based error * +* detection and correction as well as error injection capability for * +* system test help to insure data integrity. FIFO width and depth are * +* parameterizable, and for native interface FIFOs, asymmetric read and * +* write port widths are also supported. * +*******************************************************************************/ + +// Interfaces: +// AXI4Stream_MASTER_M_AXIS +// AXI4Stream_SLAVE_S_AXIS +// AXI4_MASTER_M_AXI +// AXI4_SLAVE_S_AXI +// AXI4Lite_MASTER_M_AXI +// AXI4Lite_SLAVE_S_AXI +// master_aclk +// slave_aclk +// slave_aresetn + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_4k_2clk your_instance_name ( + .rst(rst), // input rst + .wr_clk(wr_clk), // input wr_clk + .rd_clk(rd_clk), // input rd_clk + .din(din), // input [71 : 0] din + .wr_en(wr_en), // input wr_en + .rd_en(rd_en), // input rd_en + .dout(dout), // output [71 : 0] dout + .full(full), // output full + .empty(empty), // output empty + .rd_data_count(rd_data_count), // output [9 : 0] rd_data_count + .wr_data_count(wr_data_count) // output [9 : 0] wr_data_count +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_4k_2clk.v when simulating +// the core, fifo_4k_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xco b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xco new file mode 100644 index 000000000..f617ee440 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xco @@ -0,0 +1,213 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Fri Jan 25 19:58:19 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fifo_generator:9.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 +# END Select +# BEGIN Parameters +CSET add_ngc_constraint_axi=false +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET aruser_width=1 +CSET awuser_width=1 +CSET axi_address_width=32 +CSET axi_data_width=64 +CSET axi_type=AXI4_Stream +CSET axis_type=FIFO +CSET buser_width=1 +CSET clock_enable_type=Slave_Interface_Clock_Enable +CSET clock_type_axi=Common_Clock +CSET component_name=fifo_4k_2clk +CSET data_count=false +CSET data_count_width=9 +CSET disable_timing_violations=false +CSET disable_timing_violations_axi=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_assert_value_axis=1022 +CSET empty_threshold_assert_value_rach=1022 +CSET empty_threshold_assert_value_rdch=1022 +CSET empty_threshold_assert_value_wach=1022 +CSET empty_threshold_assert_value_wdch=1022 +CSET empty_threshold_assert_value_wrch=1022 +CSET empty_threshold_negate_value=5 +CSET enable_aruser=false +CSET enable_awuser=false +CSET enable_buser=false +CSET enable_common_overflow=false +CSET enable_common_underflow=false +CSET enable_data_counts_axis=false +CSET enable_data_counts_rach=false +CSET enable_data_counts_rdch=false +CSET enable_data_counts_wach=false +CSET enable_data_counts_wdch=false +CSET enable_data_counts_wrch=false +CSET enable_ecc=false +CSET enable_ecc_axis=false +CSET enable_ecc_rach=false +CSET enable_ecc_rdch=false +CSET enable_ecc_wach=false +CSET enable_ecc_wdch=false +CSET enable_ecc_wrch=false +CSET enable_read_channel=false +CSET enable_read_pointer_increment_by2=false +CSET enable_reset_synchronization=true +CSET enable_ruser=false +CSET enable_tdata=false +CSET enable_tdest=false +CSET enable_tid=false +CSET enable_tkeep=false +CSET enable_tlast=false +CSET enable_tready=true +CSET enable_tstrobe=false +CSET enable_tuser=false +CSET enable_write_channel=false +CSET enable_wuser=false +CSET fifo_application_type_axis=Data_FIFO +CSET fifo_application_type_rach=Data_FIFO +CSET fifo_application_type_rdch=Data_FIFO +CSET fifo_application_type_wach=Data_FIFO +CSET fifo_application_type_wdch=Data_FIFO +CSET fifo_application_type_wrch=Data_FIFO +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET fifo_implementation_axis=Common_Clock_Block_RAM +CSET fifo_implementation_rach=Common_Clock_Block_RAM +CSET fifo_implementation_rdch=Common_Clock_Block_RAM +CSET fifo_implementation_wach=Common_Clock_Block_RAM +CSET fifo_implementation_wdch=Common_Clock_Block_RAM +CSET fifo_implementation_wrch=Common_Clock_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=511 +CSET full_threshold_assert_value_axis=1023 +CSET full_threshold_assert_value_rach=1023 +CSET full_threshold_assert_value_rdch=1023 +CSET full_threshold_assert_value_wach=1023 +CSET full_threshold_assert_value_wdch=1023 +CSET full_threshold_assert_value_wrch=1023 +CSET full_threshold_negate_value=510 +CSET id_width=4 +CSET inject_dbit_error=false +CSET inject_dbit_error_axis=false +CSET inject_dbit_error_rach=false +CSET inject_dbit_error_rdch=false +CSET inject_dbit_error_wach=false +CSET inject_dbit_error_wdch=false +CSET inject_dbit_error_wrch=false +CSET inject_sbit_error=false +CSET inject_sbit_error_axis=false +CSET inject_sbit_error_rach=false +CSET inject_sbit_error_rdch=false +CSET inject_sbit_error_wach=false +CSET inject_sbit_error_wdch=false +CSET inject_sbit_error_wrch=false +CSET input_data_width=72 +CSET input_depth=512 +CSET input_depth_axis=1024 +CSET input_depth_rach=16 +CSET input_depth_rdch=1024 +CSET input_depth_wach=16 +CSET input_depth_wdch=1024 +CSET input_depth_wrch=16 +CSET interface_type=Native +CSET output_data_width=72 +CSET output_depth=512 +CSET overflow_flag=false +CSET overflow_flag_axi=false +CSET overflow_sense=Active_High +CSET overflow_sense_axi=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET programmable_full_type_axis=No_Programmable_Full_Threshold +CSET programmable_full_type_rach=No_Programmable_Full_Threshold +CSET programmable_full_type_rdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wach=No_Programmable_Full_Threshold +CSET programmable_full_type_wdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wrch=No_Programmable_Full_Threshold +CSET rach_type=FIFO +CSET rdch_type=FIFO +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=10 +CSET register_slice_mode_axis=Fully_Registered +CSET register_slice_mode_rach=Fully_Registered +CSET register_slice_mode_rdch=Fully_Registered +CSET register_slice_mode_wach=Fully_Registered +CSET register_slice_mode_wdch=Fully_Registered +CSET register_slice_mode_wrch=Fully_Registered +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET ruser_width=1 +CSET synchronization_stages=2 +CSET synchronization_stages_axi=2 +CSET tdata_width=64 +CSET tdest_width=4 +CSET tid_width=8 +CSET tkeep_width=4 +CSET tstrb_width=4 +CSET tuser_width=4 +CSET underflow_flag=false +CSET underflow_flag_axi=false +CSET underflow_sense=Active_High +CSET underflow_sense_axi=Active_High +CSET use_clock_enable=false +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET wach_type=FIFO +CSET wdch_type=FIFO +CSET wrch_type=FIFO +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=10 +CSET wuser_width=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-19T12:39:56Z +# END Extra information +GENERATE +# CRC: 372c204f diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise new file mode 100644 index 000000000..2d8132c10 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise @@ -0,0 +1,73 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="fifo_4k_2clk.ngc" xil_pn:type="FILE_NGC"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="fifo_4k_2clk.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/> + </file> + </files> + + <properties> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> + <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_4k_2clk" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_4k_2clk.ngc" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_4k_2clk" xil_pn:valueState="non-default"/> + <property xil_pn:name="Package" xil_pn:value="csg484" xil_pn:valueState="default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_4k_2clk" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-01-25T11:59:33" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A74B340026B44B356C1780B6C6FE45BC" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt new file mode 100644 index 000000000..7853ebde8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt @@ -0,0 +1,236 @@ +CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1 + + Release Date: December 18, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + + All 7 Series devices + Zynq-7000 devices + +................................................................................ + + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - ISE 14.4 software support + + + 3.2 Vivado + + - 2012.4 software support + - IP level constraint for Built-in FIFO reset synchronizer + +................................................................................ + + +4. RESOLVED ISSUES + + + 4.1 ISE + + - N/A + + + 4.2 Vivado + + - N/A + + +................................................................................ + + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Importing an XCO file alters the XCO configurations + + Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) + into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, + page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. + + CR 467240 + AR 31379 + + 2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed + + Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, + correct behavior of the FIFO status flags cannot be guaranteed after the first write. + + Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. + For more information and additional workaround see Answer Record 41099. + + 5.2 Vivado + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen + ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. + + CR 665836 + +The most recent information, including known issues, workarounds, and +resolutions for this version is provided in the IP Release Notes User Guide +located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + +................................................................................ + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer +10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO +07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO +04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support + AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO +01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support +10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support +06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support +03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support +10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support +09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support +07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support +06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support +12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support +09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support +06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support +04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support +09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes +03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes +10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs +08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO +04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support +09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support +07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support +01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 +08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 +04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 +11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 +05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support +04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release +================================================================================ + +................................................................................ + + +8. LEGAL DISCLAIMER + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html new file mode 100644 index 000000000..fefce62a3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html @@ -0,0 +1,247 @@ +<HTML> +<HEAD> +<TITLE>fifo_generator_v9_3_vinfo</TITLE> +<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1"> +</HEAD> +<BODY> +<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1"> +CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1 + + Release Date: December 18, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A> + +For system requirements: + + <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A> + +This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1 +solution. For the latest core updates, see the product page at: + + <A HREF="http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm">www.xilinx.com/products/ipcenter/FIFO_Generator.htm</A> + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + + All 7 Series devices + Zynq-7000 devices + +................................................................................ + + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - ISE 14.4 software support + + + 3.2 Vivado + + - 2012.4 software support + - IP level constraint for Built-in FIFO reset synchronizer + +................................................................................ + + +4. RESOLVED ISSUES + + + 4.1 ISE + + - N/A + + + 4.2 Vivado + + - N/A + + +................................................................................ + + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Importing an XCO file alters the XCO configurations + + Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) + into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, + page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. + + CR 467240 + AR 31379 + + 2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed + + Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, + correct behavior of the FIFO status flags cannot be guaranteed after the first write. + + Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. + For more information and additional workaround see Answer Record 41099. + + 5.2 Vivado + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen + ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. + + CR 665836 + +The most recent information, including known issues, workarounds, and +resolutions for this version is provided in the IP Release Notes User Guide +located at + + <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A> + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + +To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A> +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + +................................................................................ + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer +10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO +07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO +04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support + AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO +01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support +10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support +06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support +03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support +10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support +09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support +07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support +06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support +12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support +09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support +06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support +04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support +09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes +03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes +10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs +08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO +04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support +09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support +07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support +01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 +08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 +04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 +11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 +05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support +04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release +================================================================================ + +................................................................................ + + +8. LEGAL DISCLAIMER + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. +</FONT> +</PRE> +</BODY> +</HTML> diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/pg057-fifo-generator.pdf b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/pg057-fifo-generator.pdf Binary files differnew file mode 100644 index 000000000..5ec45fbcb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/pg057-fifo-generator.pdf diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf new file mode 100755 index 000000000..62e5058ab --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf @@ -0,0 +1,56 @@ +################################################################################ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. + NET "RD_CLK" TNM_NET = "RD_CLK"; + NET "WR_CLK" TNM_NET = "WR_CLK"; + TIMESPEC "TS_RD_CLK" = PERIOD "RD_CLK" 50 MHZ; + TIMESPEC "TS_WR_CLK" = PERIOD "WR_CLK" 50 MHZ; +################################################################################ diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd new file mode 100755 index 000000000..2674443c8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd @@ -0,0 +1,145 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core - core top file for implementation +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_exdes.vhd +-- +-- Description: +-- This is the FIFO core wrapper with BUFG instances for clock connections. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library unisim; +use unisim.vcomponents.all; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +entity fifo_4k_2clk_exdes is + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + +end fifo_4k_2clk_exdes; + + + +architecture xilinx of fifo_4k_2clk_exdes is + + signal wr_clk_i : std_logic; + signal rd_clk_i : std_logic; + + + + component fifo_4k_2clk is + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + + end component; + + +begin + + wr_clk_buf: bufg + PORT map( + i => WR_CLK, + o => wr_clk_i + ); + + rd_clk_buf: bufg + PORT map( + i => RD_CLK, + o => rd_clk_i + ); + + + exdes_inst : fifo_4k_2clk + PORT MAP ( + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + WR_DATA_COUNT => wr_data_count, + RD_DATA_COUNT => rd_data_count, + RST => rst, + WR_EN => wr_en, + RD_EN => rd_en, + DIN => din, + DOUT => dout, + FULL => full, + EMPTY => empty); + +end xilinx; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/fifo_generator_v9_3_readme.txt new file mode 100644 index 000000000..7853ebde8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/fifo_generator_v9_3_readme.txt @@ -0,0 +1,236 @@ +CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1 + + Release Date: December 18, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + + All 7 Series devices + Zynq-7000 devices + +................................................................................ + + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - ISE 14.4 software support + + + 3.2 Vivado + + - 2012.4 software support + - IP level constraint for Built-in FIFO reset synchronizer + +................................................................................ + + +4. RESOLVED ISSUES + + + 4.1 ISE + + - N/A + + + 4.2 Vivado + + - N/A + + +................................................................................ + + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Importing an XCO file alters the XCO configurations + + Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) + into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, + page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. + + CR 467240 + AR 31379 + + 2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed + + Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, + correct behavior of the FIFO status flags cannot be guaranteed after the first write. + + Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. + For more information and additional workaround see Answer Record 41099. + + 5.2 Vivado + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen + ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. + + CR 665836 + +The most recent information, including known issues, workarounds, and +resolutions for this version is provided in the IP Release Notes User Guide +located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + +................................................................................ + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer +10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO +07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO +04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support + AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO +01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support +10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support +06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support +03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support +10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support +09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support +07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support +06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support +12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support +09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support +06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support +04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support +09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes +03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes +10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs +08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO +04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support +09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support +07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support +01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 +08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 +04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 +11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 +05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support +04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release +================================================================================ + +................................................................................ + + +8. LEGAL DISCLAIMER + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.bat new file mode 100755 index 000000000..f5fcf0a2b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.bat @@ -0,0 +1,88 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +copy fifo_4k_2clk_exdes.ngc .\results\ + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\fifo_4k_2clk.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\fifo_4k_2clk_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-2 -sd ../../../ fifo_4k_2clk_exdes + +echo 'Running map' +map fifo_4k_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.sh new file mode 100755 index 000000000..9cb53f5c7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.sh @@ -0,0 +1,87 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +cp fifo_4k_2clk_exdes.ngc ./results/ + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../fifo_4k_2clk.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/fifo_4k_2clk_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-2 -sd ../../../ fifo_4k_2clk_exdes + +echo 'Running map' +map fifo_4k_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.bat new file mode 100755 index 000000000..9d99aaa5c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.bat @@ -0,0 +1,87 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with Synplify' +synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\fifo_4k_2clk.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\fifo_4k_2clk_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-2 -sd ../../../ fifo_4k_2clk_exdes + +echo 'Running map' +map fifo_4k_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.sh new file mode 100755 index 000000000..db245edbb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.sh @@ -0,0 +1,86 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with Synplify' +synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../fifo_4k_2clk.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/fifo_4k_2clk_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-2 -sd ../../../ fifo_4k_2clk_exdes + +echo 'Running map' +map fifo_4k_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.bat new file mode 100755 index 000000000..a48fea790 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.bat @@ -0,0 +1,54 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\fifo_4k_2clk.ngc . +planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.sh new file mode 100755 index 000000000..7171a0e5e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.sh @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../fifo_4k_2clk.ngc . +planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.tcl new file mode 100755 index 000000000..6af923b85 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.tcl @@ -0,0 +1,67 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc6slx75csg484-2 +set projName fifo_4k_2clk +set design fifo_4k_2clk +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module fifo_4k_2clk_exdes +add_files -norecurse {../../example_design/fifo_4k_2clk_exdes.vhd} +add_files -norecurse {./fifo_4k_2clk.ngc} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/fifo_4k_2clk_exdes.xdc} +set_property top fifo_4k_2clk_exdes [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module fifo_4k_2clk_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module fifo_4k_2clk_exdes routed.v +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.prj b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.prj new file mode 100755 index 000000000..573a1716f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.prj @@ -0,0 +1 @@ +work ../example_design/fifo_4k_2clk_exdes.vhd diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.scr b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.scr new file mode 100755 index 000000000..bff287f78 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.scr @@ -0,0 +1,13 @@ +run +-ifmt VHDL +-ent fifo_4k_2clk_exdes +-p xc6slx75-csg484-2 +-ifn xst.prj +-write_timing_constraints No +-iobuf YES +-max_fanout 100 +-ofn fifo_4k_2clk_exdes +-ofmt NGC +-bus_delimiter () +-hierarchy_separator / +-case Maintain diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd new file mode 100755 index 000000000..d14bb7a51 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd @@ -0,0 +1,123 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_dgen.vhd +-- +-- Description: +-- Used for write interface stimulus generation +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +ENTITY fifo_4k_2clk_dgen IS + GENERIC ( + C_DIN_WIDTH : INTEGER := 32; + C_DOUT_WIDTH : INTEGER := 32; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT ( + RESET : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + PRC_WR_EN : IN STD_LOGIC; + FULL : IN STD_LOGIC; + WR_EN : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE fg_dg_arch OF fifo_4k_2clk_dgen IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); + + SIGNAL pr_w_en : STD_LOGIC := '0'; + SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); + SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + BEGIN + + WR_EN <= PRC_WR_EN ; + WR_DATA <= wr_data_i AFTER 100 ns; + + ---------------------------------------------- + -- Generation of DATA + ---------------------------------------------- + gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + rd_gen_inst1:fifo_4k_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+N + ) + PORT MAP( + CLK => WR_CLK, + RESET => RESET, + RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), + ENABLE => pr_w_en + ); + END GENERATE; + + pr_w_en <= PRC_WR_EN AND NOT FULL; + wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0); + + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd new file mode 100755 index 000000000..0a7c2aa87 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd @@ -0,0 +1,150 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_dverif.vhd +-- +-- Description: +-- Used for FIFO read interface stimulus generation and data checking +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +ENTITY fifo_4k_2clk_dverif IS + GENERIC( + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_USE_EMBEDDED_REG : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + PRC_RD_EN : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + RD_EN : OUT STD_LOGIC; + DOUT_CHK : OUT STD_LOGIC + ); +END ENTITY; + + +ARCHITECTURE fg_dv_arch OF fifo_4k_2clk_dverif IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8); + + SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_chk : STD_LOGIC := '1'; + SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0); + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL pr_r_en : STD_LOGIC := '0'; + SIGNAL rd_en_d1 : STD_LOGIC := '1'; +BEGIN + + + DOUT_CHK <= data_chk; + RD_EN <= rd_en_i; + rd_en_i <= PRC_RD_EN; + rd_en_d1 <= '1'; + + + data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE + ------------------------------------------------------- + -- Expected data generation and checking for data_fifo + ------------------------------------------------------- + + pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1; + expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0); + + gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + rd_gen_inst2:fifo_4k_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+N + ) + PORT MAP( + CLK => RD_CLK, + RESET => RESET, + RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), + ENABLE => pr_r_en + ); + END GENERATE; + + PROCESS (RD_CLK,RESET) + BEGIN + IF(RESET = '1') THEN + data_chk <= '0'; + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + IF(EMPTY = '0') THEN + IF(DATA_OUT = expected_dout) THEN + data_chk <= '0'; + ELSE + data_chk <= '1'; + END IF; + END IF; + END IF; + END PROCESS; + END GENERATE data_fifo_chk; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd new file mode 100755 index 000000000..fa32e4781 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd @@ -0,0 +1,541 @@ + +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_pctrl.vhd +-- +-- Description: +-- Used for protocol control on write and read interface stimulus and status generation +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +ENTITY fifo_4k_2clk_pctrl IS + GENERIC( + AXI_CHANNEL : STRING :="NONE"; + C_APPLICATION_TYPE : INTEGER := 0; + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_WR_PNTR_WIDTH : INTEGER := 0; + C_RD_PNTR_WIDTH : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 2; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET_WR : IN STD_LOGIC; + RESET_RD : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + FULL : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + ALMOST_FULL : IN STD_LOGIC; + ALMOST_EMPTY : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + DOUT_CHK : IN STD_LOGIC; + PRC_WR_EN : OUT STD_LOGIC; + PRC_RD_EN : OUT STD_LOGIC; + RESET_EN : OUT STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE fg_pc_arch OF fifo_4k_2clk_pctrl IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); + CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH); + + SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); + SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); + SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); + SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); + SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_en_i : STD_LOGIC := '0'; + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL state : STD_LOGIC := '0'; + SIGNAL wr_control : STD_LOGIC := '0'; + SIGNAL rd_control : STD_LOGIC := '0'; + SIGNAL stop_on_err : STD_LOGIC := '0'; + SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8); + SIGNAL sim_done_i : STD_LOGIC := '0'; + SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); + SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); + SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0'); + SIGNAL prc_we_i : STD_LOGIC := '0'; + SIGNAL prc_re_i : STD_LOGIC := '0'; + SIGNAL reset_en_i : STD_LOGIC := '0'; + SIGNAL sim_done_d1 : STD_LOGIC := '0'; + SIGNAL sim_done_wr1 : STD_LOGIC := '0'; + SIGNAL sim_done_wr2 : STD_LOGIC := '0'; + SIGNAL empty_d1 : STD_LOGIC := '0'; + SIGNAL empty_wr_dom1 : STD_LOGIC := '0'; + SIGNAL state_d1 : STD_LOGIC := '0'; + SIGNAL state_rd_dom1 : STD_LOGIC := '0'; + SIGNAL rd_en_d1 : STD_LOGIC := '0'; + SIGNAL rd_en_wr1 : STD_LOGIC := '0'; + SIGNAL wr_en_d1 : STD_LOGIC := '0'; + SIGNAL wr_en_rd1 : STD_LOGIC := '0'; + SIGNAL full_chk_d1 : STD_LOGIC := '0'; + SIGNAL full_chk_rd1 : STD_LOGIC := '0'; + SIGNAL empty_wr_dom2 : STD_LOGIC := '0'; + + SIGNAL state_rd_dom2 : STD_LOGIC := '0'; + SIGNAL state_rd_dom3 : STD_LOGIC := '0'; + SIGNAL rd_en_wr2 : STD_LOGIC := '0'; + SIGNAL wr_en_rd2 : STD_LOGIC := '0'; + SIGNAL full_chk_rd2 : STD_LOGIC := '0'; + SIGNAL reset_en_d1 : STD_LOGIC := '0'; + SIGNAL reset_en_rd1 : STD_LOGIC := '0'; + SIGNAL reset_en_rd2 : STD_LOGIC := '0'; + + SIGNAL data_chk_wr_d1 : STD_LOGIC := '0'; + SIGNAL data_chk_rd1 : STD_LOGIC := '0'; + SIGNAL data_chk_rd2 : STD_LOGIC := '0'; + SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); + SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); +BEGIN + status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0'; + STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high); + + prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0'; + prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0'; + + SIM_DONE <= sim_done_i; + rdw_gt_wrw <= (OTHERS => '1'); + wrw_gt_rdw <= (OTHERS => '1'); + + PROCESS(RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(prc_re_i = '1') THEN + rd_activ_cont <= rd_activ_cont + "1"; + END IF; + END IF; + END PROCESS; + + + PROCESS(sim_done_i) + BEGIN + assert sim_done_i = '0' + report "Simulation Complete for:" & AXI_CHANNEL + severity note; + END PROCESS; + +----------------------------------------------------- +-- SIM_DONE SIGNAL GENERATION +----------------------------------------------------- +PROCESS (RD_CLK,RESET_RD) +BEGIN + IF(RESET_RD = '1') THEN + --sim_done_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN + sim_done_i <= '1'; + END IF; + END IF; +END PROCESS; + + -- TB Timeout/Stop + fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE + PROCESS (RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN + sim_stop_cntr <= sim_stop_cntr - "1"; + END IF; + END IF; + END PROCESS; + END GENERATE fifo_tb_stop_run; + + + -- Stop when error found + PROCESS (RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(sim_done_i = '0') THEN + status_d1_i <= status_i OR status_d1_i; + END IF; + IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN + stop_on_err <= '1'; + END IF; + END IF; + END PROCESS; + ----------------------------------------------------- + + ----------------------------------------------------- + -- CHECKS FOR FIFO + ----------------------------------------------------- + + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + post_rst_dly_rd <= (OTHERS => '1'); + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4); + END IF; + END PROCESS; + + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + post_rst_dly_wr <= (OTHERS => '1'); + ELSIF (WR_CLK'event AND WR_CLK='1') THEN + post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4); + END IF; + END PROCESS; + + + -- FULL de-assert Counter + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + full_ds_timeout <= (OTHERS => '0'); + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN + full_ds_timeout <= full_ds_timeout + '1'; + END IF; + ELSE + full_ds_timeout <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS; + + + -- EMPTY deassert counter + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_ds_timeout <= (OTHERS => '0'); + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state = '0') THEN + IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN + empty_ds_timeout <= empty_ds_timeout + '1'; + END IF; + ELSE + empty_ds_timeout <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS; + + -- Full check signal generation + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + full_chk_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN + full_chk_i <= '0'; + ELSE + full_chk_i <= AND_REDUCE(full_as_timeout) OR + AND_REDUCE(full_ds_timeout); + END IF; + END IF; + END PROCESS; + + -- Empty checks + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_chk_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN + empty_chk_i <= '0'; + ELSE + empty_chk_i <= AND_REDUCE(empty_as_timeout) OR + AND_REDUCE(empty_ds_timeout); + END IF; + END IF; + END PROCESS; + + fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE + PRC_WR_EN <= prc_we_i AFTER 100 ns; + PRC_RD_EN <= prc_re_i AFTER 50 ns; + data_chk_i <= dout_chk; + END GENERATE fifo_d_chk; + ----------------------------------------------------- + + + ----------------------------------------------------- + -- SYNCHRONIZERS B/W WRITE AND READ DOMAINS + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + empty_wr_dom1 <= '1'; + empty_wr_dom2 <= '1'; + state_d1 <= '0'; + wr_en_d1 <= '0'; + rd_en_wr1 <= '0'; + rd_en_wr2 <= '0'; + full_chk_d1 <= '0'; + reset_en_d1 <= '0'; + sim_done_wr1 <= '0'; + sim_done_wr2 <= '0'; + ELSIF (WR_CLK'event AND WR_CLK='1') THEN + sim_done_wr1 <= sim_done_d1; + sim_done_wr2 <= sim_done_wr1; + reset_en_d1 <= reset_en_i; + state_d1 <= state; + empty_wr_dom1 <= empty_d1; + empty_wr_dom2 <= empty_wr_dom1; + wr_en_d1 <= wr_en_i; + rd_en_wr1 <= rd_en_d1; + rd_en_wr2 <= rd_en_wr1; + full_chk_d1 <= full_chk_i; + END IF; + END PROCESS; + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_d1 <= '1'; + state_rd_dom1 <= '0'; + state_rd_dom2 <= '0'; + state_rd_dom3 <= '0'; + wr_en_rd1 <= '0'; + wr_en_rd2 <= '0'; + rd_en_d1 <= '0'; + full_chk_rd1 <= '0'; + full_chk_rd2 <= '0'; + reset_en_rd1 <= '0'; + reset_en_rd2 <= '0'; + sim_done_d1 <= '0'; + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + sim_done_d1 <= sim_done_i; + reset_en_rd1 <= reset_en_d1; + reset_en_rd2 <= reset_en_rd1; + empty_d1 <= EMPTY; + rd_en_d1 <= rd_en_i; + state_rd_dom1 <= state_d1; + state_rd_dom2 <= state_rd_dom1; + state_rd_dom3 <= state_rd_dom2; + wr_en_rd1 <= wr_en_d1; + wr_en_rd2 <= wr_en_rd1; + full_chk_rd1 <= full_chk_d1; + full_chk_rd2 <= full_chk_rd1; + END IF; + END PROCESS; + + RESET_EN <= reset_en_rd2; + + + data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE + ----------------------------------------------------- + -- WR_EN GENERATION + ----------------------------------------------------- + gen_rand_wr_en:fifo_4k_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+1 + ) + PORT MAP( + CLK => WR_CLK, + RESET => RESET_WR, + RANDOM_NUM => wr_en_gen, + ENABLE => '1' + ); + + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + wr_en_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control; + ELSE + wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4)); + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------- + -- WR_EN CONTROL + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + wr_cntr <= (OTHERS => '0'); + wr_control <= '1'; + full_as_timeout <= (OTHERS => '0'); + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + IF(wr_en_i = '1') THEN + wr_cntr <= wr_cntr + "1"; + END IF; + full_as_timeout <= (OTHERS => '0'); + ELSE + wr_cntr <= (OTHERS => '0'); + IF(rd_en_wr2 = '0') THEN + IF(wr_en_i = '1') THEN + full_as_timeout <= full_as_timeout + "1"; + END IF; + ELSE + full_as_timeout <= (OTHERS => '0'); + END IF; + END IF; + + wr_control <= NOT wr_cntr(wr_cntr'high); + + END IF; + END PROCESS; + + ----------------------------------------------------- + -- RD_EN GENERATION + ----------------------------------------------------- + gen_rand_rd_en:fifo_4k_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED + ) + PORT MAP( + CLK => RD_CLK, + RESET => RESET_RD, + RANDOM_NUM => rd_en_gen, + ENABLE => '1' + ); + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + rd_en_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0') THEN + rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4)); + ELSE + rd_en_i <= rd_en_gen(0) OR rd_en_gen(6); + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------- + -- RD_EN CONTROL + ----------------------------------------------------- + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + rd_cntr <= (OTHERS => '0'); + rd_control <= '1'; + empty_as_timeout <= (OTHERS => '0'); + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0') THEN + IF(rd_en_i = '1') THEN + rd_cntr <= rd_cntr + "1"; + END IF; + empty_as_timeout <= (OTHERS => '0'); + ELSE + rd_cntr <= (OTHERS => '0'); + IF(wr_en_rd2 = '0') THEN + IF(rd_en_i = '1') THEN + empty_as_timeout <= empty_as_timeout + "1"; + END IF; + ELSE + empty_as_timeout <= (OTHERS => '0'); + END IF; + END IF; + + rd_control <= NOT rd_cntr(rd_cntr'high); + + END IF; + END PROCESS; + + ----------------------------------------------------- + -- STIMULUS CONTROL + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + state <= '0'; + reset_en_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + CASE state IS + WHEN '0' => + IF(FULL = '1' AND empty_wr_dom2 = '0') THEN + state <= '1'; + reset_en_i <= '0'; + END IF; + WHEN '1' => + IF(empty_wr_dom2 = '1' AND FULL = '0') THEN + state <= '0'; + reset_en_i <= '1'; + END IF; + WHEN OTHERS => state <= state; + END CASE; + END IF; + END PROCESS; + END GENERATE data_fifo_en; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd new file mode 100755 index 000000000..46d4ac9cf --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd @@ -0,0 +1,350 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_pkg.vhd +-- +-- Description: +-- This is the demo testbench package file for FIFO Generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.std_logic_arith.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +PACKAGE fifo_4k_2clk_pkg IS + + FUNCTION divroundup ( + data_value : INTEGER; + divisor : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : INTEGER; + false_case : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : STD_LOGIC; + false_case : STD_LOGIC) + RETURN STD_LOGIC; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : TIME; + false_case : TIME) + RETURN TIME; + ------------------------ + FUNCTION log2roundup ( + data_value : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION hexstr_to_std_logic_vec( + arg1 : string; + size : integer ) + RETURN std_logic_vector; + ------------------------ + COMPONENT fifo_4k_2clk_rng IS + GENERIC (WIDTH : integer := 8; + SEED : integer := 3); + PORT ( + CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + ENABLE : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_4k_2clk_dgen IS + GENERIC ( + C_DIN_WIDTH : INTEGER := 32; + C_DOUT_WIDTH : INTEGER := 32; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT ( + RESET : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + PRC_WR_EN : IN STD_LOGIC; + FULL : IN STD_LOGIC; + WR_EN : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_4k_2clk_dverif IS + GENERIC( + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_USE_EMBEDDED_REG : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + PRC_RD_EN : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + RD_EN : OUT STD_LOGIC; + DOUT_CHK : OUT STD_LOGIC + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_4k_2clk_pctrl IS + GENERIC( + AXI_CHANNEL : STRING := "NONE"; + C_APPLICATION_TYPE : INTEGER := 0; + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_WR_PNTR_WIDTH : INTEGER := 0; + C_RD_PNTR_WIDTH : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 2; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET_WR : IN STD_LOGIC; + RESET_RD : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + FULL : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + ALMOST_FULL : IN STD_LOGIC; + ALMOST_EMPTY : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + DOUT_CHK : IN STD_LOGIC; + PRC_WR_EN : OUT STD_LOGIC; + PRC_RD_EN : OUT STD_LOGIC; + RESET_EN : OUT STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + COMPONENT fifo_4k_2clk_synth IS + GENERIC( + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 0; + TB_SEED : INTEGER := 1 + ); + PORT( + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + COMPONENT fifo_4k_2clk_exdes IS + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + + END COMPONENT; + ------------------------ + + +END fifo_4k_2clk_pkg; + + + +PACKAGE BODY fifo_4k_2clk_pkg IS + + FUNCTION divroundup ( + data_value : INTEGER; + divisor : INTEGER) + RETURN INTEGER IS + VARIABLE div : INTEGER; + BEGIN + div := data_value/divisor; + IF ( (data_value MOD divisor) /= 0) THEN + div := div+1; + END IF; + RETURN div; + END divroundup; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : INTEGER; + false_case : INTEGER) + RETURN INTEGER IS + VARIABLE retval : INTEGER := 0; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : STD_LOGIC; + false_case : STD_LOGIC) + RETURN STD_LOGIC IS + VARIABLE retval : STD_LOGIC := '0'; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : TIME; + false_case : TIME) + RETURN TIME IS + VARIABLE retval : TIME := 0 ps; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + ------------------------------- + FUNCTION log2roundup ( + data_value : INTEGER) + RETURN INTEGER IS + + VARIABLE width : INTEGER := 0; + VARIABLE cnt : INTEGER := 1; + BEGIN + IF (data_value <= 1) THEN + width := 1; + ELSE + WHILE (cnt < data_value) LOOP + width := width + 1; + cnt := cnt *2; + END LOOP; + END IF; + + RETURN width; + END log2roundup; + ------------------------------------------------------------------------------ + -- hexstr_to_std_logic_vec + -- This function converts a hex string to a std_logic_vector + ------------------------------------------------------------------------------ + FUNCTION hexstr_to_std_logic_vec( + arg1 : string; + size : integer ) + RETURN std_logic_vector IS + VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE bin : std_logic_vector(3 DOWNTO 0); + VARIABLE index : integer := 0; + BEGIN + FOR i IN arg1'reverse_range LOOP + CASE arg1(i) IS + WHEN '0' => bin := (OTHERS => '0'); + WHEN '1' => bin := (0 => '1', OTHERS => '0'); + WHEN '2' => bin := (1 => '1', OTHERS => '0'); + WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); + WHEN '4' => bin := (2 => '1', OTHERS => '0'); + WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); + WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); + WHEN '7' => bin := (3 => '0', OTHERS => '1'); + WHEN '8' => bin := (3 => '1', OTHERS => '0'); + WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); + WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); + WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); + WHEN 'B' => bin := (2 => '0', OTHERS => '1'); + WHEN 'b' => bin := (2 => '0', OTHERS => '1'); + WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); + WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); + WHEN 'D' => bin := (1 => '0', OTHERS => '1'); + WHEN 'd' => bin := (1 => '0', OTHERS => '1'); + WHEN 'E' => bin := (0 => '0', OTHERS => '1'); + WHEN 'e' => bin := (0 => '0', OTHERS => '1'); + WHEN 'F' => bin := (OTHERS => '1'); + WHEN 'f' => bin := (OTHERS => '1'); + WHEN OTHERS => + FOR j IN 0 TO 3 LOOP + bin(j) := 'X'; + END LOOP; + END CASE; + FOR j IN 0 TO 3 LOOP + IF (index*4)+j < size THEN + result((index*4)+j) := bin(j); + END IF; + END LOOP; + index := index + 1; + END LOOP; + RETURN result; + END hexstr_to_std_logic_vec; + +END fifo_4k_2clk_pkg; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd new file mode 100755 index 000000000..bed58d88e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd @@ -0,0 +1,100 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_rng.vhd +-- +-- Description: +-- Used for generation of pseudo random numbers +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +ENTITY fifo_4k_2clk_rng IS + GENERIC ( + WIDTH : integer := 8; + SEED : integer := 3); + PORT ( + CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + ENABLE : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)); +END ENTITY; + +ARCHITECTURE rg_arch OF fifo_4k_2clk_rng IS +BEGIN +PROCESS (CLK,RESET) + VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width); + VARIABLE temp : STD_LOGIC := '0'; +BEGIN + IF(RESET = '1') THEN + rand_temp := conv_std_logic_vector(SEED,width); + temp := '0'; + ELSIF (CLK'event AND CLK = '1') THEN + IF (ENABLE = '1') THEN + temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5); + rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0); + rand_temp(0) := temp; + END IF; + END IF; + + RANDOM_NUM <= rand_temp; + +END PROCESS; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd new file mode 100755 index 000000000..4149735c5 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd @@ -0,0 +1,300 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_synth.vhd +-- +-- Description: +-- This is the demo testbench for fifo_generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + +LIBRARY ieee; +USE ieee.STD_LOGIC_1164.ALL; +USE ieee.STD_LOGIC_unsigned.ALL; +USE IEEE.STD_LOGIC_arith.ALL; +USE ieee.numeric_std.ALL; +USE ieee.STD_LOGIC_misc.ALL; + +LIBRARY std; +USE std.textio.ALL; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY fifo_4k_2clk_synth IS + GENERIC( + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 0; + TB_SEED : INTEGER := 1 + ); + PORT( + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END ENTITY; + +ARCHITECTURE simulation_arch OF fifo_4k_2clk_synth IS + + -- FIFO interface signal declarations + SIGNAL wr_clk_i : STD_LOGIC; + SIGNAL rd_clk_i : STD_LOGIC; + SIGNAL wr_data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0); + SIGNAL rd_data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0); + SIGNAL rst : STD_LOGIC; + SIGNAL wr_en : STD_LOGIC; + SIGNAL rd_en : STD_LOGIC; + SIGNAL din : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL dout : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL full : STD_LOGIC; + SIGNAL empty : STD_LOGIC; + -- TB Signals + SIGNAL wr_data : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL dout_i : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL wr_en_i : STD_LOGIC := '0'; + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL full_i : STD_LOGIC := '0'; + SIGNAL empty_i : STD_LOGIC := '0'; + SIGNAL almost_full_i : STD_LOGIC := '0'; + SIGNAL almost_empty_i : STD_LOGIC := '0'; + SIGNAL prc_we_i : STD_LOGIC := '0'; + SIGNAL prc_re_i : STD_LOGIC := '0'; + SIGNAL dout_chk_i : STD_LOGIC := '0'; + SIGNAL rst_int_rd : STD_LOGIC := '0'; + SIGNAL rst_int_wr : STD_LOGIC := '0'; + SIGNAL rst_s_wr1 : STD_LOGIC := '0'; + SIGNAL rst_s_wr2 : STD_LOGIC := '0'; + SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL rst_s_wr3 : STD_LOGIC := '0'; + SIGNAL rst_s_rd : STD_LOGIC := '0'; + SIGNAL reset_en : STD_LOGIC := '0'; + SIGNAL rst_async_wr1 : STD_LOGIC := '0'; + SIGNAL rst_async_wr2 : STD_LOGIC := '0'; + SIGNAL rst_async_wr3 : STD_LOGIC := '0'; + SIGNAL rst_async_rd1 : STD_LOGIC := '0'; + SIGNAL rst_async_rd2 : STD_LOGIC := '0'; + SIGNAL rst_async_rd3 : STD_LOGIC := '0'; + + + BEGIN + + ---- Reset generation logic ----- + rst_int_wr <= rst_async_wr3 OR rst_s_wr3; + rst_int_rd <= rst_async_rd3 OR rst_s_rd; + + --Testbench reset synchronization + PROCESS(rd_clk_i,RESET) + BEGIN + IF(RESET = '1') THEN + rst_async_rd1 <= '1'; + rst_async_rd2 <= '1'; + rst_async_rd3 <= '1'; + ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN + rst_async_rd1 <= RESET; + rst_async_rd2 <= rst_async_rd1; + rst_async_rd3 <= rst_async_rd2; + END IF; + END PROCESS; + + PROCESS(wr_clk_i,RESET) + BEGIN + IF(RESET = '1') THEN + rst_async_wr1 <= '1'; + rst_async_wr2 <= '1'; + rst_async_wr3 <= '1'; + ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN + rst_async_wr1 <= RESET; + rst_async_wr2 <= rst_async_wr1; + rst_async_wr3 <= rst_async_wr2; + END IF; + END PROCESS; + + --Soft reset for core and testbench + PROCESS(rd_clk_i) + BEGIN + IF(rd_clk_i'event AND rd_clk_i='1') THEN + rst_gen_rd <= rst_gen_rd + "1"; + IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN + rst_s_rd <= '1'; + assert false + report "Reset applied..Memory Collision checks are not valid" + severity note; + ELSE + IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN + rst_s_rd <= '0'; + END IF; + END IF; + END IF; + END PROCESS; + + PROCESS(wr_clk_i) + BEGIN + IF(wr_clk_i'event AND wr_clk_i='1') THEN + rst_s_wr1 <= rst_s_rd; + rst_s_wr2 <= rst_s_wr1; + rst_s_wr3 <= rst_s_wr2; + IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN + assert false + report "Reset removed..Memory Collision checks are valid" + severity note; + END IF; + END IF; + END PROCESS; + ------------------ + + ---- Clock buffers for testbench ---- + wr_clk_i <= WR_CLK; + rd_clk_i <= RD_CLK; + ------------------ + + rst <= RESET OR rst_s_rd AFTER 12 ns; + din <= wr_data; + dout_i <= dout; + wr_en <= wr_en_i; + rd_en <= rd_en_i; + full_i <= full; + empty_i <= empty; + + fg_dg_nv: fifo_4k_2clk_dgen + GENERIC MAP ( + C_DIN_WIDTH => 72, + C_DOUT_WIDTH => 72, + TB_SEED => TB_SEED, + C_CH_TYPE => 0 + ) + PORT MAP ( -- Write Port + RESET => rst_int_wr, + WR_CLK => wr_clk_i, + PRC_WR_EN => prc_we_i, + FULL => full_i, + WR_EN => wr_en_i, + WR_DATA => wr_data + ); + + fg_dv_nv: fifo_4k_2clk_dverif + GENERIC MAP ( + C_DOUT_WIDTH => 72, + C_DIN_WIDTH => 72, + C_USE_EMBEDDED_REG => 0, + TB_SEED => TB_SEED, + C_CH_TYPE => 0 + ) + PORT MAP( + RESET => rst_int_rd, + RD_CLK => rd_clk_i, + PRC_RD_EN => prc_re_i, + RD_EN => rd_en_i, + EMPTY => empty_i, + DATA_OUT => dout_i, + DOUT_CHK => dout_chk_i + ); + + fg_pc_nv: fifo_4k_2clk_pctrl + GENERIC MAP ( + AXI_CHANNEL => "Native", + C_APPLICATION_TYPE => 0, + C_DOUT_WIDTH => 72, + C_DIN_WIDTH => 72, + C_WR_PNTR_WIDTH => 9, + C_RD_PNTR_WIDTH => 9, + C_CH_TYPE => 0, + FREEZEON_ERROR => FREEZEON_ERROR, + TB_SEED => TB_SEED, + TB_STOP_CNT => TB_STOP_CNT + ) + PORT MAP( + RESET_WR => rst_int_wr, + RESET_RD => rst_int_rd, + RESET_EN => reset_en, + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + PRC_WR_EN => prc_we_i, + PRC_RD_EN => prc_re_i, + FULL => full_i, + ALMOST_FULL => almost_full_i, + ALMOST_EMPTY => almost_empty_i, + DOUT_CHK => dout_chk_i, + EMPTY => empty_i, + DATA_IN => wr_data, + DATA_OUT => dout, + SIM_DONE => SIM_DONE, + STATUS => STATUS + ); + + + + + + fifo_4k_2clk_inst : fifo_4k_2clk_exdes + PORT MAP ( + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + WR_DATA_COUNT => wr_data_count, + RD_DATA_COUNT => rd_data_count, + RST => rst, + WR_EN => wr_en, + RD_EN => rd_en, + DIN => din, + DOUT => dout, + FULL => full, + EMPTY => empty); + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd new file mode 100755 index 000000000..51d699e21 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd @@ -0,0 +1,208 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_tb.vhd +-- +-- Description: +-- This is the demo testbench top file for fifo_generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +LIBRARY std; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +USE IEEE.std_logic_arith.ALL; +USE IEEE.std_logic_misc.ALL; +USE ieee.numeric_std.ALL; +USE ieee.std_logic_textio.ALL; +USE std.textio.ALL; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +ENTITY fifo_4k_2clk_tb IS +END ENTITY; + + +ARCHITECTURE fifo_4k_2clk_arch OF fifo_4k_2clk_tb IS + SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + SIGNAL wr_clk : STD_LOGIC; + SIGNAL rd_clk : STD_LOGIC; + SIGNAL reset : STD_LOGIC; + SIGNAL sim_done : STD_LOGIC := '0'; + SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); + -- Write and Read clock periods + CONSTANT wr_clk_period_by_2 : TIME := 200 ns; + CONSTANT rd_clk_period_by_2 : TIME := 100 ns; + -- Procedures to display strings + PROCEDURE disp_str(CONSTANT str:IN STRING) IS + variable dp_l : line := null; + BEGIN + write(dp_l,str); + writeline(output,dp_l); + END PROCEDURE; + + PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS + variable dp_lx : line := null; + BEGIN + hwrite(dp_lx,hex); + writeline(output,dp_lx); + END PROCEDURE; + +BEGIN + + -- Generation of clock + + PROCESS BEGIN + WAIT FOR 400 ns; -- Wait for global reset + WHILE 1 = 1 LOOP + wr_clk <= '0'; + WAIT FOR wr_clk_period_by_2; + wr_clk <= '1'; + WAIT FOR wr_clk_period_by_2; + END LOOP; + END PROCESS; + + PROCESS BEGIN + WAIT FOR 200 ns;-- Wait for global reset + WHILE 1 = 1 LOOP + rd_clk <= '0'; + WAIT FOR rd_clk_period_by_2; + rd_clk <= '1'; + WAIT FOR rd_clk_period_by_2; + END LOOP; + END PROCESS; + + -- Generation of Reset + + PROCESS BEGIN + reset <= '1'; + WAIT FOR 4200 ns; + reset <= '0'; + WAIT; + END PROCESS; + + + -- Error message printing based on STATUS signal from fifo_4k_2clk_synth + + PROCESS(status) + BEGIN + IF(status /= "0" AND status /= "1") THEN + disp_str("STATUS:"); + disp_hex(status); + END IF; + + IF(status(7) = '1') THEN + assert false + report "Data mismatch found" + severity error; + END IF; + + IF(status(1) = '1') THEN + END IF; + + IF(status(5) = '1') THEN + assert false + report "Empty flag Mismatch/timeout" + severity error; + END IF; + + IF(status(6) = '1') THEN + assert false + report "Full Flag Mismatch/timeout" + severity error; + END IF; + END PROCESS; + + + PROCESS + BEGIN + wait until sim_done = '1'; + IF(status /= "0" AND status /= "1") THEN + assert false + report "Simulation failed" + severity failure; + ELSE + assert false + report "Test Completed Successfully" + severity failure; + END IF; + END PROCESS; + + PROCESS + BEGIN + wait for 400 ms; + assert false + report "Test bench timed out" + severity failure; + END PROCESS; + + -- Instance of fifo_4k_2clk_synth + + fifo_4k_2clk_synth_inst:fifo_4k_2clk_synth + GENERIC MAP( + FREEZEON_ERROR => 0, + TB_STOP_CNT => 2, + TB_SEED => 76 + ) + PORT MAP( + WR_CLK => wr_clk, + RD_CLK => rd_clk, + RESET => reset, + SIM_DONE => sim_done, + STATUS => status + ); + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.bat new file mode 100755 index 000000000..3d0783055 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.bat @@ -0,0 +1,63 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ..\\..\\..\\fifo_4k_2clk.v +vhpcomp -work work ..\\..\\example_design\\fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhpcomp -work work ..\\fifo_4k_2clk_pkg.vhd +vhpcomp -work work ..\\fifo_4k_2clk_rng.vhd +vhpcomp -work work ..\\fifo_4k_2clk_dgen.vhd +vhpcomp -work work ..\\fifo_4k_2clk_dverif.vhd +vhpcomp -work work ..\\fifo_4k_2clk_pctrl.vhd +vhpcomp -work work ..\\fifo_4k_2clk_synth.vhd +vhpcomp -work work ..\\fifo_4k_2clk_tb.vhd + +vlogcomp -work work $XILINX\\verilog\\src\\glbl.v +fuse work.fifo_4k_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_4k_2clk_tb.exe + +.\\fifo_4k_2clk_tb.exe -gui -tclbatch .\\wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.sh new file mode 100755 index 000000000..c3abd5a51 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.sh @@ -0,0 +1,65 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ../../../fifo_4k_2clk.v +vhpcomp -work work ../../example_design/fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhpcomp -work work ../fifo_4k_2clk_pkg.vhd +vhpcomp -work work ../fifo_4k_2clk_rng.vhd +vhpcomp -work work ../fifo_4k_2clk_dgen.vhd +vhpcomp -work work ../fifo_4k_2clk_dverif.vhd +vhpcomp -work work ../fifo_4k_2clk_pctrl.vhd +vhpcomp -work work ../fifo_4k_2clk_synth.vhd +vhpcomp -work work ../fifo_4k_2clk_tb.vhd + +vlogcomp -work work $XILINX/verilog/src/glbl.v +fuse work.fifo_4k_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_4k_2clk_tb.exe + +./fifo_4k_2clk_tb.exe -gui -tclbatch ./wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.bat new file mode 100755 index 000000000..35375ce20 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.bat @@ -0,0 +1,47 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.do b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.do new file mode 100755 index 000000000..af53abefb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.do @@ -0,0 +1,74 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../../fifo_4k_2clk.v +vcom -work work ../../example_design/fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vcom -work work ../fifo_4k_2clk_pkg.vhd +vcom -work work ../fifo_4k_2clk_rng.vhd +vcom -work work ../fifo_4k_2clk_dgen.vhd +vcom -work work ../fifo_4k_2clk_dverif.vhd +vcom -work work ../fifo_4k_2clk_pctrl.vhd +vcom -work work ../fifo_4k_2clk_synth.vhd +vcom -work work ../fifo_4k_2clk_tb.vhd + +vlog -work work $env(XILINX)/verilog/src/glbl.v +vsim -t ps -voptargs="+acc" -L XilinxCoreLib_ver -L unisims_ver glbl work.fifo_4k_2clk_tb + +add log -r /* +do wave_mti.do +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.sh new file mode 100755 index 000000000..edb1b0dd9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.sh @@ -0,0 +1,49 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_ncsim.sh new file mode 100755 index 000000000..0d3376452 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_ncsim.sh @@ -0,0 +1,69 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +mkdir work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +ncvlog -work work ../../../fifo_4k_2clk.v +ncvhdl -v93 -work work ../../example_design/fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +ncvhdl -v93 -work work ../fifo_4k_2clk_pkg.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_rng.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_dgen.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_dverif.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_pctrl.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_synth.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_tb.vhd + +echo "Elaborating Design" +ncvlog -work work $XILINX/verilog/src/glbl.v +ncelab -access +rwc glbl work.fifo_4k_2clk_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_4k_2clk_tb + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_vcs.sh new file mode 100755 index 000000000..8c26af20c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_vcs.sh @@ -0,0 +1,69 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogan +v2k ../../../fifo_4k_2clk.v +vhdlan ../../example_design/fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhdlan ../fifo_4k_2clk_pkg.vhd +vhdlan ../fifo_4k_2clk_rng.vhd +vhdlan ../fifo_4k_2clk_dgen.vhd +vhdlan ../fifo_4k_2clk_dverif.vhd +vhdlan ../fifo_4k_2clk_pctrl.vhd +vhdlan ../fifo_4k_2clk_synth.vhd +vhdlan ../fifo_4k_2clk_tb.vhd + +echo "Elaborating Design" +vlogan +v2k $XILINX/verilog/src/glbl.v +vcs -time_res 1ps +vcs+lic+wait -debug fifo_4k_2clk_tb glbl + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/ucli_commands.key b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/ucli_commands.key new file mode 100755 index 000000000..9c95a2ade --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/ucli_commands.key @@ -0,0 +1,4 @@ +dump -file fifo_4k_2clk.vpd -type VPD +dump -add fifo_4k_2clk_tb +run +quit diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/vcs_session.tcl new file mode 100755 index 000000000..b9ef9837a --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/vcs_session.tcl @@ -0,0 +1,77 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {fifo_4k_2clk.vpd}] } { + gui_open_db -design V1 -file fifo_4k_2clk.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + + +gui_open_window Wave +gui_sg_create fifo_4k_2clk_Group +gui_list_add_group -id Wave.1 {fifo_4k_2clk_Group} + +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +gui_sg_addsignal -group fifo_4k_2clk_Group WRITE -divider +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +gui_sg_addsignal -group fifo_4k_2clk_Group READ -divider +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_isim.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_isim.tcl new file mode 100755 index 000000000..10be1a965 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_isim.tcl @@ -0,0 +1,68 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_isim.tcl +# +# Description: +# This is the ISIM wave form file. +# +#-------------------------------------------------------------------------------- +wcfg new +isim set radix hex +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +run all +quit + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_mti.do b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_mti.do new file mode 100755 index 000000000..adc4cb8d7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_mti.do @@ -0,0 +1,88 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +# Filename: wave_mti.do +# +# Description: +# This is the modelsim wave form file. +# +#-------------------------------------------------------------------------------- + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +add wave -noupdate -divider WRITE +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DIN +add wave -noupdate -divider READ +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DOUT + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2164886 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_ncsim.sv b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_ncsim.sv new file mode 100755 index 000000000..51819bad9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_ncsim.sv @@ -0,0 +1,70 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_ncsim.sv +# +# Description: +# This is the IUS wave form file. +# +#-------------------------------------------------------------------------------- + +window new WaveWindow -name "Waves for FIFO Generator Example Design" +waveform using "Waves for FIFO Generator Example Design" + +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +waveform add -label WRITE +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +waveform add -label READ +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +console submit -using simulator -wait no "run" diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.bat new file mode 100755 index 000000000..a6f8ce91f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.bat @@ -0,0 +1,61 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ..\\..\\implement\\results\\routed.v + +echo "Compiling Test Bench Files" +vhpcomp -work work ..\\fifo_4k_2clk_pkg.vhd +vhpcomp -work work ..\\fifo_4k_2clk_rng.vhd +vhpcomp -work work ..\\fifo_4k_2clk_dgen.vhd +vhpcomp -work work ..\\fifo_4k_2clk_dverif.vhd +vhpcomp -work work ..\\fifo_4k_2clk_pctrl.vhd +vhpcomp -work work ..\\fifo_4k_2clk_synth.vhd +vhpcomp -work work ..\\fifo_4k_2clk_tb.vhd + +fuse work.fifo_4k_2clk_tb work.glbl -L simprims_ver -o fifo_4k_2clk_tb.exe + +.\\fifo_4k_2clk_tb.exe -sdfmax /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst=..\\..\\implement\\results\\routed.sdf -gui -tclbatch .\\wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.sh new file mode 100755 index 000000000..f5ad36b7e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.sh @@ -0,0 +1,63 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vhpcomp -work work ../fifo_4k_2clk_pkg.vhd +vhpcomp -work work ../fifo_4k_2clk_rng.vhd +vhpcomp -work work ../fifo_4k_2clk_dgen.vhd +vhpcomp -work work ../fifo_4k_2clk_dverif.vhd +vhpcomp -work work ../fifo_4k_2clk_pctrl.vhd +vhpcomp -work work ../fifo_4k_2clk_synth.vhd +vhpcomp -work work ../fifo_4k_2clk_tb.vhd + +fuse work.fifo_4k_2clk_tb work.glbl -L simprims_ver -o fifo_4k_2clk_tb.exe + +./fifo_4k_2clk_tb.exe -sdfmax /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst=../../implement/results/routed.sdf -gui -tclbatch ./wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.bat new file mode 100755 index 000000000..35375ce20 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.bat @@ -0,0 +1,47 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.do b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.do new file mode 100755 index 000000000..74e930a13 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.do @@ -0,0 +1,72 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vcom -work work ../fifo_4k_2clk_pkg.vhd +vcom -work work ../fifo_4k_2clk_rng.vhd +vcom -work work ../fifo_4k_2clk_dgen.vhd +vcom -work work ../fifo_4k_2clk_dverif.vhd +vcom -work work ../fifo_4k_2clk_pctrl.vhd +vcom -work work ../fifo_4k_2clk_synth.vhd +vcom -work work ../fifo_4k_2clk_tb.vhd + +vsim -t ps -voptargs="+acc" +transport_int_delays -L simprims_ver glbl -sdfmax /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst=../../implement/results/routed.sdf work.fifo_4k_2clk_tb + +add log -r /* +do wave_mti.do +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.sh new file mode 100755 index 000000000..edb1b0dd9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.sh @@ -0,0 +1,49 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_ncsim.sh new file mode 100755 index 000000000..a1967adcf --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_ncsim.sh @@ -0,0 +1,73 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +mkdir work +echo "Compiling Core Verilog UNISIM/Behavioral model" +ncvlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +ncvhdl -v93 -work work ../fifo_4k_2clk_pkg.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_rng.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_dgen.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_dverif.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_pctrl.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_synth.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_tb.vhd + +echo "Compiling SDF file" +ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X + +echo "Generating SDF command file" +echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd +echo 'SCOPE = :fifo_4k_2clk_synth_inst:fifo_4k_2clk_inst,' >> sdf.cmd +echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd + +echo "Elaborating Design" +ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd work.fifo_4k_2clk_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_4k_2clk_tb diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_vcs.sh new file mode 100755 index 000000000..f62f540be --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_vcs.sh @@ -0,0 +1,67 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogan +v2k ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vhdlan ../fifo_4k_2clk_pkg.vhd +vhdlan ../fifo_4k_2clk_rng.vhd +vhdlan ../fifo_4k_2clk_dgen.vhd +vhdlan ../fifo_4k_2clk_dverif.vhd +vhdlan ../fifo_4k_2clk_pctrl.vhd +vhdlan ../fifo_4k_2clk_synth.vhd +vhdlan ../fifo_4k_2clk_tb.vhd + +echo "Elaborating Design" +vcs -time_res 1ps +neg_tchk -sdf max:/fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst:../../implement/results/routed.sdf +vcs+lic+wait -debug fifo_4k_2clk_tb glbl + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/ucli_commands.key b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/ucli_commands.key new file mode 100755 index 000000000..9c95a2ade --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/ucli_commands.key @@ -0,0 +1,4 @@ +dump -file fifo_4k_2clk.vpd -type VPD +dump -add fifo_4k_2clk_tb +run +quit diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/vcs_session.tcl new file mode 100755 index 000000000..28ebc1163 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/vcs_session.tcl @@ -0,0 +1,76 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {fifo_4k_2clk.vpd}] } { + gui_open_db -design V1 -file fifo_4k_2clk.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + +gui_open_window Wave +gui_sg_create fifo_4k_2clk_Group +gui_list_add_group -id Wave.1 {fifo_4k_2clk_Group} + +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +gui_sg_addsignal -group fifo_4k_2clk_Group WRITE -divider +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +gui_sg_addsignal -group fifo_4k_2clk_Group READ -divider +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_isim.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_isim.tcl new file mode 100755 index 000000000..10be1a965 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_isim.tcl @@ -0,0 +1,68 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_isim.tcl +# +# Description: +# This is the ISIM wave form file. +# +#-------------------------------------------------------------------------------- +wcfg new +isim set radix hex +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +run all +quit + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_mti.do b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_mti.do new file mode 100755 index 000000000..adc4cb8d7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_mti.do @@ -0,0 +1,88 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +# Filename: wave_mti.do +# +# Description: +# This is the modelsim wave form file. +# +#-------------------------------------------------------------------------------- + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +add wave -noupdate -divider WRITE +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DIN +add wave -noupdate -divider READ +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DOUT + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2164886 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_ncsim.sv b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_ncsim.sv new file mode 100755 index 000000000..51819bad9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_ncsim.sv @@ -0,0 +1,70 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_ncsim.sv +# +# Description: +# This is the IUS wave form file. +# +#-------------------------------------------------------------------------------- + +window new WaveWindow -name "Waves for FIFO Generator Example Design" +waveform using "Waves for FIFO Generator Example Design" + +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +waveform add -label WRITE +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +waveform add -label READ +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +console submit -using simulator -wait no "run" diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_flist.txt b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_flist.txt new file mode 100644 index 000000000..e33a4de1c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_flist.txt @@ -0,0 +1,56 @@ +# Output products list for <fifo_4k_2clk> +fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt +fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html +fifo_4k_2clk/doc/pg057-fifo-generator.pdf +fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf +fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd +fifo_4k_2clk/fifo_generator_v9_3_readme.txt +fifo_4k_2clk/implement/implement.bat +fifo_4k_2clk/implement/implement.sh +fifo_4k_2clk/implement/implement_synplify.bat +fifo_4k_2clk/implement/implement_synplify.sh +fifo_4k_2clk/implement/planAhead_ise.bat +fifo_4k_2clk/implement/planAhead_ise.sh +fifo_4k_2clk/implement/planAhead_ise.tcl +fifo_4k_2clk/implement/xst.prj +fifo_4k_2clk/implement/xst.scr +fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd +fifo_4k_2clk/simulation/functional/simulate_isim.bat +fifo_4k_2clk/simulation/functional/simulate_isim.sh +fifo_4k_2clk/simulation/functional/simulate_mti.bat +fifo_4k_2clk/simulation/functional/simulate_mti.do +fifo_4k_2clk/simulation/functional/simulate_mti.sh +fifo_4k_2clk/simulation/functional/simulate_ncsim.sh +fifo_4k_2clk/simulation/functional/simulate_vcs.sh +fifo_4k_2clk/simulation/functional/ucli_commands.key +fifo_4k_2clk/simulation/functional/vcs_session.tcl +fifo_4k_2clk/simulation/functional/wave_isim.tcl +fifo_4k_2clk/simulation/functional/wave_mti.do +fifo_4k_2clk/simulation/functional/wave_ncsim.sv +fifo_4k_2clk/simulation/timing/simulate_isim.bat +fifo_4k_2clk/simulation/timing/simulate_isim.sh +fifo_4k_2clk/simulation/timing/simulate_mti.bat +fifo_4k_2clk/simulation/timing/simulate_mti.do +fifo_4k_2clk/simulation/timing/simulate_mti.sh +fifo_4k_2clk/simulation/timing/simulate_ncsim.sh +fifo_4k_2clk/simulation/timing/simulate_vcs.sh +fifo_4k_2clk/simulation/timing/ucli_commands.key +fifo_4k_2clk/simulation/timing/vcs_session.tcl +fifo_4k_2clk/simulation/timing/wave_isim.tcl +fifo_4k_2clk/simulation/timing/wave_mti.do +fifo_4k_2clk/simulation/timing/wave_ncsim.sv +fifo_4k_2clk.asy +fifo_4k_2clk.gise +fifo_4k_2clk.ngc +fifo_4k_2clk.v +fifo_4k_2clk.veo +fifo_4k_2clk.xco +fifo_4k_2clk.xise +fifo_4k_2clk_flist.txt +fifo_4k_2clk_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_xmdf.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_xmdf.tcl new file mode 100644 index 000000000..bdc5c355d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_xmdf.tcl @@ -0,0 +1,251 @@ +# The package naming convention is <core_name>_xmdf +package provide fifo_4k_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is <core_name>_xmdf +namespace eval ::fifo_4k_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_4k_2clk_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: <module_name> +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_4k_2clk +} +# ::fifo_4k_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_4k_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/doc/pg057-fifo-generator.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/fifo_generator_v9_3_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement_synplify.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement_synplify.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/planAhead_ise.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/planAhead_ise.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/planAhead_ise.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/wave_isim.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/wave_isim.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_4k_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.asy b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.asy new file mode 100644 index 000000000..1c03599f3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_short_2clk +RECTANGLE Normal 32 32 800 4064 +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Normal 0 208 32 208 +PIN 0 208 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Wide 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName din[71:0] +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 464 32 464 +PIN 0 464 LEFT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 0 624 32 624 +PIN 0 624 LEFT 36 +PINATTR PinName wr_data_count[5:0] +PINATTR Polarity OUT +LINE Normal 832 240 800 240 +PIN 832 240 RIGHT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Wide 832 272 800 272 +PIN 832 272 RIGHT 36 +PINATTR PinName dout[71:0] +PINATTR Polarity OUT +LINE Normal 832 304 800 304 +PIN 832 304 RIGHT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 832 496 800 496 +PIN 832 496 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 832 656 800 656 +PIN 832 656 RIGHT 36 +PINATTR PinName rd_data_count[5:0] +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise new file mode 100644 index 000000000..ea47d0f4b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise @@ -0,0 +1,31 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_short_2clk.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_short_2clk.asy" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_short_2clk.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ncf b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ncf new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ncf diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ngc b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ngc new file mode 100644 index 000000000..ec6b0ff10 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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a5=111C?ik4H2f:?!g32>1b9h4?::k43?6=3`i26=44ob`94?=zj:ii6=4;:183!b42020D>jj;I1g=>"f<3=0e8k50;9j32<722ch57>5;naa>5<<uk9o97>53;294~"c;33>7E=ke:J0`<=O=h1/n?4k2:&b0?4<a<o1<75f7683>>idj3:17pl<c183>1<729q/h>468:J0``=O;m30D8o4$c09`7=#i=0<7d;j:188m21=831bo44?::m`f?6=3th94o4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<d<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9454?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<2<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th94;4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<0<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9494?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<6<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th94?4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<4<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th94=4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13c<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;i4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13f<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;o4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13d<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;44?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13=<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;:4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`133<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;84?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`131<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;?4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`134<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;=4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`12c<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:h4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`12a<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:n4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`12g<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:l4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`12<<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9::4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`123<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:84?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`121<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:>4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`127<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:<4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`125<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99k4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`11`<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99n4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`11g<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99l4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`11<<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9954?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`112<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99;4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`110<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9994?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`116<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99<4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`115<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th98k4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`10`<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th98i4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`10f<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th98o4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`10d<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9844?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`10=<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th94i4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<f<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9444?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13`<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;: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d8?:188m25=831b;:4?::m`f?6=3th88o4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`00<<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th88:4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`000<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th88>4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`07c<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8?i4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`07g<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8?44?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`072<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8?84?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`076<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8?<4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`06c<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8>i4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0f=<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8n;4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0f5<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th85l4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0<1<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8:h4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`01=<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th88?4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`06f<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8>l4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`234<72=0;6=u+d28:2>N4ll1C?i74$`696>o2m3:17d9<:188m21=831doo4?::a526=83>1<7>t$e19=3=O;mo0D>j6;%c7>7=n=l0;66g83;29?l102900cnl50;9~f40a290?6=4?{%f0><0<@:nn7E=k9:&b0?4<a<o1<75f7283>>o0?3:17bmm:188yg71m3:187>50z&g7??13A9oi6F<d89'e1<53`?n6=44i6194?=n?>0;66alb;29?xd6>m0;694?:1y'`6<>>2B8hh5G3e;8 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.v b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.v new file mode 100644 index 000000000..82200a502 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.v @@ -0,0 +1,491 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2013 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file fifo_short_2clk.v when simulating +// the core, fifo_short_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module fifo_short_2clk( + rst, + wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + empty, + rd_data_count, + wr_data_count +); + +input rst; +input wr_clk; +input rd_clk; +input [71 : 0] din; +input wr_en; +input rd_en; +output [71 : 0] dout; +output full; +output empty; +output [5 : 0] rd_data_count; +output [5 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V9_3 #( + .C_ADD_NGC_CONSTRAINT(0), + .C_APPLICATION_TYPE_AXIS(0), + .C_APPLICATION_TYPE_RACH(0), + .C_APPLICATION_TYPE_RDCH(0), + .C_APPLICATION_TYPE_WACH(0), + .C_APPLICATION_TYPE_WDCH(0), + .C_APPLICATION_TYPE_WRCH(0), + .C_AXI_ADDR_WIDTH(32), + .C_AXI_ARUSER_WIDTH(1), + .C_AXI_AWUSER_WIDTH(1), + .C_AXI_BUSER_WIDTH(1), + .C_AXI_DATA_WIDTH(64), + .C_AXI_ID_WIDTH(4), + .C_AXI_RUSER_WIDTH(1), + .C_AXI_TYPE(0), + .C_AXI_WUSER_WIDTH(1), + .C_AXIS_TDATA_WIDTH(64), + .C_AXIS_TDEST_WIDTH(4), + .C_AXIS_TID_WIDTH(8), + .C_AXIS_TKEEP_WIDTH(4), + .C_AXIS_TSTRB_WIDTH(4), + .C_AXIS_TUSER_WIDTH(4), + .C_AXIS_TYPE(0), + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(5), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(72), + .C_DIN_WIDTH_AXIS(1), + .C_DIN_WIDTH_RACH(32), + .C_DIN_WIDTH_RDCH(64), + .C_DIN_WIDTH_WACH(32), + .C_DIN_WIDTH_WDCH(64), + .C_DIN_WIDTH_WRCH(2), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(72), + .C_ENABLE_RLOCS(0), + .C_ENABLE_RST_SYNC(1), + .C_ERROR_INJECTION_TYPE(0), + .C_ERROR_INJECTION_TYPE_AXIS(0), + .C_ERROR_INJECTION_TYPE_RACH(0), + .C_ERROR_INJECTION_TYPE_RDCH(0), + .C_ERROR_INJECTION_TYPE_WACH(0), + .C_ERROR_INJECTION_TYPE_WDCH(0), + .C_ERROR_INJECTION_TYPE_WRCH(0), + .C_FAMILY("spartan6"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_AXI_ARUSER(0), + .C_HAS_AXI_AWUSER(0), + .C_HAS_AXI_BUSER(0), + .C_HAS_AXI_RD_CHANNEL(0), + .C_HAS_AXI_RUSER(0), + .C_HAS_AXI_WR_CHANNEL(0), + .C_HAS_AXI_WUSER(0), + .C_HAS_AXIS_TDATA(0), + .C_HAS_AXIS_TDEST(0), + .C_HAS_AXIS_TID(0), + .C_HAS_AXIS_TKEEP(0), + .C_HAS_AXIS_TLAST(0), + .C_HAS_AXIS_TREADY(1), + .C_HAS_AXIS_TSTRB(0), + .C_HAS_AXIS_TUSER(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_DATA_COUNTS_AXIS(0), + .C_HAS_DATA_COUNTS_RACH(0), + .C_HAS_DATA_COUNTS_RDCH(0), + .C_HAS_DATA_COUNTS_WACH(0), + .C_HAS_DATA_COUNTS_WDCH(0), + .C_HAS_DATA_COUNTS_WRCH(0), + .C_HAS_INT_CLK(0), + .C_HAS_MASTER_CE(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_PROG_FLAGS_AXIS(0), + .C_HAS_PROG_FLAGS_RACH(0), + .C_HAS_PROG_FLAGS_RDCH(0), + .C_HAS_PROG_FLAGS_WACH(0), + .C_HAS_PROG_FLAGS_WDCH(0), + .C_HAS_PROG_FLAGS_WRCH(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SLAVE_CE(0), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_IMPLEMENTATION_TYPE_AXIS(1), + .C_IMPLEMENTATION_TYPE_RACH(1), + .C_IMPLEMENTATION_TYPE_RDCH(1), + .C_IMPLEMENTATION_TYPE_WACH(1), + .C_IMPLEMENTATION_TYPE_WDCH(1), + .C_IMPLEMENTATION_TYPE_WRCH(1), + .C_INIT_WR_PNTR_VAL(0), + .C_INTERFACE_TYPE(0), + .C_MEMORY_TYPE(2), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x72"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_EMPTY_TYPE_AXIS(0), + .C_PROG_EMPTY_TYPE_RACH(0), + .C_PROG_EMPTY_TYPE_RDCH(0), + .C_PROG_EMPTY_TYPE_WACH(0), + .C_PROG_EMPTY_TYPE_WDCH(0), + .C_PROG_EMPTY_TYPE_WRCH(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(31), + .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023), + .C_PROG_FULL_THRESH_NEGATE_VAL(30), + .C_PROG_FULL_TYPE(0), + .C_PROG_FULL_TYPE_AXIS(0), + .C_PROG_FULL_TYPE_RACH(0), + .C_PROG_FULL_TYPE_RDCH(0), + .C_PROG_FULL_TYPE_WACH(0), + .C_PROG_FULL_TYPE_WDCH(0), + .C_PROG_FULL_TYPE_WRCH(0), + .C_RACH_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(6), + .C_RD_DEPTH(32), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(5), + .C_RDCH_TYPE(0), + .C_REG_SLICE_MODE_AXIS(0), + .C_REG_SLICE_MODE_RACH(0), + .C_REG_SLICE_MODE_RDCH(0), + .C_REG_SLICE_MODE_WACH(0), + .C_REG_SLICE_MODE_WDCH(0), + .C_REG_SLICE_MODE_WRCH(0), + .C_SYNCHRONIZER_STAGE(2), + .C_UNDERFLOW_LOW(0), + .C_USE_COMMON_OVERFLOW(0), + .C_USE_COMMON_UNDERFLOW(0), + .C_USE_DEFAULT_SETTINGS(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_ECC_AXIS(0), + .C_USE_ECC_RACH(0), + .C_USE_ECC_RDCH(0), + .C_USE_ECC_WACH(0), + .C_USE_ECC_WDCH(0), + .C_USE_ECC_WRCH(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(1), + .C_VALID_LOW(0), + .C_WACH_TYPE(0), + .C_WDCH_TYPE(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(6), + .C_WR_DEPTH(32), + .C_WR_DEPTH_AXIS(1024), + .C_WR_DEPTH_RACH(16), + .C_WR_DEPTH_RDCH(1024), + .C_WR_DEPTH_WACH(16), + .C_WR_DEPTH_WDCH(1024), + .C_WR_DEPTH_WRCH(16), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(5), + .C_WR_PNTR_WIDTH_AXIS(10), + .C_WR_PNTR_WIDTH_RACH(4), + .C_WR_PNTR_WIDTH_RDCH(10), + .C_WR_PNTR_WIDTH_WACH(4), + .C_WR_PNTR_WIDTH_WDCH(10), + .C_WR_PNTR_WIDTH_WRCH(4), + .C_WR_RESPONSE_LATENCY(1), + .C_WRCH_TYPE(0) + ) + inst ( + .RST(rst), + .WR_CLK(wr_clk), + .RD_CLK(rd_clk), + .DIN(din), + .WR_EN(wr_en), + .RD_EN(rd_en), + .DOUT(dout), + .FULL(full), + .EMPTY(empty), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .BACKUP(), + .BACKUP_MARKER(), + .CLK(), + .SRST(), + .WR_RST(), + .RD_RST(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .INT_CLK(), + .INJECTDBITERR(), + .INJECTSBITERR(), + .ALMOST_FULL(), + .WR_ACK(), + .OVERFLOW(), + .ALMOST_EMPTY(), + .VALID(), + .UNDERFLOW(), + .DATA_COUNT(), + .PROG_FULL(), + .PROG_EMPTY(), + .SBITERR(), + .DBITERR(), + .M_ACLK(), + .S_ACLK(), + .S_ARESETN(), + .M_ACLK_EN(), + .S_ACLK_EN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWLOCK(), + .S_AXI_AWCACHE(), + .S_AXI_AWPROT(), + .S_AXI_AWQOS(), + .S_AXI_AWREGION(), + .S_AXI_AWUSER(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WID(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WUSER(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BUSER(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .M_AXI_AWID(), + .M_AXI_AWADDR(), + .M_AXI_AWLEN(), + .M_AXI_AWSIZE(), + .M_AXI_AWBURST(), + .M_AXI_AWLOCK(), + .M_AXI_AWCACHE(), + .M_AXI_AWPROT(), + .M_AXI_AWQOS(), + .M_AXI_AWREGION(), + .M_AXI_AWUSER(), + .M_AXI_AWVALID(), + .M_AXI_AWREADY(), + .M_AXI_WID(), + .M_AXI_WDATA(), + .M_AXI_WSTRB(), + .M_AXI_WLAST(), + .M_AXI_WUSER(), + .M_AXI_WVALID(), + .M_AXI_WREADY(), + .M_AXI_BID(), + .M_AXI_BRESP(), + .M_AXI_BUSER(), + .M_AXI_BVALID(), + .M_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARLOCK(), + .S_AXI_ARCACHE(), + .S_AXI_ARPROT(), + .S_AXI_ARQOS(), + .S_AXI_ARREGION(), + .S_AXI_ARUSER(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RUSER(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .M_AXI_ARID(), + .M_AXI_ARADDR(), + .M_AXI_ARLEN(), + .M_AXI_ARSIZE(), + .M_AXI_ARBURST(), + .M_AXI_ARLOCK(), + .M_AXI_ARCACHE(), + .M_AXI_ARPROT(), + .M_AXI_ARQOS(), + .M_AXI_ARREGION(), + .M_AXI_ARUSER(), + .M_AXI_ARVALID(), + .M_AXI_ARREADY(), + .M_AXI_RID(), + .M_AXI_RDATA(), + .M_AXI_RRESP(), + .M_AXI_RLAST(), + .M_AXI_RUSER(), + .M_AXI_RVALID(), + .M_AXI_RREADY(), + .S_AXIS_TVALID(), + .S_AXIS_TREADY(), + .S_AXIS_TDATA(), + .S_AXIS_TSTRB(), + .S_AXIS_TKEEP(), + .S_AXIS_TLAST(), + .S_AXIS_TID(), + .S_AXIS_TDEST(), + .S_AXIS_TUSER(), + .M_AXIS_TVALID(), + .M_AXIS_TREADY(), + .M_AXIS_TDATA(), + .M_AXIS_TSTRB(), + .M_AXIS_TKEEP(), + .M_AXIS_TLAST(), + .M_AXIS_TID(), + .M_AXIS_TDEST(), + .M_AXIS_TUSER(), + .AXI_AW_INJECTSBITERR(), + .AXI_AW_INJECTDBITERR(), + .AXI_AW_PROG_FULL_THRESH(), + .AXI_AW_PROG_EMPTY_THRESH(), + .AXI_AW_DATA_COUNT(), + .AXI_AW_WR_DATA_COUNT(), + .AXI_AW_RD_DATA_COUNT(), + .AXI_AW_SBITERR(), + .AXI_AW_DBITERR(), + .AXI_AW_OVERFLOW(), + .AXI_AW_UNDERFLOW(), + .AXI_AW_PROG_FULL(), + .AXI_AW_PROG_EMPTY(), + .AXI_W_INJECTSBITERR(), + .AXI_W_INJECTDBITERR(), + .AXI_W_PROG_FULL_THRESH(), + .AXI_W_PROG_EMPTY_THRESH(), + .AXI_W_DATA_COUNT(), + .AXI_W_WR_DATA_COUNT(), + .AXI_W_RD_DATA_COUNT(), + .AXI_W_SBITERR(), + .AXI_W_DBITERR(), + .AXI_W_OVERFLOW(), + .AXI_W_UNDERFLOW(), + .AXI_B_INJECTSBITERR(), + .AXI_W_PROG_FULL(), + .AXI_W_PROG_EMPTY(), + .AXI_B_INJECTDBITERR(), + .AXI_B_PROG_FULL_THRESH(), + .AXI_B_PROG_EMPTY_THRESH(), + .AXI_B_DATA_COUNT(), + .AXI_B_WR_DATA_COUNT(), + .AXI_B_RD_DATA_COUNT(), + .AXI_B_SBITERR(), + .AXI_B_DBITERR(), + .AXI_B_OVERFLOW(), + .AXI_B_UNDERFLOW(), + .AXI_AR_INJECTSBITERR(), + .AXI_B_PROG_FULL(), + .AXI_B_PROG_EMPTY(), + .AXI_AR_INJECTDBITERR(), + .AXI_AR_PROG_FULL_THRESH(), + .AXI_AR_PROG_EMPTY_THRESH(), + .AXI_AR_DATA_COUNT(), + .AXI_AR_WR_DATA_COUNT(), + .AXI_AR_RD_DATA_COUNT(), + .AXI_AR_SBITERR(), + .AXI_AR_DBITERR(), + .AXI_AR_OVERFLOW(), + .AXI_AR_UNDERFLOW(), + .AXI_AR_PROG_FULL(), + .AXI_AR_PROG_EMPTY(), + .AXI_R_INJECTSBITERR(), + .AXI_R_INJECTDBITERR(), + .AXI_R_PROG_FULL_THRESH(), + .AXI_R_PROG_EMPTY_THRESH(), + .AXI_R_DATA_COUNT(), + .AXI_R_WR_DATA_COUNT(), + .AXI_R_RD_DATA_COUNT(), + .AXI_R_SBITERR(), + .AXI_R_DBITERR(), + .AXI_R_OVERFLOW(), + .AXI_R_UNDERFLOW(), + .AXIS_INJECTSBITERR(), + .AXI_R_PROG_FULL(), + .AXI_R_PROG_EMPTY(), + .AXIS_INJECTDBITERR(), + .AXIS_PROG_FULL_THRESH(), + .AXIS_PROG_EMPTY_THRESH(), + .AXIS_DATA_COUNT(), + .AXIS_WR_DATA_COUNT(), + .AXIS_RD_DATA_COUNT(), + .AXIS_SBITERR(), + .AXIS_DBITERR(), + .AXIS_OVERFLOW(), + .AXIS_UNDERFLOW(), + .AXIS_PROG_FULL(), + .AXIS_PROG_EMPTY() + ); + +// synthesis translate_on + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.veo b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.veo new file mode 100644 index 000000000..06d74a77c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.veo @@ -0,0 +1,79 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2013 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ + +/******************************************************************************* +* Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 * +* * +* Rev 1. The FIFO Generator is a parameterizable first-in/first-out * +* memory queue generator. Use it to generate resource and performance * +* optimized FIFOs with common or independent read/write clock domains, * +* and optional fixed or programmable full and empty flags and * +* handshaking signals. Choose from a selection of memory resource * +* types for implementation. Optional Hamming code based error * +* detection and correction as well as error injection capability for * +* system test help to insure data integrity. FIFO width and depth are * +* parameterizable, and for native interface FIFOs, asymmetric read and * +* write port widths are also supported. * +*******************************************************************************/ + +// Interfaces: +// AXI4Stream_MASTER_M_AXIS +// AXI4Stream_SLAVE_S_AXIS +// AXI4_MASTER_M_AXI +// AXI4_SLAVE_S_AXI +// AXI4Lite_MASTER_M_AXI +// AXI4Lite_SLAVE_S_AXI +// master_aclk +// slave_aclk +// slave_aresetn + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_short_2clk your_instance_name ( + .rst(rst), // input rst + .wr_clk(wr_clk), // input wr_clk + .rd_clk(rd_clk), // input rd_clk + .din(din), // input [71 : 0] din + .wr_en(wr_en), // input wr_en + .rd_en(rd_en), // input rd_en + .dout(dout), // output [71 : 0] dout + .full(full), // output full + .empty(empty), // output empty + .rd_data_count(rd_data_count), // output [5 : 0] rd_data_count + .wr_data_count(wr_data_count) // output [5 : 0] wr_data_count +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_short_2clk.v when simulating +// the core, fifo_short_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xco b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xco new file mode 100644 index 000000000..0f256d496 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xco @@ -0,0 +1,213 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Fri Mar 8 18:15:07 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fifo_generator:9.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 +# END Select +# BEGIN Parameters +CSET add_ngc_constraint_axi=false +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET aruser_width=1 +CSET awuser_width=1 +CSET axi_address_width=32 +CSET axi_data_width=64 +CSET axi_type=AXI4_Stream +CSET axis_type=FIFO +CSET buser_width=1 +CSET clock_enable_type=Slave_Interface_Clock_Enable +CSET clock_type_axi=Common_Clock +CSET component_name=fifo_short_2clk +CSET data_count=false +CSET data_count_width=5 +CSET disable_timing_violations=false +CSET disable_timing_violations_axi=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_assert_value_axis=1022 +CSET empty_threshold_assert_value_rach=1022 +CSET empty_threshold_assert_value_rdch=1022 +CSET empty_threshold_assert_value_wach=1022 +CSET empty_threshold_assert_value_wdch=1022 +CSET empty_threshold_assert_value_wrch=1022 +CSET empty_threshold_negate_value=5 +CSET enable_aruser=false +CSET enable_awuser=false +CSET enable_buser=false +CSET enable_common_overflow=false +CSET enable_common_underflow=false +CSET enable_data_counts_axis=false +CSET enable_data_counts_rach=false +CSET enable_data_counts_rdch=false +CSET enable_data_counts_wach=false +CSET enable_data_counts_wdch=false +CSET enable_data_counts_wrch=false +CSET enable_ecc=false +CSET enable_ecc_axis=false +CSET enable_ecc_rach=false +CSET enable_ecc_rdch=false +CSET enable_ecc_wach=false +CSET enable_ecc_wdch=false +CSET enable_ecc_wrch=false +CSET enable_read_channel=false +CSET enable_read_pointer_increment_by2=false +CSET enable_reset_synchronization=true +CSET enable_ruser=false +CSET enable_tdata=false +CSET enable_tdest=false +CSET enable_tid=false +CSET enable_tkeep=false +CSET enable_tlast=false +CSET enable_tready=true +CSET enable_tstrobe=false +CSET enable_tuser=false +CSET enable_write_channel=false +CSET enable_wuser=false +CSET fifo_application_type_axis=Data_FIFO +CSET fifo_application_type_rach=Data_FIFO +CSET fifo_application_type_rdch=Data_FIFO +CSET fifo_application_type_wach=Data_FIFO +CSET fifo_application_type_wdch=Data_FIFO +CSET fifo_application_type_wrch=Data_FIFO +CSET fifo_implementation=Independent_Clocks_Distributed_RAM +CSET fifo_implementation_axis=Common_Clock_Block_RAM +CSET fifo_implementation_rach=Common_Clock_Block_RAM +CSET fifo_implementation_rdch=Common_Clock_Block_RAM +CSET fifo_implementation_wach=Common_Clock_Block_RAM +CSET fifo_implementation_wdch=Common_Clock_Block_RAM +CSET fifo_implementation_wrch=Common_Clock_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=31 +CSET full_threshold_assert_value_axis=1023 +CSET full_threshold_assert_value_rach=1023 +CSET full_threshold_assert_value_rdch=1023 +CSET full_threshold_assert_value_wach=1023 +CSET full_threshold_assert_value_wdch=1023 +CSET full_threshold_assert_value_wrch=1023 +CSET full_threshold_negate_value=30 +CSET id_width=4 +CSET inject_dbit_error=false +CSET inject_dbit_error_axis=false +CSET inject_dbit_error_rach=false +CSET inject_dbit_error_rdch=false +CSET inject_dbit_error_wach=false +CSET inject_dbit_error_wdch=false +CSET inject_dbit_error_wrch=false +CSET inject_sbit_error=false +CSET inject_sbit_error_axis=false +CSET inject_sbit_error_rach=false +CSET inject_sbit_error_rdch=false +CSET inject_sbit_error_wach=false +CSET inject_sbit_error_wdch=false +CSET inject_sbit_error_wrch=false +CSET input_data_width=72 +CSET input_depth=32 +CSET input_depth_axis=1024 +CSET input_depth_rach=16 +CSET input_depth_rdch=1024 +CSET input_depth_wach=16 +CSET input_depth_wdch=1024 +CSET input_depth_wrch=16 +CSET interface_type=Native +CSET output_data_width=72 +CSET output_depth=32 +CSET overflow_flag=false +CSET overflow_flag_axi=false +CSET overflow_sense=Active_High +CSET overflow_sense_axi=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET programmable_full_type_axis=No_Programmable_Full_Threshold +CSET programmable_full_type_rach=No_Programmable_Full_Threshold +CSET programmable_full_type_rdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wach=No_Programmable_Full_Threshold +CSET programmable_full_type_wdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wrch=No_Programmable_Full_Threshold +CSET rach_type=FIFO +CSET rdch_type=FIFO +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=6 +CSET register_slice_mode_axis=Fully_Registered +CSET register_slice_mode_rach=Fully_Registered +CSET register_slice_mode_rdch=Fully_Registered +CSET register_slice_mode_wach=Fully_Registered +CSET register_slice_mode_wdch=Fully_Registered +CSET register_slice_mode_wrch=Fully_Registered +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET ruser_width=1 +CSET synchronization_stages=2 +CSET synchronization_stages_axi=2 +CSET tdata_width=64 +CSET tdest_width=4 +CSET tid_width=8 +CSET tkeep_width=4 +CSET tstrb_width=4 +CSET tuser_width=4 +CSET underflow_flag=false +CSET underflow_flag_axi=false +CSET underflow_sense=Active_High +CSET underflow_sense_axi=Active_High +CSET use_clock_enable=false +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET wach_type=FIFO +CSET wdch_type=FIFO +CSET wrch_type=FIFO +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=6 +CSET wuser_width=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-19T12:39:56Z +# END Extra information +GENERATE +# CRC: 8cc2c19d diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise new file mode 100644 index 000000000..1ca7d35ee --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise @@ -0,0 +1,73 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="fifo_short_2clk.ngc" xil_pn:type="FILE_NGC"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="fifo_short_2clk.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/> + </file> + </files> + + <properties> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> + <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_short_2clk" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_short_2clk.ngc" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_short_2clk" xil_pn:valueState="non-default"/> + <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_short_2clk" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-08T10:16:13" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="164C88B0B983B3E77A86A61EAC6C8697" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt new file mode 100644 index 000000000..7853ebde8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt @@ -0,0 +1,236 @@ +CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1 + + Release Date: December 18, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + + All 7 Series devices + Zynq-7000 devices + +................................................................................ + + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - ISE 14.4 software support + + + 3.2 Vivado + + - 2012.4 software support + - IP level constraint for Built-in FIFO reset synchronizer + +................................................................................ + + +4. RESOLVED ISSUES + + + 4.1 ISE + + - N/A + + + 4.2 Vivado + + - N/A + + +................................................................................ + + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Importing an XCO file alters the XCO configurations + + Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) + into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, + page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. + + CR 467240 + AR 31379 + + 2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed + + Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, + correct behavior of the FIFO status flags cannot be guaranteed after the first write. + + Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. + For more information and additional workaround see Answer Record 41099. + + 5.2 Vivado + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen + ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. + + CR 665836 + +The most recent information, including known issues, workarounds, and +resolutions for this version is provided in the IP Release Notes User Guide +located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + +................................................................................ + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer +10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO +07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO +04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support + AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO +01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support +10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support +06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support +03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support +10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support +09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support +07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support +06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support +12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support +09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support +06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support +04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support +09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes +03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes +10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs +08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO +04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support +09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support +07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support +01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 +08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 +04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 +11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 +05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support +04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release +================================================================================ + +................................................................................ + + +8. LEGAL DISCLAIMER + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html new file mode 100644 index 000000000..fefce62a3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html @@ -0,0 +1,247 @@ +<HTML> +<HEAD> +<TITLE>fifo_generator_v9_3_vinfo</TITLE> +<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1"> +</HEAD> +<BODY> +<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1"> +CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1 + + Release Date: December 18, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A> + +For system requirements: + + <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A> + +This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1 +solution. For the latest core updates, see the product page at: + + <A HREF="http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm">www.xilinx.com/products/ipcenter/FIFO_Generator.htm</A> + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + + All 7 Series devices + Zynq-7000 devices + +................................................................................ + + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - ISE 14.4 software support + + + 3.2 Vivado + + - 2012.4 software support + - IP level constraint for Built-in FIFO reset synchronizer + +................................................................................ + + +4. RESOLVED ISSUES + + + 4.1 ISE + + - N/A + + + 4.2 Vivado + + - N/A + + +................................................................................ + + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Importing an XCO file alters the XCO configurations + + Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) + into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, + page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. + + CR 467240 + AR 31379 + + 2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed + + Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, + correct behavior of the FIFO status flags cannot be guaranteed after the first write. + + Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. + For more information and additional workaround see Answer Record 41099. + + 5.2 Vivado + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen + ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. + + CR 665836 + +The most recent information, including known issues, workarounds, and +resolutions for this version is provided in the IP Release Notes User Guide +located at + + <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A> + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + +To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A> +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + +................................................................................ + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer +10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO +07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO +04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support + AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO +01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support +10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support +06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support +03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support +10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support +09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support +07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support +06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support +12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support +09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support +06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support +04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support +09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes +03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes +10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs +08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO +04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support +09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support +07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support +01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 +08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 +04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 +11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 +05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support +04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release +================================================================================ + +................................................................................ + + +8. LEGAL DISCLAIMER + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. +</FONT> +</PRE> +</BODY> +</HTML> diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/pg057-fifo-generator.pdf b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/pg057-fifo-generator.pdf Binary files differnew file mode 100644 index 000000000..5ec45fbcb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/pg057-fifo-generator.pdf diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf new file mode 100755 index 000000000..62e5058ab --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf @@ -0,0 +1,56 @@ +################################################################################ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. + NET "RD_CLK" TNM_NET = "RD_CLK"; + NET "WR_CLK" TNM_NET = "WR_CLK"; + TIMESPEC "TS_RD_CLK" = PERIOD "RD_CLK" 50 MHZ; + TIMESPEC "TS_WR_CLK" = PERIOD "WR_CLK" 50 MHZ; +################################################################################ diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd new file mode 100755 index 000000000..9e38bcb7c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd @@ -0,0 +1,145 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core - core top file for implementation +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_exdes.vhd +-- +-- Description: +-- This is the FIFO core wrapper with BUFG instances for clock connections. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library unisim; +use unisim.vcomponents.all; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +entity fifo_short_2clk_exdes is + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + +end fifo_short_2clk_exdes; + + + +architecture xilinx of fifo_short_2clk_exdes is + + signal wr_clk_i : std_logic; + signal rd_clk_i : std_logic; + + + + component fifo_short_2clk is + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + + end component; + + +begin + + wr_clk_buf: bufg + PORT map( + i => WR_CLK, + o => wr_clk_i + ); + + rd_clk_buf: bufg + PORT map( + i => RD_CLK, + o => rd_clk_i + ); + + + exdes_inst : fifo_short_2clk + PORT MAP ( + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + WR_DATA_COUNT => wr_data_count, + RD_DATA_COUNT => rd_data_count, + RST => rst, + WR_EN => wr_en, + RD_EN => rd_en, + DIN => din, + DOUT => dout, + FULL => full, + EMPTY => empty); + +end xilinx; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/fifo_generator_v9_3_readme.txt new file mode 100644 index 000000000..7853ebde8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/fifo_generator_v9_3_readme.txt @@ -0,0 +1,236 @@ +CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1 + + Release Date: December 18, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + + All 7 Series devices + Zynq-7000 devices + +................................................................................ + + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - ISE 14.4 software support + + + 3.2 Vivado + + - 2012.4 software support + - IP level constraint for Built-in FIFO reset synchronizer + +................................................................................ + + +4. RESOLVED ISSUES + + + 4.1 ISE + + - N/A + + + 4.2 Vivado + + - N/A + + +................................................................................ + + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Importing an XCO file alters the XCO configurations + + Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) + into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, + page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. + + CR 467240 + AR 31379 + + 2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed + + Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, + correct behavior of the FIFO status flags cannot be guaranteed after the first write. + + Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. + For more information and additional workaround see Answer Record 41099. + + 5.2 Vivado + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen + ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. + + CR 665836 + +The most recent information, including known issues, workarounds, and +resolutions for this version is provided in the IP Release Notes User Guide +located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + +................................................................................ + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer +10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO +07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO +04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support + AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO +01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support +10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support +06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support +03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support +10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support +09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support +07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support +06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support +12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support +09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support +06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support +04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support +09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes +03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes +10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs +08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO +04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support +09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support +07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support +01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 +08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 +04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 +11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 +05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support +04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release +================================================================================ + +................................................................................ + + +8. LEGAL DISCLAIMER + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.bat new file mode 100755 index 000000000..f846d4485 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.bat @@ -0,0 +1,88 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +copy fifo_short_2clk_exdes.ngc .\results\ + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\fifo_short_2clk.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\fifo_short_2clk_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-fgg484-3 -sd ../../../ fifo_short_2clk_exdes + +echo 'Running map' +map fifo_short_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.sh new file mode 100755 index 000000000..e2453c4a1 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.sh @@ -0,0 +1,87 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +cp fifo_short_2clk_exdes.ngc ./results/ + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../fifo_short_2clk.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/fifo_short_2clk_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-fgg484-3 -sd ../../../ fifo_short_2clk_exdes + +echo 'Running map' +map fifo_short_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.bat new file mode 100755 index 000000000..4fe498bff --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.bat @@ -0,0 +1,87 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with Synplify' +synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\fifo_short_2clk.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\fifo_short_2clk_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-fgg484-3 -sd ../../../ fifo_short_2clk_exdes + +echo 'Running map' +map fifo_short_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.sh new file mode 100755 index 000000000..882036474 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.sh @@ -0,0 +1,86 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with Synplify' +synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../fifo_short_2clk.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/fifo_short_2clk_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-fgg484-3 -sd ../../../ fifo_short_2clk_exdes + +echo 'Running map' +map fifo_short_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.bat new file mode 100755 index 000000000..49053fd63 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.bat @@ -0,0 +1,54 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\fifo_short_2clk.ngc . +planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.sh new file mode 100755 index 000000000..42916c2bc --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.sh @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../fifo_short_2clk.ngc . +planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.tcl new file mode 100755 index 000000000..9f39b3e13 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.tcl @@ -0,0 +1,67 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc6slx75fgg484-3 +set projName fifo_short_2clk +set design fifo_short_2clk +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module fifo_short_2clk_exdes +add_files -norecurse {../../example_design/fifo_short_2clk_exdes.vhd} +add_files -norecurse {./fifo_short_2clk.ngc} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/fifo_short_2clk_exdes.xdc} +set_property top fifo_short_2clk_exdes [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module fifo_short_2clk_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module fifo_short_2clk_exdes routed.v +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.prj b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.prj new file mode 100755 index 000000000..f16af4308 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.prj @@ -0,0 +1 @@ +work ../example_design/fifo_short_2clk_exdes.vhd diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.scr b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.scr new file mode 100755 index 000000000..b5a9091c7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.scr @@ -0,0 +1,13 @@ +run +-ifmt VHDL +-ent fifo_short_2clk_exdes +-p xc6slx75-fgg484-3 +-ifn xst.prj +-write_timing_constraints No +-iobuf YES +-max_fanout 100 +-ofn fifo_short_2clk_exdes +-ofmt NGC +-bus_delimiter () +-hierarchy_separator / +-case Maintain diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd new file mode 100755 index 000000000..bc7a1b525 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd @@ -0,0 +1,123 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_dgen.vhd +-- +-- Description: +-- Used for write interface stimulus generation +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +ENTITY fifo_short_2clk_dgen IS + GENERIC ( + C_DIN_WIDTH : INTEGER := 32; + C_DOUT_WIDTH : INTEGER := 32; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT ( + RESET : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + PRC_WR_EN : IN STD_LOGIC; + FULL : IN STD_LOGIC; + WR_EN : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE fg_dg_arch OF fifo_short_2clk_dgen IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); + + SIGNAL pr_w_en : STD_LOGIC := '0'; + SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); + SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + BEGIN + + WR_EN <= PRC_WR_EN ; + WR_DATA <= wr_data_i AFTER 100 ns; + + ---------------------------------------------- + -- Generation of DATA + ---------------------------------------------- + gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + rd_gen_inst1:fifo_short_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+N + ) + PORT MAP( + CLK => WR_CLK, + RESET => RESET, + RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), + ENABLE => pr_w_en + ); + END GENERATE; + + pr_w_en <= PRC_WR_EN AND NOT FULL; + wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0); + + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd new file mode 100755 index 000000000..b0465d84f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd @@ -0,0 +1,150 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_dverif.vhd +-- +-- Description: +-- Used for FIFO read interface stimulus generation and data checking +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +ENTITY fifo_short_2clk_dverif IS + GENERIC( + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_USE_EMBEDDED_REG : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + PRC_RD_EN : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + RD_EN : OUT STD_LOGIC; + DOUT_CHK : OUT STD_LOGIC + ); +END ENTITY; + + +ARCHITECTURE fg_dv_arch OF fifo_short_2clk_dverif IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8); + + SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_chk : STD_LOGIC := '1'; + SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0); + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL pr_r_en : STD_LOGIC := '0'; + SIGNAL rd_en_d1 : STD_LOGIC := '1'; +BEGIN + + + DOUT_CHK <= data_chk; + RD_EN <= rd_en_i; + rd_en_i <= PRC_RD_EN; + rd_en_d1 <= '1'; + + + data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE + ------------------------------------------------------- + -- Expected data generation and checking for data_fifo + ------------------------------------------------------- + + pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1; + expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0); + + gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + rd_gen_inst2:fifo_short_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+N + ) + PORT MAP( + CLK => RD_CLK, + RESET => RESET, + RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), + ENABLE => pr_r_en + ); + END GENERATE; + + PROCESS (RD_CLK,RESET) + BEGIN + IF(RESET = '1') THEN + data_chk <= '0'; + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + IF(EMPTY = '0') THEN + IF(DATA_OUT = expected_dout) THEN + data_chk <= '0'; + ELSE + data_chk <= '1'; + END IF; + END IF; + END IF; + END PROCESS; + END GENERATE data_fifo_chk; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd new file mode 100755 index 000000000..5d6506398 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd @@ -0,0 +1,541 @@ + +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_pctrl.vhd +-- +-- Description: +-- Used for protocol control on write and read interface stimulus and status generation +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +ENTITY fifo_short_2clk_pctrl IS + GENERIC( + AXI_CHANNEL : STRING :="NONE"; + C_APPLICATION_TYPE : INTEGER := 0; + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_WR_PNTR_WIDTH : INTEGER := 0; + C_RD_PNTR_WIDTH : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 2; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET_WR : IN STD_LOGIC; + RESET_RD : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + FULL : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + ALMOST_FULL : IN STD_LOGIC; + ALMOST_EMPTY : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + DOUT_CHK : IN STD_LOGIC; + PRC_WR_EN : OUT STD_LOGIC; + PRC_RD_EN : OUT STD_LOGIC; + RESET_EN : OUT STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE fg_pc_arch OF fifo_short_2clk_pctrl IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); + CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH); + + SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); + SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); + SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); + SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); + SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_en_i : STD_LOGIC := '0'; + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL state : STD_LOGIC := '0'; + SIGNAL wr_control : STD_LOGIC := '0'; + SIGNAL rd_control : STD_LOGIC := '0'; + SIGNAL stop_on_err : STD_LOGIC := '0'; + SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8); + SIGNAL sim_done_i : STD_LOGIC := '0'; + SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); + SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); + SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0'); + SIGNAL prc_we_i : STD_LOGIC := '0'; + SIGNAL prc_re_i : STD_LOGIC := '0'; + SIGNAL reset_en_i : STD_LOGIC := '0'; + SIGNAL sim_done_d1 : STD_LOGIC := '0'; + SIGNAL sim_done_wr1 : STD_LOGIC := '0'; + SIGNAL sim_done_wr2 : STD_LOGIC := '0'; + SIGNAL empty_d1 : STD_LOGIC := '0'; + SIGNAL empty_wr_dom1 : STD_LOGIC := '0'; + SIGNAL state_d1 : STD_LOGIC := '0'; + SIGNAL state_rd_dom1 : STD_LOGIC := '0'; + SIGNAL rd_en_d1 : STD_LOGIC := '0'; + SIGNAL rd_en_wr1 : STD_LOGIC := '0'; + SIGNAL wr_en_d1 : STD_LOGIC := '0'; + SIGNAL wr_en_rd1 : STD_LOGIC := '0'; + SIGNAL full_chk_d1 : STD_LOGIC := '0'; + SIGNAL full_chk_rd1 : STD_LOGIC := '0'; + SIGNAL empty_wr_dom2 : STD_LOGIC := '0'; + + SIGNAL state_rd_dom2 : STD_LOGIC := '0'; + SIGNAL state_rd_dom3 : STD_LOGIC := '0'; + SIGNAL rd_en_wr2 : STD_LOGIC := '0'; + SIGNAL wr_en_rd2 : STD_LOGIC := '0'; + SIGNAL full_chk_rd2 : STD_LOGIC := '0'; + SIGNAL reset_en_d1 : STD_LOGIC := '0'; + SIGNAL reset_en_rd1 : STD_LOGIC := '0'; + SIGNAL reset_en_rd2 : STD_LOGIC := '0'; + + SIGNAL data_chk_wr_d1 : STD_LOGIC := '0'; + SIGNAL data_chk_rd1 : STD_LOGIC := '0'; + SIGNAL data_chk_rd2 : STD_LOGIC := '0'; + SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); + SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); +BEGIN + status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0'; + STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high); + + prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0'; + prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0'; + + SIM_DONE <= sim_done_i; + rdw_gt_wrw <= (OTHERS => '1'); + wrw_gt_rdw <= (OTHERS => '1'); + + PROCESS(RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(prc_re_i = '1') THEN + rd_activ_cont <= rd_activ_cont + "1"; + END IF; + END IF; + END PROCESS; + + + PROCESS(sim_done_i) + BEGIN + assert sim_done_i = '0' + report "Simulation Complete for:" & AXI_CHANNEL + severity note; + END PROCESS; + +----------------------------------------------------- +-- SIM_DONE SIGNAL GENERATION +----------------------------------------------------- +PROCESS (RD_CLK,RESET_RD) +BEGIN + IF(RESET_RD = '1') THEN + --sim_done_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN + sim_done_i <= '1'; + END IF; + END IF; +END PROCESS; + + -- TB Timeout/Stop + fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE + PROCESS (RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN + sim_stop_cntr <= sim_stop_cntr - "1"; + END IF; + END IF; + END PROCESS; + END GENERATE fifo_tb_stop_run; + + + -- Stop when error found + PROCESS (RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(sim_done_i = '0') THEN + status_d1_i <= status_i OR status_d1_i; + END IF; + IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN + stop_on_err <= '1'; + END IF; + END IF; + END PROCESS; + ----------------------------------------------------- + + ----------------------------------------------------- + -- CHECKS FOR FIFO + ----------------------------------------------------- + + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + post_rst_dly_rd <= (OTHERS => '1'); + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4); + END IF; + END PROCESS; + + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + post_rst_dly_wr <= (OTHERS => '1'); + ELSIF (WR_CLK'event AND WR_CLK='1') THEN + post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4); + END IF; + END PROCESS; + + + -- FULL de-assert Counter + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + full_ds_timeout <= (OTHERS => '0'); + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN + full_ds_timeout <= full_ds_timeout + '1'; + END IF; + ELSE + full_ds_timeout <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS; + + + -- EMPTY deassert counter + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_ds_timeout <= (OTHERS => '0'); + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state = '0') THEN + IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN + empty_ds_timeout <= empty_ds_timeout + '1'; + END IF; + ELSE + empty_ds_timeout <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS; + + -- Full check signal generation + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + full_chk_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN + full_chk_i <= '0'; + ELSE + full_chk_i <= AND_REDUCE(full_as_timeout) OR + AND_REDUCE(full_ds_timeout); + END IF; + END IF; + END PROCESS; + + -- Empty checks + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_chk_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN + empty_chk_i <= '0'; + ELSE + empty_chk_i <= AND_REDUCE(empty_as_timeout) OR + AND_REDUCE(empty_ds_timeout); + END IF; + END IF; + END PROCESS; + + fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE + PRC_WR_EN <= prc_we_i AFTER 100 ns; + PRC_RD_EN <= prc_re_i AFTER 50 ns; + data_chk_i <= dout_chk; + END GENERATE fifo_d_chk; + ----------------------------------------------------- + + + ----------------------------------------------------- + -- SYNCHRONIZERS B/W WRITE AND READ DOMAINS + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + empty_wr_dom1 <= '1'; + empty_wr_dom2 <= '1'; + state_d1 <= '0'; + wr_en_d1 <= '0'; + rd_en_wr1 <= '0'; + rd_en_wr2 <= '0'; + full_chk_d1 <= '0'; + reset_en_d1 <= '0'; + sim_done_wr1 <= '0'; + sim_done_wr2 <= '0'; + ELSIF (WR_CLK'event AND WR_CLK='1') THEN + sim_done_wr1 <= sim_done_d1; + sim_done_wr2 <= sim_done_wr1; + reset_en_d1 <= reset_en_i; + state_d1 <= state; + empty_wr_dom1 <= empty_d1; + empty_wr_dom2 <= empty_wr_dom1; + wr_en_d1 <= wr_en_i; + rd_en_wr1 <= rd_en_d1; + rd_en_wr2 <= rd_en_wr1; + full_chk_d1 <= full_chk_i; + END IF; + END PROCESS; + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_d1 <= '1'; + state_rd_dom1 <= '0'; + state_rd_dom2 <= '0'; + state_rd_dom3 <= '0'; + wr_en_rd1 <= '0'; + wr_en_rd2 <= '0'; + rd_en_d1 <= '0'; + full_chk_rd1 <= '0'; + full_chk_rd2 <= '0'; + reset_en_rd1 <= '0'; + reset_en_rd2 <= '0'; + sim_done_d1 <= '0'; + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + sim_done_d1 <= sim_done_i; + reset_en_rd1 <= reset_en_d1; + reset_en_rd2 <= reset_en_rd1; + empty_d1 <= EMPTY; + rd_en_d1 <= rd_en_i; + state_rd_dom1 <= state_d1; + state_rd_dom2 <= state_rd_dom1; + state_rd_dom3 <= state_rd_dom2; + wr_en_rd1 <= wr_en_d1; + wr_en_rd2 <= wr_en_rd1; + full_chk_rd1 <= full_chk_d1; + full_chk_rd2 <= full_chk_rd1; + END IF; + END PROCESS; + + RESET_EN <= reset_en_rd2; + + + data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE + ----------------------------------------------------- + -- WR_EN GENERATION + ----------------------------------------------------- + gen_rand_wr_en:fifo_short_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+1 + ) + PORT MAP( + CLK => WR_CLK, + RESET => RESET_WR, + RANDOM_NUM => wr_en_gen, + ENABLE => '1' + ); + + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + wr_en_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control; + ELSE + wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4)); + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------- + -- WR_EN CONTROL + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + wr_cntr <= (OTHERS => '0'); + wr_control <= '1'; + full_as_timeout <= (OTHERS => '0'); + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + IF(wr_en_i = '1') THEN + wr_cntr <= wr_cntr + "1"; + END IF; + full_as_timeout <= (OTHERS => '0'); + ELSE + wr_cntr <= (OTHERS => '0'); + IF(rd_en_wr2 = '0') THEN + IF(wr_en_i = '1') THEN + full_as_timeout <= full_as_timeout + "1"; + END IF; + ELSE + full_as_timeout <= (OTHERS => '0'); + END IF; + END IF; + + wr_control <= NOT wr_cntr(wr_cntr'high); + + END IF; + END PROCESS; + + ----------------------------------------------------- + -- RD_EN GENERATION + ----------------------------------------------------- + gen_rand_rd_en:fifo_short_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED + ) + PORT MAP( + CLK => RD_CLK, + RESET => RESET_RD, + RANDOM_NUM => rd_en_gen, + ENABLE => '1' + ); + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + rd_en_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0') THEN + rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4)); + ELSE + rd_en_i <= rd_en_gen(0) OR rd_en_gen(6); + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------- + -- RD_EN CONTROL + ----------------------------------------------------- + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + rd_cntr <= (OTHERS => '0'); + rd_control <= '1'; + empty_as_timeout <= (OTHERS => '0'); + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0') THEN + IF(rd_en_i = '1') THEN + rd_cntr <= rd_cntr + "1"; + END IF; + empty_as_timeout <= (OTHERS => '0'); + ELSE + rd_cntr <= (OTHERS => '0'); + IF(wr_en_rd2 = '0') THEN + IF(rd_en_i = '1') THEN + empty_as_timeout <= empty_as_timeout + "1"; + END IF; + ELSE + empty_as_timeout <= (OTHERS => '0'); + END IF; + END IF; + + rd_control <= NOT rd_cntr(rd_cntr'high); + + END IF; + END PROCESS; + + ----------------------------------------------------- + -- STIMULUS CONTROL + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + state <= '0'; + reset_en_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + CASE state IS + WHEN '0' => + IF(FULL = '1' AND empty_wr_dom2 = '0') THEN + state <= '1'; + reset_en_i <= '0'; + END IF; + WHEN '1' => + IF(empty_wr_dom2 = '1' AND FULL = '0') THEN + state <= '0'; + reset_en_i <= '1'; + END IF; + WHEN OTHERS => state <= state; + END CASE; + END IF; + END PROCESS; + END GENERATE data_fifo_en; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd new file mode 100755 index 000000000..4c0e4035b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd @@ -0,0 +1,350 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_pkg.vhd +-- +-- Description: +-- This is the demo testbench package file for FIFO Generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.std_logic_arith.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +PACKAGE fifo_short_2clk_pkg IS + + FUNCTION divroundup ( + data_value : INTEGER; + divisor : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : INTEGER; + false_case : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : STD_LOGIC; + false_case : STD_LOGIC) + RETURN STD_LOGIC; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : TIME; + false_case : TIME) + RETURN TIME; + ------------------------ + FUNCTION log2roundup ( + data_value : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION hexstr_to_std_logic_vec( + arg1 : string; + size : integer ) + RETURN std_logic_vector; + ------------------------ + COMPONENT fifo_short_2clk_rng IS + GENERIC (WIDTH : integer := 8; + SEED : integer := 3); + PORT ( + CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + ENABLE : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_short_2clk_dgen IS + GENERIC ( + C_DIN_WIDTH : INTEGER := 32; + C_DOUT_WIDTH : INTEGER := 32; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT ( + RESET : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + PRC_WR_EN : IN STD_LOGIC; + FULL : IN STD_LOGIC; + WR_EN : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_short_2clk_dverif IS + GENERIC( + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_USE_EMBEDDED_REG : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + PRC_RD_EN : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + RD_EN : OUT STD_LOGIC; + DOUT_CHK : OUT STD_LOGIC + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_short_2clk_pctrl IS + GENERIC( + AXI_CHANNEL : STRING := "NONE"; + C_APPLICATION_TYPE : INTEGER := 0; + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_WR_PNTR_WIDTH : INTEGER := 0; + C_RD_PNTR_WIDTH : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 2; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET_WR : IN STD_LOGIC; + RESET_RD : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + FULL : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + ALMOST_FULL : IN STD_LOGIC; + ALMOST_EMPTY : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + DOUT_CHK : IN STD_LOGIC; + PRC_WR_EN : OUT STD_LOGIC; + PRC_RD_EN : OUT STD_LOGIC; + RESET_EN : OUT STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + COMPONENT fifo_short_2clk_synth IS + GENERIC( + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 0; + TB_SEED : INTEGER := 1 + ); + PORT( + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + COMPONENT fifo_short_2clk_exdes IS + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + + END COMPONENT; + ------------------------ + + +END fifo_short_2clk_pkg; + + + +PACKAGE BODY fifo_short_2clk_pkg IS + + FUNCTION divroundup ( + data_value : INTEGER; + divisor : INTEGER) + RETURN INTEGER IS + VARIABLE div : INTEGER; + BEGIN + div := data_value/divisor; + IF ( (data_value MOD divisor) /= 0) THEN + div := div+1; + END IF; + RETURN div; + END divroundup; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : INTEGER; + false_case : INTEGER) + RETURN INTEGER IS + VARIABLE retval : INTEGER := 0; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : STD_LOGIC; + false_case : STD_LOGIC) + RETURN STD_LOGIC IS + VARIABLE retval : STD_LOGIC := '0'; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : TIME; + false_case : TIME) + RETURN TIME IS + VARIABLE retval : TIME := 0 ps; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + ------------------------------- + FUNCTION log2roundup ( + data_value : INTEGER) + RETURN INTEGER IS + + VARIABLE width : INTEGER := 0; + VARIABLE cnt : INTEGER := 1; + BEGIN + IF (data_value <= 1) THEN + width := 1; + ELSE + WHILE (cnt < data_value) LOOP + width := width + 1; + cnt := cnt *2; + END LOOP; + END IF; + + RETURN width; + END log2roundup; + ------------------------------------------------------------------------------ + -- hexstr_to_std_logic_vec + -- This function converts a hex string to a std_logic_vector + ------------------------------------------------------------------------------ + FUNCTION hexstr_to_std_logic_vec( + arg1 : string; + size : integer ) + RETURN std_logic_vector IS + VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE bin : std_logic_vector(3 DOWNTO 0); + VARIABLE index : integer := 0; + BEGIN + FOR i IN arg1'reverse_range LOOP + CASE arg1(i) IS + WHEN '0' => bin := (OTHERS => '0'); + WHEN '1' => bin := (0 => '1', OTHERS => '0'); + WHEN '2' => bin := (1 => '1', OTHERS => '0'); + WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); + WHEN '4' => bin := (2 => '1', OTHERS => '0'); + WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); + WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); + WHEN '7' => bin := (3 => '0', OTHERS => '1'); + WHEN '8' => bin := (3 => '1', OTHERS => '0'); + WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); + WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); + WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); + WHEN 'B' => bin := (2 => '0', OTHERS => '1'); + WHEN 'b' => bin := (2 => '0', OTHERS => '1'); + WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); + WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); + WHEN 'D' => bin := (1 => '0', OTHERS => '1'); + WHEN 'd' => bin := (1 => '0', OTHERS => '1'); + WHEN 'E' => bin := (0 => '0', OTHERS => '1'); + WHEN 'e' => bin := (0 => '0', OTHERS => '1'); + WHEN 'F' => bin := (OTHERS => '1'); + WHEN 'f' => bin := (OTHERS => '1'); + WHEN OTHERS => + FOR j IN 0 TO 3 LOOP + bin(j) := 'X'; + END LOOP; + END CASE; + FOR j IN 0 TO 3 LOOP + IF (index*4)+j < size THEN + result((index*4)+j) := bin(j); + END IF; + END LOOP; + index := index + 1; + END LOOP; + RETURN result; + END hexstr_to_std_logic_vec; + +END fifo_short_2clk_pkg; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd new file mode 100755 index 000000000..80c201c3b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd @@ -0,0 +1,100 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_rng.vhd +-- +-- Description: +-- Used for generation of pseudo random numbers +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +ENTITY fifo_short_2clk_rng IS + GENERIC ( + WIDTH : integer := 8; + SEED : integer := 3); + PORT ( + CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + ENABLE : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)); +END ENTITY; + +ARCHITECTURE rg_arch OF fifo_short_2clk_rng IS +BEGIN +PROCESS (CLK,RESET) + VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width); + VARIABLE temp : STD_LOGIC := '0'; +BEGIN + IF(RESET = '1') THEN + rand_temp := conv_std_logic_vector(SEED,width); + temp := '0'; + ELSIF (CLK'event AND CLK = '1') THEN + IF (ENABLE = '1') THEN + temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5); + rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0); + rand_temp(0) := temp; + END IF; + END IF; + + RANDOM_NUM <= rand_temp; + +END PROCESS; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd new file mode 100755 index 000000000..e9139fc96 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd @@ -0,0 +1,300 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_synth.vhd +-- +-- Description: +-- This is the demo testbench for fifo_generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + +LIBRARY ieee; +USE ieee.STD_LOGIC_1164.ALL; +USE ieee.STD_LOGIC_unsigned.ALL; +USE IEEE.STD_LOGIC_arith.ALL; +USE ieee.numeric_std.ALL; +USE ieee.STD_LOGIC_misc.ALL; + +LIBRARY std; +USE std.textio.ALL; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY fifo_short_2clk_synth IS + GENERIC( + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 0; + TB_SEED : INTEGER := 1 + ); + PORT( + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END ENTITY; + +ARCHITECTURE simulation_arch OF fifo_short_2clk_synth IS + + -- FIFO interface signal declarations + SIGNAL wr_clk_i : STD_LOGIC; + SIGNAL rd_clk_i : STD_LOGIC; + SIGNAL wr_data_count : STD_LOGIC_VECTOR(6-1 DOWNTO 0); + SIGNAL rd_data_count : STD_LOGIC_VECTOR(6-1 DOWNTO 0); + SIGNAL rst : STD_LOGIC; + SIGNAL wr_en : STD_LOGIC; + SIGNAL rd_en : STD_LOGIC; + SIGNAL din : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL dout : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL full : STD_LOGIC; + SIGNAL empty : STD_LOGIC; + -- TB Signals + SIGNAL wr_data : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL dout_i : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL wr_en_i : STD_LOGIC := '0'; + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL full_i : STD_LOGIC := '0'; + SIGNAL empty_i : STD_LOGIC := '0'; + SIGNAL almost_full_i : STD_LOGIC := '0'; + SIGNAL almost_empty_i : STD_LOGIC := '0'; + SIGNAL prc_we_i : STD_LOGIC := '0'; + SIGNAL prc_re_i : STD_LOGIC := '0'; + SIGNAL dout_chk_i : STD_LOGIC := '0'; + SIGNAL rst_int_rd : STD_LOGIC := '0'; + SIGNAL rst_int_wr : STD_LOGIC := '0'; + SIGNAL rst_s_wr1 : STD_LOGIC := '0'; + SIGNAL rst_s_wr2 : STD_LOGIC := '0'; + SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL rst_s_wr3 : STD_LOGIC := '0'; + SIGNAL rst_s_rd : STD_LOGIC := '0'; + SIGNAL reset_en : STD_LOGIC := '0'; + SIGNAL rst_async_wr1 : STD_LOGIC := '0'; + SIGNAL rst_async_wr2 : STD_LOGIC := '0'; + SIGNAL rst_async_wr3 : STD_LOGIC := '0'; + SIGNAL rst_async_rd1 : STD_LOGIC := '0'; + SIGNAL rst_async_rd2 : STD_LOGIC := '0'; + SIGNAL rst_async_rd3 : STD_LOGIC := '0'; + + + BEGIN + + ---- Reset generation logic ----- + rst_int_wr <= rst_async_wr3 OR rst_s_wr3; + rst_int_rd <= rst_async_rd3 OR rst_s_rd; + + --Testbench reset synchronization + PROCESS(rd_clk_i,RESET) + BEGIN + IF(RESET = '1') THEN + rst_async_rd1 <= '1'; + rst_async_rd2 <= '1'; + rst_async_rd3 <= '1'; + ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN + rst_async_rd1 <= RESET; + rst_async_rd2 <= rst_async_rd1; + rst_async_rd3 <= rst_async_rd2; + END IF; + END PROCESS; + + PROCESS(wr_clk_i,RESET) + BEGIN + IF(RESET = '1') THEN + rst_async_wr1 <= '1'; + rst_async_wr2 <= '1'; + rst_async_wr3 <= '1'; + ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN + rst_async_wr1 <= RESET; + rst_async_wr2 <= rst_async_wr1; + rst_async_wr3 <= rst_async_wr2; + END IF; + END PROCESS; + + --Soft reset for core and testbench + PROCESS(rd_clk_i) + BEGIN + IF(rd_clk_i'event AND rd_clk_i='1') THEN + rst_gen_rd <= rst_gen_rd + "1"; + IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN + rst_s_rd <= '1'; + assert false + report "Reset applied..Memory Collision checks are not valid" + severity note; + ELSE + IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN + rst_s_rd <= '0'; + END IF; + END IF; + END IF; + END PROCESS; + + PROCESS(wr_clk_i) + BEGIN + IF(wr_clk_i'event AND wr_clk_i='1') THEN + rst_s_wr1 <= rst_s_rd; + rst_s_wr2 <= rst_s_wr1; + rst_s_wr3 <= rst_s_wr2; + IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN + assert false + report "Reset removed..Memory Collision checks are valid" + severity note; + END IF; + END IF; + END PROCESS; + ------------------ + + ---- Clock buffers for testbench ---- + wr_clk_i <= WR_CLK; + rd_clk_i <= RD_CLK; + ------------------ + + rst <= RESET OR rst_s_rd AFTER 12 ns; + din <= wr_data; + dout_i <= dout; + wr_en <= wr_en_i; + rd_en <= rd_en_i; + full_i <= full; + empty_i <= empty; + + fg_dg_nv: fifo_short_2clk_dgen + GENERIC MAP ( + C_DIN_WIDTH => 72, + C_DOUT_WIDTH => 72, + TB_SEED => TB_SEED, + C_CH_TYPE => 0 + ) + PORT MAP ( -- Write Port + RESET => rst_int_wr, + WR_CLK => wr_clk_i, + PRC_WR_EN => prc_we_i, + FULL => full_i, + WR_EN => wr_en_i, + WR_DATA => wr_data + ); + + fg_dv_nv: fifo_short_2clk_dverif + GENERIC MAP ( + C_DOUT_WIDTH => 72, + C_DIN_WIDTH => 72, + C_USE_EMBEDDED_REG => 0, + TB_SEED => TB_SEED, + C_CH_TYPE => 0 + ) + PORT MAP( + RESET => rst_int_rd, + RD_CLK => rd_clk_i, + PRC_RD_EN => prc_re_i, + RD_EN => rd_en_i, + EMPTY => empty_i, + DATA_OUT => dout_i, + DOUT_CHK => dout_chk_i + ); + + fg_pc_nv: fifo_short_2clk_pctrl + GENERIC MAP ( + AXI_CHANNEL => "Native", + C_APPLICATION_TYPE => 0, + C_DOUT_WIDTH => 72, + C_DIN_WIDTH => 72, + C_WR_PNTR_WIDTH => 5, + C_RD_PNTR_WIDTH => 5, + C_CH_TYPE => 0, + FREEZEON_ERROR => FREEZEON_ERROR, + TB_SEED => TB_SEED, + TB_STOP_CNT => TB_STOP_CNT + ) + PORT MAP( + RESET_WR => rst_int_wr, + RESET_RD => rst_int_rd, + RESET_EN => reset_en, + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + PRC_WR_EN => prc_we_i, + PRC_RD_EN => prc_re_i, + FULL => full_i, + ALMOST_FULL => almost_full_i, + ALMOST_EMPTY => almost_empty_i, + DOUT_CHK => dout_chk_i, + EMPTY => empty_i, + DATA_IN => wr_data, + DATA_OUT => dout, + SIM_DONE => SIM_DONE, + STATUS => STATUS + ); + + + + + + fifo_short_2clk_inst : fifo_short_2clk_exdes + PORT MAP ( + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + WR_DATA_COUNT => wr_data_count, + RD_DATA_COUNT => rd_data_count, + RST => rst, + WR_EN => wr_en, + RD_EN => rd_en, + DIN => din, + DOUT => dout, + FULL => full, + EMPTY => empty); + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd new file mode 100755 index 000000000..6d86157db --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd @@ -0,0 +1,208 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_tb.vhd +-- +-- Description: +-- This is the demo testbench top file for fifo_generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +LIBRARY std; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +USE IEEE.std_logic_arith.ALL; +USE IEEE.std_logic_misc.ALL; +USE ieee.numeric_std.ALL; +USE ieee.std_logic_textio.ALL; +USE std.textio.ALL; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +ENTITY fifo_short_2clk_tb IS +END ENTITY; + + +ARCHITECTURE fifo_short_2clk_arch OF fifo_short_2clk_tb IS + SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + SIGNAL wr_clk : STD_LOGIC; + SIGNAL rd_clk : STD_LOGIC; + SIGNAL reset : STD_LOGIC; + SIGNAL sim_done : STD_LOGIC := '0'; + SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); + -- Write and Read clock periods + CONSTANT wr_clk_period_by_2 : TIME := 200 ns; + CONSTANT rd_clk_period_by_2 : TIME := 100 ns; + -- Procedures to display strings + PROCEDURE disp_str(CONSTANT str:IN STRING) IS + variable dp_l : line := null; + BEGIN + write(dp_l,str); + writeline(output,dp_l); + END PROCEDURE; + + PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS + variable dp_lx : line := null; + BEGIN + hwrite(dp_lx,hex); + writeline(output,dp_lx); + END PROCEDURE; + +BEGIN + + -- Generation of clock + + PROCESS BEGIN + WAIT FOR 400 ns; -- Wait for global reset + WHILE 1 = 1 LOOP + wr_clk <= '0'; + WAIT FOR wr_clk_period_by_2; + wr_clk <= '1'; + WAIT FOR wr_clk_period_by_2; + END LOOP; + END PROCESS; + + PROCESS BEGIN + WAIT FOR 200 ns;-- Wait for global reset + WHILE 1 = 1 LOOP + rd_clk <= '0'; + WAIT FOR rd_clk_period_by_2; + rd_clk <= '1'; + WAIT FOR rd_clk_period_by_2; + END LOOP; + END PROCESS; + + -- Generation of Reset + + PROCESS BEGIN + reset <= '1'; + WAIT FOR 4200 ns; + reset <= '0'; + WAIT; + END PROCESS; + + + -- Error message printing based on STATUS signal from fifo_short_2clk_synth + + PROCESS(status) + BEGIN + IF(status /= "0" AND status /= "1") THEN + disp_str("STATUS:"); + disp_hex(status); + END IF; + + IF(status(7) = '1') THEN + assert false + report "Data mismatch found" + severity error; + END IF; + + IF(status(1) = '1') THEN + END IF; + + IF(status(5) = '1') THEN + assert false + report "Empty flag Mismatch/timeout" + severity error; + END IF; + + IF(status(6) = '1') THEN + assert false + report "Full Flag Mismatch/timeout" + severity error; + END IF; + END PROCESS; + + + PROCESS + BEGIN + wait until sim_done = '1'; + IF(status /= "0" AND status /= "1") THEN + assert false + report "Simulation failed" + severity failure; + ELSE + assert false + report "Test Completed Successfully" + severity failure; + END IF; + END PROCESS; + + PROCESS + BEGIN + wait for 400 ms; + assert false + report "Test bench timed out" + severity failure; + END PROCESS; + + -- Instance of fifo_short_2clk_synth + + fifo_short_2clk_synth_inst:fifo_short_2clk_synth + GENERIC MAP( + FREEZEON_ERROR => 0, + TB_STOP_CNT => 2, + TB_SEED => 108 + ) + PORT MAP( + WR_CLK => wr_clk, + RD_CLK => rd_clk, + RESET => reset, + SIM_DONE => sim_done, + STATUS => status + ); + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.bat new file mode 100755 index 000000000..d40cb85cf --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.bat @@ -0,0 +1,63 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ..\\..\\..\\fifo_short_2clk.v +vhpcomp -work work ..\\..\\example_design\\fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhpcomp -work work ..\\fifo_short_2clk_pkg.vhd +vhpcomp -work work ..\\fifo_short_2clk_rng.vhd +vhpcomp -work work ..\\fifo_short_2clk_dgen.vhd +vhpcomp -work work ..\\fifo_short_2clk_dverif.vhd +vhpcomp -work work ..\\fifo_short_2clk_pctrl.vhd +vhpcomp -work work ..\\fifo_short_2clk_synth.vhd +vhpcomp -work work ..\\fifo_short_2clk_tb.vhd + +vlogcomp -work work $XILINX\\verilog\\src\\glbl.v +fuse work.fifo_short_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_short_2clk_tb.exe + +.\\fifo_short_2clk_tb.exe -gui -tclbatch .\\wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.sh new file mode 100755 index 000000000..78f9ce588 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.sh @@ -0,0 +1,65 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ../../../fifo_short_2clk.v +vhpcomp -work work ../../example_design/fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhpcomp -work work ../fifo_short_2clk_pkg.vhd +vhpcomp -work work ../fifo_short_2clk_rng.vhd +vhpcomp -work work ../fifo_short_2clk_dgen.vhd +vhpcomp -work work ../fifo_short_2clk_dverif.vhd +vhpcomp -work work ../fifo_short_2clk_pctrl.vhd +vhpcomp -work work ../fifo_short_2clk_synth.vhd +vhpcomp -work work ../fifo_short_2clk_tb.vhd + +vlogcomp -work work $XILINX/verilog/src/glbl.v +fuse work.fifo_short_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_short_2clk_tb.exe + +./fifo_short_2clk_tb.exe -gui -tclbatch ./wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.bat new file mode 100755 index 000000000..35375ce20 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.bat @@ -0,0 +1,47 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.do b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.do new file mode 100755 index 000000000..8deb52187 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.do @@ -0,0 +1,74 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../../fifo_short_2clk.v +vcom -work work ../../example_design/fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vcom -work work ../fifo_short_2clk_pkg.vhd +vcom -work work ../fifo_short_2clk_rng.vhd +vcom -work work ../fifo_short_2clk_dgen.vhd +vcom -work work ../fifo_short_2clk_dverif.vhd +vcom -work work ../fifo_short_2clk_pctrl.vhd +vcom -work work ../fifo_short_2clk_synth.vhd +vcom -work work ../fifo_short_2clk_tb.vhd + +vlog -work work $env(XILINX)/verilog/src/glbl.v +vsim -t ps -voptargs="+acc" -L XilinxCoreLib_ver -L unisims_ver glbl work.fifo_short_2clk_tb + +add log -r /* +do wave_mti.do +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.sh new file mode 100755 index 000000000..edb1b0dd9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.sh @@ -0,0 +1,49 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_ncsim.sh new file mode 100755 index 000000000..749f9db06 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_ncsim.sh @@ -0,0 +1,69 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +mkdir work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +ncvlog -work work ../../../fifo_short_2clk.v +ncvhdl -v93 -work work ../../example_design/fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +ncvhdl -v93 -work work ../fifo_short_2clk_pkg.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_rng.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_dgen.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_dverif.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_pctrl.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_synth.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_tb.vhd + +echo "Elaborating Design" +ncvlog -work work $XILINX/verilog/src/glbl.v +ncelab -access +rwc glbl work.fifo_short_2clk_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_short_2clk_tb + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_vcs.sh new file mode 100755 index 000000000..71a568e24 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_vcs.sh @@ -0,0 +1,69 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogan +v2k ../../../fifo_short_2clk.v +vhdlan ../../example_design/fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhdlan ../fifo_short_2clk_pkg.vhd +vhdlan ../fifo_short_2clk_rng.vhd +vhdlan ../fifo_short_2clk_dgen.vhd +vhdlan ../fifo_short_2clk_dverif.vhd +vhdlan ../fifo_short_2clk_pctrl.vhd +vhdlan ../fifo_short_2clk_synth.vhd +vhdlan ../fifo_short_2clk_tb.vhd + +echo "Elaborating Design" +vlogan +v2k $XILINX/verilog/src/glbl.v +vcs -time_res 1ps +vcs+lic+wait -debug fifo_short_2clk_tb glbl + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/ucli_commands.key b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/ucli_commands.key new file mode 100755 index 000000000..f90cccb67 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/ucli_commands.key @@ -0,0 +1,4 @@ +dump -file fifo_short_2clk.vpd -type VPD +dump -add fifo_short_2clk_tb +run +quit diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/vcs_session.tcl new file mode 100755 index 000000000..7f3170d74 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/vcs_session.tcl @@ -0,0 +1,77 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {fifo_short_2clk.vpd}] } { + gui_open_db -design V1 -file fifo_short_2clk.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + + +gui_open_window Wave +gui_sg_create fifo_short_2clk_Group +gui_list_add_group -id Wave.1 {fifo_short_2clk_Group} + +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +gui_sg_addsignal -group fifo_short_2clk_Group WRITE -divider +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +gui_sg_addsignal -group fifo_short_2clk_Group READ -divider +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_isim.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_isim.tcl new file mode 100755 index 000000000..156aad172 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_isim.tcl @@ -0,0 +1,68 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_isim.tcl +# +# Description: +# This is the ISIM wave form file. +# +#-------------------------------------------------------------------------------- +wcfg new +isim set radix hex +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +run all +quit + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_mti.do b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_mti.do new file mode 100755 index 000000000..eafc64cf2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_mti.do @@ -0,0 +1,88 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +# Filename: wave_mti.do +# +# Description: +# This is the modelsim wave form file. +# +#-------------------------------------------------------------------------------- + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +add wave -noupdate -divider WRITE +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DIN +add wave -noupdate -divider READ +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DOUT + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2164886 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_ncsim.sv b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_ncsim.sv new file mode 100755 index 000000000..655d5c65a --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_ncsim.sv @@ -0,0 +1,70 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_ncsim.sv +# +# Description: +# This is the IUS wave form file. +# +#-------------------------------------------------------------------------------- + +window new WaveWindow -name "Waves for FIFO Generator Example Design" +waveform using "Waves for FIFO Generator Example Design" + +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +waveform add -label WRITE +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +waveform add -label READ +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +console submit -using simulator -wait no "run" diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.bat new file mode 100755 index 000000000..536a7cfee --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.bat @@ -0,0 +1,61 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ..\\..\\implement\\results\\routed.v + +echo "Compiling Test Bench Files" +vhpcomp -work work ..\\fifo_short_2clk_pkg.vhd +vhpcomp -work work ..\\fifo_short_2clk_rng.vhd +vhpcomp -work work ..\\fifo_short_2clk_dgen.vhd +vhpcomp -work work ..\\fifo_short_2clk_dverif.vhd +vhpcomp -work work ..\\fifo_short_2clk_pctrl.vhd +vhpcomp -work work ..\\fifo_short_2clk_synth.vhd +vhpcomp -work work ..\\fifo_short_2clk_tb.vhd + +fuse work.fifo_short_2clk_tb work.glbl -L simprims_ver -o fifo_short_2clk_tb.exe + +.\\fifo_short_2clk_tb.exe -sdfmax /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst=..\\..\\implement\\results\\routed.sdf -gui -tclbatch .\\wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.sh new file mode 100755 index 000000000..2d9404294 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.sh @@ -0,0 +1,63 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vhpcomp -work work ../fifo_short_2clk_pkg.vhd +vhpcomp -work work ../fifo_short_2clk_rng.vhd +vhpcomp -work work ../fifo_short_2clk_dgen.vhd +vhpcomp -work work ../fifo_short_2clk_dverif.vhd +vhpcomp -work work ../fifo_short_2clk_pctrl.vhd +vhpcomp -work work ../fifo_short_2clk_synth.vhd +vhpcomp -work work ../fifo_short_2clk_tb.vhd + +fuse work.fifo_short_2clk_tb work.glbl -L simprims_ver -o fifo_short_2clk_tb.exe + +./fifo_short_2clk_tb.exe -sdfmax /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst=../../implement/results/routed.sdf -gui -tclbatch ./wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.bat new file mode 100755 index 000000000..35375ce20 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.bat @@ -0,0 +1,47 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.do b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.do new file mode 100755 index 000000000..7ec785533 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.do @@ -0,0 +1,72 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vcom -work work ../fifo_short_2clk_pkg.vhd +vcom -work work ../fifo_short_2clk_rng.vhd +vcom -work work ../fifo_short_2clk_dgen.vhd +vcom -work work ../fifo_short_2clk_dverif.vhd +vcom -work work ../fifo_short_2clk_pctrl.vhd +vcom -work work ../fifo_short_2clk_synth.vhd +vcom -work work ../fifo_short_2clk_tb.vhd + +vsim -t ps -voptargs="+acc" +transport_int_delays -L simprims_ver glbl -sdfmax /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst=../../implement/results/routed.sdf work.fifo_short_2clk_tb + +add log -r /* +do wave_mti.do +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.sh new file mode 100755 index 000000000..edb1b0dd9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.sh @@ -0,0 +1,49 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_ncsim.sh new file mode 100755 index 000000000..e9dc952cf --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_ncsim.sh @@ -0,0 +1,73 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +mkdir work +echo "Compiling Core Verilog UNISIM/Behavioral model" +ncvlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +ncvhdl -v93 -work work ../fifo_short_2clk_pkg.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_rng.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_dgen.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_dverif.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_pctrl.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_synth.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_tb.vhd + +echo "Compiling SDF file" +ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X + +echo "Generating SDF command file" +echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd +echo 'SCOPE = :fifo_short_2clk_synth_inst:fifo_short_2clk_inst,' >> sdf.cmd +echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd + +echo "Elaborating Design" +ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd work.fifo_short_2clk_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_short_2clk_tb diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_vcs.sh new file mode 100755 index 000000000..bbd548a74 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_vcs.sh @@ -0,0 +1,67 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogan +v2k ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vhdlan ../fifo_short_2clk_pkg.vhd +vhdlan ../fifo_short_2clk_rng.vhd +vhdlan ../fifo_short_2clk_dgen.vhd +vhdlan ../fifo_short_2clk_dverif.vhd +vhdlan ../fifo_short_2clk_pctrl.vhd +vhdlan ../fifo_short_2clk_synth.vhd +vhdlan ../fifo_short_2clk_tb.vhd + +echo "Elaborating Design" +vcs -time_res 1ps +neg_tchk -sdf max:/fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst:../../implement/results/routed.sdf +vcs+lic+wait -debug fifo_short_2clk_tb glbl + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/ucli_commands.key b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/ucli_commands.key new file mode 100755 index 000000000..f90cccb67 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/ucli_commands.key @@ -0,0 +1,4 @@ +dump -file fifo_short_2clk.vpd -type VPD +dump -add fifo_short_2clk_tb +run +quit diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/vcs_session.tcl new file mode 100755 index 000000000..e27baa9d8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/vcs_session.tcl @@ -0,0 +1,76 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {fifo_short_2clk.vpd}] } { + gui_open_db -design V1 -file fifo_short_2clk.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + +gui_open_window Wave +gui_sg_create fifo_short_2clk_Group +gui_list_add_group -id Wave.1 {fifo_short_2clk_Group} + +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +gui_sg_addsignal -group fifo_short_2clk_Group WRITE -divider +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +gui_sg_addsignal -group fifo_short_2clk_Group READ -divider +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_isim.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_isim.tcl new file mode 100755 index 000000000..156aad172 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_isim.tcl @@ -0,0 +1,68 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_isim.tcl +# +# Description: +# This is the ISIM wave form file. +# +#-------------------------------------------------------------------------------- +wcfg new +isim set radix hex +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +run all +quit + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_mti.do b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_mti.do new file mode 100755 index 000000000..eafc64cf2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_mti.do @@ -0,0 +1,88 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +# Filename: wave_mti.do +# +# Description: +# This is the modelsim wave form file. +# +#-------------------------------------------------------------------------------- + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +add wave -noupdate -divider WRITE +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DIN +add wave -noupdate -divider READ +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DOUT + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2164886 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_ncsim.sv b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_ncsim.sv new file mode 100755 index 000000000..655d5c65a --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_ncsim.sv @@ -0,0 +1,70 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_ncsim.sv +# +# Description: +# This is the IUS wave form file. +# +#-------------------------------------------------------------------------------- + +window new WaveWindow -name "Waves for FIFO Generator Example Design" +waveform using "Waves for FIFO Generator Example Design" + +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +waveform add -label WRITE +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +waveform add -label READ +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +console submit -using simulator -wait no "run" diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk_flist.txt b/fpga/usrp3/top/b200/coregen/fifo_short_2clk_flist.txt new file mode 100644 index 000000000..4ab119a52 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk_flist.txt @@ -0,0 +1,57 @@ +# Output products list for <fifo_short_2clk> +_xmsgs/pn_parser.xmsgs +fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt +fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html +fifo_short_2clk/doc/pg057-fifo-generator.pdf +fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf +fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd +fifo_short_2clk/fifo_generator_v9_3_readme.txt +fifo_short_2clk/implement/implement.bat +fifo_short_2clk/implement/implement.sh +fifo_short_2clk/implement/implement_synplify.bat +fifo_short_2clk/implement/implement_synplify.sh +fifo_short_2clk/implement/planAhead_ise.bat +fifo_short_2clk/implement/planAhead_ise.sh +fifo_short_2clk/implement/planAhead_ise.tcl +fifo_short_2clk/implement/xst.prj +fifo_short_2clk/implement/xst.scr +fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd +fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd +fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd +fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd +fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd +fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd +fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd +fifo_short_2clk/simulation/functional/simulate_isim.bat +fifo_short_2clk/simulation/functional/simulate_isim.sh +fifo_short_2clk/simulation/functional/simulate_mti.bat +fifo_short_2clk/simulation/functional/simulate_mti.do +fifo_short_2clk/simulation/functional/simulate_mti.sh +fifo_short_2clk/simulation/functional/simulate_ncsim.sh +fifo_short_2clk/simulation/functional/simulate_vcs.sh +fifo_short_2clk/simulation/functional/ucli_commands.key +fifo_short_2clk/simulation/functional/vcs_session.tcl +fifo_short_2clk/simulation/functional/wave_isim.tcl +fifo_short_2clk/simulation/functional/wave_mti.do +fifo_short_2clk/simulation/functional/wave_ncsim.sv +fifo_short_2clk/simulation/timing/simulate_isim.bat +fifo_short_2clk/simulation/timing/simulate_isim.sh +fifo_short_2clk/simulation/timing/simulate_mti.bat +fifo_short_2clk/simulation/timing/simulate_mti.do +fifo_short_2clk/simulation/timing/simulate_mti.sh +fifo_short_2clk/simulation/timing/simulate_ncsim.sh +fifo_short_2clk/simulation/timing/simulate_vcs.sh +fifo_short_2clk/simulation/timing/ucli_commands.key +fifo_short_2clk/simulation/timing/vcs_session.tcl +fifo_short_2clk/simulation/timing/wave_isim.tcl +fifo_short_2clk/simulation/timing/wave_mti.do +fifo_short_2clk/simulation/timing/wave_ncsim.sv +fifo_short_2clk.asy +fifo_short_2clk.gise +fifo_short_2clk.ngc +fifo_short_2clk.v +fifo_short_2clk.veo +fifo_short_2clk.xco +fifo_short_2clk.xise +fifo_short_2clk_flist.txt +fifo_short_2clk_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk_xmdf.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk_xmdf.tcl new file mode 100644 index 000000000..0abe2bb7c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk_xmdf.tcl @@ -0,0 +1,251 @@ +# The package naming convention is <core_name>_xmdf +package provide fifo_short_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is <core_name>_xmdf +namespace eval ::fifo_short_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_short_2clk_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: <module_name> +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_short_2clk +} +# ::fifo_short_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_short_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/doc/pg057-fifo-generator.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/fifo_generator_v9_3_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement_synplify.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement_synplify.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/planAhead_ise.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/planAhead_ise.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/planAhead_ise.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/wave_isim.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/wave_isim.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_short_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams |