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authormichael-west <michael.west@ettus.com>2014-07-30 11:54:26 -0700
committermichael-west <michael.west@ettus.com>2014-07-30 11:54:26 -0700
commit35fc42f9fcbc5a791bdabc92086a51a2279563f1 (patch)
treefd053dd7e462fd49759ae255334de6d5c5aefd59 /fpga/usrp3/top/b200/b200_core.v
parentbca5edb57979983a9eb8d6cd1016961552ad217c (diff)
parenteafae66c030aa86e9da127de4f6d5ec4fd641c59 (diff)
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Merge branch 'maint' into uhd/bug492
Conflicts: host/lib/usrp/b200/b200_impl.cpp
Diffstat (limited to 'fpga/usrp3/top/b200/b200_core.v')
-rw-r--r--fpga/usrp3/top/b200/b200_core.v25
1 files changed, 19 insertions, 6 deletions
diff --git a/fpga/usrp3/top/b200/b200_core.v b/fpga/usrp3/top/b200/b200_core.v
index 016037688..dc8baba4f 100644
--- a/fpga/usrp3/top/b200/b200_core.v
+++ b/fpga/usrp3/top/b200/b200_core.v
@@ -1,5 +1,5 @@
//
-// Copyright 2013 Ettus Research LLC
+// Copyright 2013-14 Ettus Research LLC
//
@@ -78,11 +78,24 @@ module b200_core
/*******************************************************************
* PPS Timing stuff
******************************************************************/
- reg [1:0] int_pps_del, ext_pps_del;
+
+ // Generate an internal PPS signal
+ wire int_pps;
+ pps_generator #(.CLK_FREQ(100000000)) pps_gen
+ (.clk(bus_clk), .pps(int_pps));
+
+ // Flop PPS signals into radio clock domain
+ reg [1:0] gpsdo_pps_del, ext_pps_del, int_pps_del;
always @(posedge radio_clk) ext_pps_del[1:0] <= {ext_pps_del[0], pps_ext};
- always @(posedge radio_clk) int_pps_del[1:0] <= {int_pps_del[0], pps_int};
- wire pps_select;
- wire pps = pps_select? ext_pps_del[1] : int_pps_del[1];
+ always @(posedge radio_clk) gpsdo_pps_del[1:0] <= {gpsdo_pps_del[0], pps_int};
+ always @(posedge radio_clk) int_pps_del[1:0] <= {int_pps_del[0], int_pps};
+
+ // PPS mux
+ wire [1:0] pps_select;
+ wire pps = (pps_select == 2'b00)? gpsdo_pps_del[1] :
+ (pps_select == 2'b01)? ext_pps_del[1] :
+ (pps_select == 2'b10)? int_pps_del[1] :
+ 1'b0;
/*******************************************************************
* Response mux Routing logic
@@ -189,7 +202,7 @@ module b200_core
(.clk(bus_clk), .rst(1'b0/*keep*/), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(gpsdo_st), .changed());
- setting_reg #(.my_addr(SR_CORE_PPS_SEL), .awidth(8), .width(1)) sr_pps_sel
+ setting_reg #(.my_addr(SR_CORE_PPS_SEL), .awidth(8), .width(2)) sr_pps_sel
(.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(pps_select), .changed());