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author | Ben Hilburn <ben.hilburn@ettus.com> | 2014-02-14 12:05:07 -0800 |
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committer | Ben Hilburn <ben.hilburn@ettus.com> | 2014-02-14 12:05:07 -0800 |
commit | ff1546f8137f7f92bb250f685561b0c34cc0e053 (patch) | |
tree | 7fa6fd05c8828df256a1b20e2935bd3ba9899e2c /fpga/usrp3/top/b200/Makefile.b200.inc | |
parent | 4f691d88123784c2b405816925f1a1aef69d18c1 (diff) | |
download | uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.tar.gz uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.tar.bz2 uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.zip |
Pushing the bulk of UHD-3.7.0 code.
Diffstat (limited to 'fpga/usrp3/top/b200/Makefile.b200.inc')
-rw-r--r-- | fpga/usrp3/top/b200/Makefile.b200.inc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/fpga/usrp3/top/b200/Makefile.b200.inc b/fpga/usrp3/top/b200/Makefile.b200.inc index da7561cab..288a29fe3 100644 --- a/fpga/usrp3/top/b200/Makefile.b200.inc +++ b/fpga/usrp3/top/b200/Makefile.b200.inc @@ -22,6 +22,7 @@ include ../../lib/packet_proc/Makefile.srcs include ../../lib/timing/Makefile.srcs include ../../lib/vita/Makefile.srcs include ../../lib/wishbone/Makefile.srcs +include ../../lib/axi/Makefile.srcs B200_COREGEN_SRCS = \ coregen/b200_clk_gen.v \ @@ -76,7 +77,8 @@ $(GPIF2_SRCS) $(PACKET_PROC_SRCS) \ $(WISHBONE_SRCS) \ $(TIMING_SRCS) \ $(DSP_SRCS) \ -$(VITA_SRCS) +$(VITA_SRCS) \ +$(AXI_SRCS) ################################################## # Process Properties |