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| author | Wade Fife <wade.fife@ettus.com> | 2021-06-03 12:58:37 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2021-06-17 08:16:59 -0500 |
| commit | 648c70ae758ab1d15c7ec6cbe57672e8c27640cd (patch) | |
| tree | 11e1d5d11f24fa41ff29ecf5bd5332ad3ba9d755 /fpga/usrp3/tools | |
| parent | 244608187f824903ea2c8b003be1918d7dc21d5e (diff) | |
| download | uhd-648c70ae758ab1d15c7ec6cbe57672e8c27640cd.tar.gz uhd-648c70ae758ab1d15c7ec6cbe57672e8c27640cd.tar.bz2 uhd-648c70ae758ab1d15c7ec6cbe57672e8c27640cd.zip | |
fpga: tools: Support new FPGA types in viv_simulator.mak
This updates the existing PART_NAME generation used in simulation
makefiles to work with newer part families by calling
viv_gen_part_id.py to generate the part name needed by Vivado.
Diffstat (limited to 'fpga/usrp3/tools')
| -rw-r--r-- | fpga/usrp3/tools/make/viv_simulator.mak | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/fpga/usrp3/tools/make/viv_simulator.mak b/fpga/usrp3/tools/make/viv_simulator.mak index f37cc9626..64af051a1 100644 --- a/fpga/usrp3/tools/make/viv_simulator.mak +++ b/fpga/usrp3/tools/make/viv_simulator.mak @@ -21,8 +21,8 @@ ifdef SIM_COMPLIBDIR COMPLIBDIR = $(call RESOLVE_PATH,$(SIM_COMPLIBDIR)) endif -# Parse part name from ID -PART_NAME=$(subst /,,$(PART_ID)) +# Get full part name, formatted for Vivado +PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(ARCH)/$(PART_ID)` # Resolve path EXP_DESIGN_SRCS = $(call RESOLVE_PATHS,$(DESIGN_SRCS)) |