From 648c70ae758ab1d15c7ec6cbe57672e8c27640cd Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Thu, 3 Jun 2021 12:58:37 -0500 Subject: fpga: tools: Support new FPGA types in viv_simulator.mak This updates the existing PART_NAME generation used in simulation makefiles to work with newer part families by calling viv_gen_part_id.py to generate the part name needed by Vivado. --- fpga/usrp3/tools/make/viv_simulator.mak | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'fpga/usrp3/tools') diff --git a/fpga/usrp3/tools/make/viv_simulator.mak b/fpga/usrp3/tools/make/viv_simulator.mak index f37cc9626..64af051a1 100644 --- a/fpga/usrp3/tools/make/viv_simulator.mak +++ b/fpga/usrp3/tools/make/viv_simulator.mak @@ -21,8 +21,8 @@ ifdef SIM_COMPLIBDIR COMPLIBDIR = $(call RESOLVE_PATH,$(SIM_COMPLIBDIR)) endif -# Parse part name from ID -PART_NAME=$(subst /,,$(PART_ID)) +# Get full part name, formatted for Vivado +PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(ARCH)/$(PART_ID)` # Resolve path EXP_DESIGN_SRCS = $(call RESOLVE_PATHS,$(DESIGN_SRCS)) -- cgit v1.2.3