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| author | Wade Fife <wade.fife@ettus.com> | 2021-06-09 10:09:22 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2021-06-17 08:16:59 -0500 |
| commit | 4dc2b7010c0f3e41758b8192636ef7672caae0f7 (patch) | |
| tree | ddd120f8750bc08b4c4ff935a3b03888f5e89a89 /fpga/usrp3/tools | |
| parent | 9ff2dd8e41e6f34d99cba28640ab00290906cae6 (diff) | |
| download | uhd-4dc2b7010c0f3e41758b8192636ef7672caae0f7.tar.gz uhd-4dc2b7010c0f3e41758b8192636ef7672caae0f7.tar.bz2 uhd-4dc2b7010c0f3e41758b8192636ef7672caae0f7.zip | |
fpga: tools: Add ip target to simulation makefiles
Allow building of just the IP by running "make ip" in simulation
directories.
Diffstat (limited to 'fpga/usrp3/tools')
| -rw-r--r-- | fpga/usrp3/tools/make/viv_simulator.mak | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/fpga/usrp3/tools/make/viv_simulator.mak b/fpga/usrp3/tools/make/viv_simulator.mak index 66af10fec..eaa23adcc 100644 --- a/fpga/usrp3/tools/make/viv_simulator.mak +++ b/fpga/usrp3/tools/make/viv_simulator.mak @@ -86,6 +86,9 @@ SETUP_AND_LAUNCH_MODELSIM = \ .SECONDEXPANSION: +##ip: Generate the IP required for this simulation +ip: $(DESIGN_SRCS) + ##xsim: Run the simulation using the Xilinx Vivado Simulator xsim: .check_tool $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS) $(call SETUP_AND_LAUNCH_SIMULATION,XSim) @@ -111,7 +114,7 @@ modelsim: .check_tool vlint # NOTE: VHDL files require a correct compile order. This script compiles files # in the order they are defined in $(DESIGN_SRC), then $SIM_SRC) -##vlint: Run ModelSim compiler to lint files. +##vlint: Run ModelSim compiler to lint files vlint: .check_tool $(COMPLIBDIR) $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS) $(call SETUP_AND_LAUNCH_VLINT) @@ -127,4 +130,4 @@ clean:: xclean vclean help:: @grep -h "##" $(abspath $(lastword $(MAKEFILE_LIST))) | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//' -.PHONY: xsim xsim_hls xclean vsim vlint vclean clean help +.PHONY: ip xsim xsim_hls xclean vsim vlint vclean clean help |