From 4dc2b7010c0f3e41758b8192636ef7672caae0f7 Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Wed, 9 Jun 2021 10:09:22 -0500 Subject: fpga: tools: Add ip target to simulation makefiles Allow building of just the IP by running "make ip" in simulation directories. --- fpga/usrp3/tools/make/viv_simulator.mak | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'fpga/usrp3/tools') diff --git a/fpga/usrp3/tools/make/viv_simulator.mak b/fpga/usrp3/tools/make/viv_simulator.mak index 66af10fec..eaa23adcc 100644 --- a/fpga/usrp3/tools/make/viv_simulator.mak +++ b/fpga/usrp3/tools/make/viv_simulator.mak @@ -86,6 +86,9 @@ SETUP_AND_LAUNCH_MODELSIM = \ .SECONDEXPANSION: +##ip: Generate the IP required for this simulation +ip: $(DESIGN_SRCS) + ##xsim: Run the simulation using the Xilinx Vivado Simulator xsim: .check_tool $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS) $(call SETUP_AND_LAUNCH_SIMULATION,XSim) @@ -111,7 +114,7 @@ modelsim: .check_tool vlint # NOTE: VHDL files require a correct compile order. This script compiles files # in the order they are defined in $(DESIGN_SRC), then $SIM_SRC) -##vlint: Run ModelSim compiler to lint files. +##vlint: Run ModelSim compiler to lint files vlint: .check_tool $(COMPLIBDIR) $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS) $(call SETUP_AND_LAUNCH_VLINT) @@ -127,4 +130,4 @@ clean:: xclean vclean help:: @grep -h "##" $(abspath $(lastword $(MAKEFILE_LIST))) | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//' -.PHONY: xsim xsim_hls xclean vsim vlint vclean clean help +.PHONY: ip xsim xsim_hls xclean vsim vlint vclean clean help -- cgit v1.2.3