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| author | Wade Fife <wade.fife@ettus.com> | 2021-06-10 11:50:04 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2021-06-17 08:16:59 -0500 |
| commit | 6190eca14ec13db7456a059cbd69c93550aa45c7 (patch) | |
| tree | 0dc272a0e66e2b3884019626ddb514466a98e528 /fpga/usrp3/tools/utils | |
| parent | 08473776b28a949027ec8cf2596d8d1b438b979b (diff) | |
| download | uhd-6190eca14ec13db7456a059cbd69c93550aa45c7.tar.gz uhd-6190eca14ec13db7456a059cbd69c93550aa45c7.tar.bz2 uhd-6190eca14ec13db7456a059cbd69c93550aa45c7.zip | |
fpga: tools: Add modelsim.excludes
This is a list of testbenches that don't work with ModelSim and should
be excluded when running run_testbenches.py.
Diffstat (limited to 'fpga/usrp3/tools/utils')
| -rw-r--r-- | fpga/usrp3/tools/utils/modelsim.excludes | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/fpga/usrp3/tools/utils/modelsim.excludes b/fpga/usrp3/tools/utils/modelsim.excludes new file mode 100644 index 000000000..41df329c4 --- /dev/null +++ b/fpga/usrp3/tools/utils/modelsim.excludes @@ -0,0 +1,18 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# This file contains all testbenches to exclude from the list discovered +# by run_testbenches.py for the ModelSim simulator. +# + +top/e31x/sim/dram_test +top/n3xx/sim/arm_to_sfp_loopback +top/n3xx/sim/aurora_loopback +top/n3xx/sim/one_gig_eth_loopback +top/n3xx/sim/ten_gig_eth_loopback +top/x300/sim/x300_pcie_int + +# This TB doesn't pass in ModelSim +top/x300/sim/dram_fifo_bist |