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author | Wade Fife <wade.fife@ettus.com> | 2021-06-10 11:45:58 -0500 |
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committer | Wade Fife <wade.fife@ettus.com> | 2021-06-17 08:16:59 -0500 |
commit | 319d8c6411f62a2150b21b38bfe5fd55366ee700 (patch) | |
tree | 7b44766d72b00aa189c3094c9cc6c0f8ed00cdb2 /fpga/usrp3/tools/utils | |
parent | 574146ec8909da367c3441189c2877a287892f7e (diff) | |
download | uhd-319d8c6411f62a2150b21b38bfe5fd55366ee700.tar.gz uhd-319d8c6411f62a2150b21b38bfe5fd55366ee700.tar.bz2 uhd-319d8c6411f62a2150b21b38bfe5fd55366ee700.zip |
fpga: x400: Add makefiles for RF testbenches
Diffstat (limited to 'fpga/usrp3/tools/utils')
-rw-r--r-- | fpga/usrp3/tools/utils/testbenches.excludes | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/fpga/usrp3/tools/utils/testbenches.excludes b/fpga/usrp3/tools/utils/testbenches.excludes index 9566b0015..bfcc7d87d 100644 --- a/fpga/usrp3/tools/utils/testbenches.excludes +++ b/fpga/usrp3/tools/utils/testbenches.excludes @@ -1,6 +1,5 @@ -# This file contains all testbenches to exlcude from the filter -# list discovered by run_testbenches.py -# NOTE: Lines containing "#" are treated as a comment +# This file contains all testbenches to exlcude from the filter list discovered +# by run_testbenches.py with the Vivado simulator (xsim). top/e31x/sim/dram_test top/n3xx/sim/arm_to_sfp_loopback @@ -15,3 +14,4 @@ lib/axi4s_sv/axi4s_add_bytes_tb lib/rfnoc/xport_sv/eth_interface_tb top/x400/sim/x4xx_qsfp_wrapper top/x400/ip/eth_100g_bd/lbus_tb +top/x400/rf/sim |