fpga: tools: Add features to run_testbenches.py

Run "make ip" in a separate step for each testbench. This allows some
testbenches to work better with ModelSim because it needs IP files that
aren't known until after the IP is generated.

Make run_testbenches.py more log friendly. Add a -l/--logged option for
when the output is being logged. In this case, we don't want to display
elapsed time every second.

Add "Begin TB Log:" and "End TB Log:" to the output to more easily tell
where the output from one testbench ends and another begins.

Use the basedir argument as the base directory in which to search for
testbenches so that a subset of the repo can be easily specified.

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