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| author | Wade Fife <wade.fife@ettus.com> | 2020-05-15 14:04:38 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-05-26 13:36:55 -0500 |
| commit | 90933d9b2faf392fd26f3f7ca32f73719614a40a (patch) | |
| tree | 18d861b4b7a83054c7b9bc5c6e937bac73fe3458 /fpga/usrp3/tools/make | |
| parent | a24cfbac866ba713714dcddb753d4ad808d200c6 (diff) | |
| download | uhd-90933d9b2faf392fd26f3f7ca32f73719614a40a.tar.gz uhd-90933d9b2faf392fd26f3f7ca32f73719614a40a.tar.bz2 uhd-90933d9b2faf392fd26f3f7ca32f73719614a40a.zip | |
fpga: tools: Add contents of directories for HDL source
For HLS builds, the output file names aren't known in advance. This
makes it difficult to write the Makefile to pull in the files and pass
them to the build tools. This change allows you to add a directory as
your HDL source so that all files in the directory will be pulled in by
the build process.
Diffstat (limited to 'fpga/usrp3/tools/make')
| -rw-r--r-- | fpga/usrp3/tools/make/viv_hls_ip_builder.mak | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/tools/make/viv_hls_ip_builder.mak b/fpga/usrp3/tools/make/viv_hls_ip_builder.mak index 77f09157f..10c5a8330 100644 --- a/fpga/usrp3/tools/make/viv_hls_ip_builder.mak +++ b/fpga/usrp3/tools/make/viv_hls_ip_builder.mak @@ -4,7 +4,7 @@ # ------------------------------------------------------------------- # Usage: BUILD_VIVADO_HLS_IP -# Args: $1 = HLS_IP_NAME (High level synthsis IP name) +# Args: $1 = HLS_IP_NAME (High level synthesis IP name) # $2 = PART_ID (<device>/<package>/<speedgrade>) # $3 = HLS_IP_SRCS (Absolute paths to the HLS IP source files) # $4 = HLS_IP_SRC_DIR (Absolute path to the top level HLS IP src dir) |