From 90933d9b2faf392fd26f3f7ca32f73719614a40a Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Fri, 15 May 2020 14:04:38 -0500 Subject: fpga: tools: Add contents of directories for HDL source For HLS builds, the output file names aren't known in advance. This makes it difficult to write the Makefile to pull in the files and pass them to the build tools. This change allows you to add a directory as your HDL source so that all files in the directory will be pulled in by the build process. --- fpga/usrp3/tools/make/viv_hls_ip_builder.mak | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'fpga/usrp3/tools/make') diff --git a/fpga/usrp3/tools/make/viv_hls_ip_builder.mak b/fpga/usrp3/tools/make/viv_hls_ip_builder.mak index 77f09157f..10c5a8330 100644 --- a/fpga/usrp3/tools/make/viv_hls_ip_builder.mak +++ b/fpga/usrp3/tools/make/viv_hls_ip_builder.mak @@ -4,7 +4,7 @@ # ------------------------------------------------------------------- # Usage: BUILD_VIVADO_HLS_IP -# Args: $1 = HLS_IP_NAME (High level synthsis IP name) +# Args: $1 = HLS_IP_NAME (High level synthesis IP name) # $2 = PART_ID (//) # $3 = HLS_IP_SRCS (Absolute paths to the HLS IP source files) # $4 = HLS_IP_SRC_DIR (Absolute path to the top level HLS IP src dir) -- cgit v1.2.3