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| author | Wade Fife <wade.fife@ettus.com> | 2021-06-10 11:50:04 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2021-06-17 08:16:59 -0500 |
| commit | 6190eca14ec13db7456a059cbd69c93550aa45c7 (patch) | |
| tree | 0dc272a0e66e2b3884019626ddb514466a98e528 /fpga/usrp3/tools/make/viv_ip_builder.mak | |
| parent | 08473776b28a949027ec8cf2596d8d1b438b979b (diff) | |
| download | uhd-6190eca14ec13db7456a059cbd69c93550aa45c7.tar.gz uhd-6190eca14ec13db7456a059cbd69c93550aa45c7.tar.bz2 uhd-6190eca14ec13db7456a059cbd69c93550aa45c7.zip | |
fpga: tools: Add modelsim.excludes
This is a list of testbenches that don't work with ModelSim and should
be excluded when running run_testbenches.py.
Diffstat (limited to 'fpga/usrp3/tools/make/viv_ip_builder.mak')
0 files changed, 0 insertions, 0 deletions