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| author | Wade Fife <wade.fife@ettus.com> | 2022-02-26 12:18:57 -0600 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2022-03-04 18:46:12 -0600 |
| commit | 822cd03c8cd686f8b0554774adcbdd3803128bc2 (patch) | |
| tree | d5f562ba28b581255363280dc9150307d9f0c830 /fpga/usrp3/sim | |
| parent | 8f68886ee3045abb486bfa8179e7129ebd377580 (diff) | |
| download | uhd-822cd03c8cd686f8b0554774adcbdd3803128bc2.tar.gz uhd-822cd03c8cd686f8b0554774adcbdd3803128bc2.tar.bz2 uhd-822cd03c8cd686f8b0554774adcbdd3803128bc2.zip | |
fpga: x400: Change AXI XB for DRAM to 512-bit
Change the width of the crossbar in the AXI Interconnect IP from
256-bit to 512-bit to match the DRAM memory controller width and to
give better performance.
Diffstat (limited to 'fpga/usrp3/sim')
0 files changed, 0 insertions, 0 deletions