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authormichael-west <michael.west@ettus.com>2014-03-07 13:23:00 -0800
committermichael-west <michael.west@ettus.com>2014-03-07 13:23:00 -0800
commita8d4649c4e95a5d8ccfe3c52fdbfc05c984f3acc (patch)
tree603d535d764e0850d7b99df3ab619daaaefe2f21 /fpga/usrp3/sim/ddc_chain_x300
parent973b47c48339dbae2e125a8c8d84ef67fedc4bdf (diff)
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Fix for BUG #386: RIO & UHD: Flush buffers smarter
- Updated flush algorithm to acquire and release all elements instead of 1 element at a time
Diffstat (limited to 'fpga/usrp3/sim/ddc_chain_x300')
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