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| author | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
| commit | fd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch) | |
| tree | 3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp3/sim/b2x0/sim_b2x0_1 | |
| parent | 3b66804e41891e358c790b453a7a59ec7462dba4 (diff) | |
| download | uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.gz uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.bz2 uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.zip | |
Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp3/sim/b2x0/sim_b2x0_1')
| -rwxr-xr-x | fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim b/fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim deleted file mode 100755 index dd9215934..000000000 --- a/fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim +++ /dev/null @@ -1,22 +0,0 @@ -vlogcomp -work work ${XILINX}/verilog/src/glbl.v - -vlogcomp -work work --sourcelibext .v \ - --sourcelibdir ../../../lib/axi \ - --sourcelibdir ../../../lib/fifo \ - --sourcelibdir ../../../lib/control \ - --sourcelibdir ../../../top/b200/coregen \ - --sourcelibdir ../../../top/b200 \ - --sourcelibdir ../../../lib/timing \ - --sourcelibdir ../../../lib/vita \ - --sourcelibdir ../../../lib/packet_proc \ - --sourcelibdir ../../../lib/dsp \ - --sourcelibdir ../../../lib/wishbone \ - --sourcelibdir ../../../lib/gpif2 \ - ../../../top/b200/b200_tb.v - - - -fuse work.b200_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o b200_tb.exe - -# run the simulation scrip -./b200_tb.exe # -gui #-tclbatch simcmds.tcl |