diff options
author | Ben Hilburn <ben.hilburn@ettus.com> | 2014-02-14 12:05:07 -0800 |
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committer | Ben Hilburn <ben.hilburn@ettus.com> | 2014-02-14 12:05:07 -0800 |
commit | ff1546f8137f7f92bb250f685561b0c34cc0e053 (patch) | |
tree | 7fa6fd05c8828df256a1b20e2935bd3ba9899e2c /fpga/usrp3/sim/axi_dram_fifo | |
parent | 4f691d88123784c2b405816925f1a1aef69d18c1 (diff) | |
download | uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.tar.gz uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.tar.bz2 uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.zip |
Pushing the bulk of UHD-3.7.0 code.
Diffstat (limited to 'fpga/usrp3/sim/axi_dram_fifo')
-rw-r--r-- | fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/default.wcfg | 412 | ||||
-rwxr-xr-x | fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/run_isim | 17 | ||||
-rw-r--r-- | fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/simulation_script.v | 113 | ||||
-rw-r--r-- | fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/Default.wcfg | 388 | ||||
-rwxr-xr-x | fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim | 19 | ||||
-rw-r--r-- | fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/simulation_script.v | 91 |
6 files changed, 1040 insertions, 0 deletions
diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/default.wcfg b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/default.wcfg new file mode 100644 index 000000000..796071597 --- /dev/null +++ b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/default.wcfg @@ -0,0 +1,412 @@ +<?xml version="1.0" encoding="UTF-8"?> +<wave_config> + <wave_state> + </wave_state> + <db_ref_list> + <db_ref path="./isim.wdb" id="1" type="auto"> + <top_modules> + <top_module name="axi_dram_fifo_tb" /> + <top_module name="glbl" /> + </top_modules> + </db_ref> + </db_ref_list> + <WVObjectSize size="38" /> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/clk" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">clk</obj_property> + <obj_property name="ObjectShortName">clk</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/reset" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">reset</obj_property> + <obj_property name="ObjectShortName">reset</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/clear" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">clear</obj_property> + <obj_property name="ObjectShortName">clear</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/count_rx" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">count_rx[31:0]</obj_property> + <obj_property name="ObjectShortName">count_rx[31:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/count_tx" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">count_tx[31:0]</obj_property> + <obj_property name="ObjectShortName">count_tx[31:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">i_tdata[63:0]</obj_property> + <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tlast" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">i_tlast</obj_property> + <obj_property name="ObjectShortName">i_tlast</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">i_tvalid</obj_property> + <obj_property name="ObjectShortName">i_tvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">i_tready</obj_property> + <obj_property name="ObjectShortName">i_tready</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_state" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">input_state[2:0]</obj_property> + <obj_property name="ObjectShortName">input_state[2:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/write_ctrl_ready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">write_ctrl_ready</obj_property> + <obj_property name="ObjectShortName">write_ctrl_ready</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/write_ctrl_valid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">write_ctrl_valid</obj_property> + <obj_property name="ObjectShortName">write_ctrl_valid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/occupied_input" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">occupied_input[5:0]</obj_property> + <obj_property name="ObjectShortName">occupied_input[5:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="group92" type="group"> + <obj_property name="label">INPUT TIMEOUT</obj_property> + <obj_property name="DisplayName">label</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_timeout_count" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">input_timeout_count[7:0]</obj_property> + <obj_property name="ObjectShortName">input_timeout_count[7:0]</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_timeout_reset" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">input_timeout_reset</obj_property> + <obj_property name="ObjectShortName">input_timeout_reset</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_timeout_triggered" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">input_timeout_triggered</obj_property> + <obj_property name="ObjectShortName">input_timeout_triggered</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="group60" type="group"> + <obj_property name="label">AXI_WADDR</obj_property> + <obj_property name="DisplayName">label</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/write_addr_state" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">write_addr_state[1:0]</obj_property> + <obj_property name="ObjectShortName">write_addr_state[1:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + <obj_property name="UseCustomSignalColor">true</obj_property> + <obj_property name="CustomSignalColor">#ffff00</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awid" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_awid[0:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_awid[0:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awaddr" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_awaddr[31:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_awaddr[31:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awlen" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_awlen[7:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_awlen[7:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awsize" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_awsize[2:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_awsize[2:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awburst" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_awburst[1:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_awburst[1:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_awvalid</obj_property> + <obj_property name="ObjectShortName">m_axi_awvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_awready</obj_property> + <obj_property name="ObjectShortName">m_axi_awready</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/write_data_count" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">write_data_count[3:0]</obj_property> + <obj_property name="ObjectShortName">write_data_count[3:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="group61" type="group"> + <obj_property name="label">AXI_WDATA</obj_property> + <obj_property name="DisplayName">label</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_wdata[63:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_wdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wstrb" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_wstrb[7:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_wstrb[7:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wlast" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_wlast</obj_property> + <obj_property name="ObjectShortName">m_axi_wlast</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_wvalid</obj_property> + <obj_property name="ObjectShortName">m_axi_wvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_wready</obj_property> + <obj_property name="ObjectShortName">m_axi_wready</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="group62" type="group"> + <obj_property name="label">AXI_WRESP</obj_property> + <obj_property name="DisplayName">label</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bid" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_bid[0:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_bid[0:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bresp" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_bresp[1:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_bresp[1:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_bvalid</obj_property> + <obj_property name="ObjectShortName">m_axi_bvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_bready</obj_property> + <obj_property name="ObjectShortName">m_axi_bready</obj_property> + <obj_property name="UseCustomSignalColor">true</obj_property> + <obj_property name="CustomSignalColor">#00ff00</obj_property> + <obj_property name="label">/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bready</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/space" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">space[10:0]</obj_property> + <obj_property name="ObjectShortName">space[10:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/occupied" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">occupied[10:0]</obj_property> + <obj_property name="ObjectShortName">occupied[10:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + <obj_property name="UseCustomSignalColor">true</obj_property> + <obj_property name="CustomSignalColor">#00ffff</obj_property> + </wvobject> + <wvobject fp_name="group63" type="group"> + <obj_property name="label">AXI_RADDR</obj_property> + <obj_property name="DisplayName">label</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/read_addr_state" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">read_addr_state[1:0]</obj_property> + <obj_property name="ObjectShortName">read_addr_state[1:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + <obj_property name="UseCustomSignalColor">true</obj_property> + <obj_property name="CustomSignalColor">#ffff00</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arid" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_arid[0:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_arid[0:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_araddr" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_araddr[31:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_araddr[31:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arlen" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_arlen[7:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_arlen[7:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arsize" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_arsize[2:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_arsize[2:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arburst" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_arburst[1:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_arburst[1:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_arvalid</obj_property> + <obj_property name="ObjectShortName">m_axi_arvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_arready</obj_property> + <obj_property name="ObjectShortName">m_axi_arready</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="group64" type="group"> + <obj_property name="label">AXI_RDATA</obj_property> + <obj_property name="DisplayName">label</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/read_data_state" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">read_data_state[1:0]</obj_property> + <obj_property name="ObjectShortName">read_data_state[1:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + <obj_property name="UseCustomSignalColor">true</obj_property> + <obj_property name="CustomSignalColor">#ffff00</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rid" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_rid[0:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_rid[0:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_rdata[63:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_rdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rresp" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_rresp[1:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_rresp[1:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rlast" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_rlast</obj_property> + <obj_property name="ObjectShortName">m_axi_rlast</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_rvalid</obj_property> + <obj_property name="ObjectShortName">m_axi_rvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_rready</obj_property> + <obj_property name="ObjectShortName">m_axi_rready</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/read_ctrl_valid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">read_ctrl_valid</obj_property> + <obj_property name="ObjectShortName">read_ctrl_valid</obj_property> + <obj_property name="UseCustomSignalColor">true</obj_property> + <obj_property name="CustomSignalColor">#ffff00</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/read_ctrl_ready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">read_ctrl_ready</obj_property> + <obj_property name="ObjectShortName">read_ctrl_ready</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/read_data_count" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">read_data_count[3:0]</obj_property> + <obj_property name="ObjectShortName">read_data_count[3:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_state" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">output_state[2:0]</obj_property> + <obj_property name="ObjectShortName">output_state[2:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/space_output" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">space_output[5:0]</obj_property> + <obj_property name="ObjectShortName">space_output[5:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="group80" type="group"> + <obj_property name="label">DRAM FIFO OUT</obj_property> + <obj_property name="DisplayName">label</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata_output" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">o_tdata_output[63:0]</obj_property> + <obj_property name="ObjectShortName">o_tdata_output[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid_output" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tvalid_output</obj_property> + <obj_property name="ObjectShortName">o_tvalid_output</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready_output" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tready_output</obj_property> + <obj_property name="ObjectShortName">o_tready_output</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/update_write" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">update_write</obj_property> + <obj_property name="ObjectShortName">update_write</obj_property> + <obj_property name="UseCustomSignalColor">true</obj_property> + <obj_property name="CustomSignalColor">#ff00ff</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/write_count" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">write_count[3:0]</obj_property> + <obj_property name="ObjectShortName">write_count[3:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/update_read" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">update_read</obj_property> + <obj_property name="ObjectShortName">update_read</obj_property> + <obj_property name="UseCustomSignalColor">true</obj_property> + <obj_property name="CustomSignalColor">#ff00ff</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/read_count" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">read_count[3:0]</obj_property> + <obj_property name="ObjectShortName">read_count[3:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="group68" type="group"> + <obj_property name="label">Output TImeout</obj_property> + <obj_property name="DisplayName">label</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_timeout_count" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">output_timeout_count[7:0]</obj_property> + <obj_property name="ObjectShortName">output_timeout_count[7:0]</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_timeout_reset" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">output_timeout_reset</obj_property> + <obj_property name="ObjectShortName">output_timeout_reset</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_timeout_triggered" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">output_timeout_triggered</obj_property> + <obj_property name="ObjectShortName">output_timeout_triggered</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="group76" type="group"> + <obj_property name="label">Extract TLAST</obj_property> + <obj_property name="DisplayName">label</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata_i0" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">o_tdata_i0[63:0]</obj_property> + <obj_property name="ObjectShortName">o_tdata_i0[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid_i0" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tvalid_i0</obj_property> + <obj_property name="ObjectShortName">o_tvalid_i0</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready_i0" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tready_i0</obj_property> + <obj_property name="ObjectShortName">o_tready_i0</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata_i1" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">o_tdata_i1[63:0]</obj_property> + <obj_property name="ObjectShortName">o_tdata_i1[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid_i1" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tvalid_i1</obj_property> + <obj_property name="ObjectShortName">o_tvalid_i1</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready_i1" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tready_i1</obj_property> + <obj_property name="ObjectShortName">o_tready_i1</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tlast_i1" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tlast_i1</obj_property> + <obj_property name="ObjectShortName">o_tlast_i1</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">o_tdata[63:0]</obj_property> + <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tlast" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tlast</obj_property> + <obj_property name="ObjectShortName">o_tlast</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tvalid</obj_property> + <obj_property name="ObjectShortName">o_tvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tready</obj_property> + <obj_property name="ObjectShortName">o_tready</obj_property> + </wvobject> +</wave_config> diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/run_isim b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/run_isim new file mode 100755 index 000000000..03eead1f7 --- /dev/null +++ b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/run_isim @@ -0,0 +1,17 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +#vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../packet_proc/source_flow_control_tb.v +vlogcomp -work work --sourcelibext .v \ + --sourcelibdir ../../../lib/axi \ + --sourcelibdir ../../../lib/fifo \ + --sourcelibdir ../../../lib/control \ + --sourcelibdir ../../../top/x300/coregen \ + ../../../lib/axi/axi_dram_fifo_tb.v + + + +fuse work.axi_dram_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_dram_fifo_tb.exe + +# run the simulation scrip +./axi_dram_fifo_tb.exe # -gui #-tclbatch simcmds.tcl + + diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/simulation_script.v b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/simulation_script.v new file mode 100644 index 000000000..eb72da360 --- /dev/null +++ b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/simulation_script.v @@ -0,0 +1,113 @@ +reg [31:0] count_rx, count_tx; +reg status; +reg fail; + + +// +// Use task library +// +`define USE_TASKS + + initial + begin + clk <= 1'b0; + reset <= 1'b0; + clear <= 1'b0; + i_tdata_r <= 0; + i_tlast_r <= 0; + i_tvalid_r <= 0; + o_tready_r <= 0; + end + + always + #5 clk <= ~clk; + + initial + begin + count_tx = 2; + count_rx = 2; + status = 0; + + + @(negedge clk); + reset <= 1'b1; + repeat(10) @(negedge clk); + reset <= 1'b0; + repeat(10) @(negedge clk); + + // Send 40 packets. + repeat(40) begin + send_raw_packet(count_tx); + repeat(2) @(posedge clk); + count_tx = count_tx + 1; + @(posedge clk); + end + repeat(100) @(posedge clk); + + + // Recieve 40 packets + repeat(40) begin + receive_raw_packet(count_rx,fail); + status = status || fail; + repeat(2) @(posedge clk); + count_rx = count_rx + 1; + @(posedge clk); + end + repeat(100) @(posedge clk); + + count_tx = 2; + count_rx = 2; + + // Send 40 packets. + repeat(40) begin + send_raw_packet(count_tx); + repeat(2) @(posedge clk); + count_tx = count_tx + 1; + @(posedge clk); + end + repeat(100) @(posedge clk); + // Now fork so send and receive run concurrently + fork + begin + // Send 40 packets. + repeat(40) begin + send_raw_packet(count_tx); + repeat(2) @(posedge clk); + count_tx = count_tx + 1; + @(posedge clk); + end + end + begin + // Recieve 80 packets + repeat(80) begin + receive_raw_packet(count_rx,status); + status = status || fail; + repeat(2) @(posedge clk); + count_rx = count_rx + 1; + @(posedge clk); + if (status !== 0) begin + repeat(100) @(posedge clk); + $display("FAILED."); + $finish; + end + end + end + join + // Now single threaded agian. + repeat(100) @(posedge clk); + + $display; + // Should not be able to get to here with FAIL status but check anyhow + if (status != 0) + $display("FAILED."); + else + $display("PASSED."); + + @(posedge clk); + $finish; + + end + + //initial + // o_tready = 1; + diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/Default.wcfg b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/Default.wcfg new file mode 100644 index 000000000..3e6d96fb4 --- /dev/null +++ b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/Default.wcfg @@ -0,0 +1,388 @@ +<?xml version="1.0" encoding="UTF-8"?> +<wave_config> + <wave_state> + </wave_state> + <db_ref_list> + <db_ref path="./isim.wdb" id="1" type="auto"> + <top_modules> + <top_module name="axi_dram_fifo_tb" /> + <top_module name="glbl" /> + </top_modules> + </db_ref> + </db_ref_list> + <WVObjectSize size="14" /> + <wave_markers> + <marker time="31415100000" label="" /> + <marker time="30385518000" label="" /> + <marker time="23065100000" label="" /> + <marker time="18355382000" label="" /> + </wave_markers> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/clk" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">clk</obj_property> + <obj_property name="ObjectShortName">clk</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/reset" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">reset</obj_property> + <obj_property name="ObjectShortName">reset</obj_property> + </wvobject> + <wvobject fp_name="group31" type="group"> + <obj_property name="label">chdr_test_pattern</obj_property> + <obj_property name="DisplayName">label</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/start" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">start</obj_property> + <obj_property name="ObjectShortName">start</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/i_tdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">i_tdata[63:0]</obj_property> + <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/i_tlast" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">i_tlast</obj_property> + <obj_property name="ObjectShortName">i_tlast</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/i_tvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">i_tvalid</obj_property> + <obj_property name="ObjectShortName">i_tvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/i_tready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">i_tready</obj_property> + <obj_property name="ObjectShortName">i_tready</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/o_tdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">o_tdata[63:0]</obj_property> + <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/o_tlast" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tlast</obj_property> + <obj_property name="ObjectShortName">o_tlast</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/o_tready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tready</obj_property> + <obj_property name="ObjectShortName">o_tready</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/o_tvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tvalid</obj_property> + <obj_property name="ObjectShortName">o_tvalid</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="group11" type="group"> + <obj_property name="label">embed_tlast</obj_property> + <obj_property name="DisplayName">label</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/i_tdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">i_tdata[63:0]</obj_property> + <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/i_tlast" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">i_tlast</obj_property> + <obj_property name="ObjectShortName">i_tlast</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/i_tvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">i_tvalid</obj_property> + <obj_property name="ObjectShortName">i_tvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/i_tready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">i_tready</obj_property> + <obj_property name="ObjectShortName">i_tready</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/o_tdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">o_tdata[63:0]</obj_property> + <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/o_tvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tvalid</obj_property> + <obj_property name="ObjectShortName">o_tvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/o_tready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tready</obj_property> + <obj_property name="ObjectShortName">o_tready</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/state" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">state[1:0]</obj_property> + <obj_property name="ObjectShortName">state[1:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="group18" type="group"> + <obj_property name="label">fast_fifo_i0</obj_property> + <obj_property name="DisplayName">label</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/state" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">state[1:0]</obj_property> + <obj_property name="ObjectShortName">state[1:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/i_tdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">i_tdata[63:0]</obj_property> + <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/i_tvalid" type="logic" db_ref_id="1"> + <obj_property name="DisplayName">FullPathName</obj_property> + <obj_property name="ElementShortName">i_tvalid</obj_property> + <obj_property name="ObjectShortName">i_tvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/i_tready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">i_tready</obj_property> + <obj_property name="ObjectShortName">i_tready</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/o_tdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">o_tdata[63:0]</obj_property> + <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/o_tvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tvalid</obj_property> + <obj_property name="ObjectShortName">o_tvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/o_tready" type="logic" db_ref_id="1"> + <obj_property name="DisplayName">label</obj_property> + <obj_property name="ElementShortName">o_tready</obj_property> + <obj_property name="ObjectShortName">o_tready</obj_property> + <obj_property name="label">o_tready</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="group25" type="group"> + <obj_property name="label">fifo_i1</obj_property> + <obj_property name="DisplayName">label</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i1/i_tdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">i_tdata[63:0]</obj_property> + <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i1/i_tvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">i_tvalid</obj_property> + <obj_property name="ObjectShortName">i_tvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i1/i_tready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">i_tready</obj_property> + <obj_property name="ObjectShortName">i_tready</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i1/o_tdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">o_tdata[63:0]</obj_property> + <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i1/o_tvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tvalid</obj_property> + <obj_property name="ObjectShortName">o_tvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i1/o_tready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tready</obj_property> + <obj_property name="ObjectShortName">o_tready</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="group79" type="group"> + <obj_property name="label">AXI write bus</obj_property> + <obj_property name="DisplayName">label</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_awaddr" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">axi_awaddr[31:0]</obj_property> + <obj_property name="ObjectShortName">axi_awaddr[31:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_awlen" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">axi_awlen[7:0]</obj_property> + <obj_property name="ObjectShortName">axi_awlen[7:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_awvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">axi_awvalid</obj_property> + <obj_property name="ObjectShortName">axi_awvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_awready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">axi_awready</obj_property> + <obj_property name="ObjectShortName">axi_awready</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_wdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">axi_wdata[63:0]</obj_property> + <obj_property name="ObjectShortName">axi_wdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_wvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">axi_wvalid</obj_property> + <obj_property name="ObjectShortName">axi_wvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_wready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">axi_wready</obj_property> + <obj_property name="ObjectShortName">axi_wready</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_bvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">axi_bvalid</obj_property> + <obj_property name="ObjectShortName">axi_bvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_bready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">axi_bready</obj_property> + <obj_property name="ObjectShortName">axi_bready</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/space" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">space[10:0]</obj_property> + <obj_property name="ObjectShortName">space[10:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/occupied" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">occupied[10:0]</obj_property> + <obj_property name="ObjectShortName">occupied[10:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="group71" type="group"> + <obj_property name="label">AXI read bus</obj_property> + <obj_property name="DisplayName">label</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_araddr" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_araddr[31:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_araddr[31:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arlen" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_arlen[7:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_arlen[7:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_arvalid</obj_property> + <obj_property name="ObjectShortName">m_axi_arvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_arready</obj_property> + <obj_property name="ObjectShortName">m_axi_arready</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_rdata[63:0]</obj_property> + <obj_property name="ObjectShortName">m_axi_rdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_rvalid</obj_property> + <obj_property name="ObjectShortName">m_axi_rvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">m_axi_rready</obj_property> + <obj_property name="ObjectShortName">m_axi_rready</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="group43" type="group"> + <obj_property name="label">fifo_i2</obj_property> + <obj_property name="DisplayName">label</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i2/i_tdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">i_tdata[63:0]</obj_property> + <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i2/i_tvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">i_tvalid</obj_property> + <obj_property name="ObjectShortName">i_tvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i2/i_tready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">i_tready</obj_property> + <obj_property name="ObjectShortName">i_tready</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i2/o_tdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">o_tdata[63:0]</obj_property> + <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i2/o_tvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tvalid</obj_property> + <obj_property name="ObjectShortName">o_tvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i2/o_tready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tready</obj_property> + <obj_property name="ObjectShortName">o_tready</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="group50" type="group"> + <obj_property name="label">fast_fifo_i1</obj_property> + <obj_property name="DisplayName">label</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i1/i_tdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">i_tdata[63:0]</obj_property> + <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i1/i_tvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">i_tvalid</obj_property> + <obj_property name="ObjectShortName">i_tvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i1/i_tready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">i_tready</obj_property> + <obj_property name="ObjectShortName">i_tready</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i1/o_tdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">o_tdata[63:0]</obj_property> + <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i1/o_tready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tready</obj_property> + <obj_property name="ObjectShortName">o_tready</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i1/o_tvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tvalid</obj_property> + <obj_property name="ObjectShortName">o_tvalid</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="group58" type="group"> + <obj_property name="label">axi_fast_extract</obj_property> + <obj_property name="DisplayName">label</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/i_tdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">i_tdata[63:0]</obj_property> + <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/i_tvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">i_tvalid</obj_property> + <obj_property name="ObjectShortName">i_tvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/i_tready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">i_tready</obj_property> + <obj_property name="ObjectShortName">i_tready</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/o_tdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">o_tdata[63:0]</obj_property> + <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/o_tlast" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tlast</obj_property> + <obj_property name="ObjectShortName">o_tlast</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/o_tready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tready</obj_property> + <obj_property name="ObjectShortName">o_tready</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/o_tvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tvalid</obj_property> + <obj_property name="ObjectShortName">o_tvalid</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="group63" type="group"> + <obj_property name="label">dram_fifo_output</obj_property> + <obj_property name="DisplayName">label</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">o_tdata[63:0]</obj_property> + <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tlast" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tlast</obj_property> + <obj_property name="ObjectShortName">o_tlast</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tvalid</obj_property> + <obj_property name="ObjectShortName">o_tvalid</obj_property> + </wvobject> + <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">o_tready</obj_property> + <obj_property name="ObjectShortName">o_tready</obj_property> + </wvobject> + </wvobject> +</wave_config> diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim new file mode 100755 index 000000000..46141fcae --- /dev/null +++ b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim @@ -0,0 +1,19 @@ +/bin/rm -r isim + +vlogcomp -work work ${XILINX}/verilog/src/glbl.v + +vlogcomp -work work --sourcelibext .v \ + --sourcelibdir ../../../lib/axi \ + --sourcelibdir ../../../lib/fifo \ + --sourcelibdir ../../../lib/control \ + --sourcelibdir ../../../top/x300/coregen \ + ../../../lib/axi/axi_dram_fifo_tb.v + + + +fuse work.axi_dram_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_dram_fifo_tb.exe + +# run the simulation scrip +./axi_dram_fifo_tb.exe -gui #-tclbatch simcmds.tcl + + diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/simulation_script.v b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/simulation_script.v new file mode 100644 index 000000000..4a94820b7 --- /dev/null +++ b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/simulation_script.v @@ -0,0 +1,91 @@ +wire fail; +wire done; +reg start; +reg [15:0] control; + + + +axi_chdr_test_pattern axi_chdr_test_pattern_i + ( + .clk(clk), + .reset(reset), + + // + // CHDR friendly AXI stream input + // + .i_tdata(i_tdata), + .i_tlast(i_tlast), + .i_tvalid(i_tvalid), + .i_tready(i_tready), + // + // CHDR friendly AXI Stream output + // + .o_tdata(o_tdata), + .o_tlast(o_tlast), + .o_tvalid(o_tvalid), + .o_tready(o_tready), + // + // Test flags + // + .start(start), + .fail(fail), + .done(done), + .control(control) + ); + + + always + #5 clk <= ~clk; + + initial + begin + clk <= 1'b0; + reset <= 1'b0; + clear <= 1'b0; + start <= 1'b0; + control <= 16'h0101; + + + @(negedge clk); + reset <= 1'b1; + repeat(10) @(negedge clk); + reset <= 1'b0; + repeat(10) @(negedge clk); + // Now activate BIST + start <= 1'b1; + + // Wait until simulation is done. + while(!done) + @(negedge clk); + + $display; + + if (fail) + $display("FAILED."); + else + $display("Done 1st pass."); + + @(posedge clk); + start <= 1'b0; + repeat(10) @(negedge clk); + // Now activate BIST + start <= 1'b1; + + // Wait until simulation is done. + while(!done) + @(negedge clk); + + $display; + + if (fail) + $display("FAILED."); + else + $display("PASSED."); + + $finish; + + end + + //initial + // o_tready = 1; + |