From ff1546f8137f7f92bb250f685561b0c34cc0e053 Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Fri, 14 Feb 2014 12:05:07 -0800 Subject: Pushing the bulk of UHD-3.7.0 code. --- .../sim/axi_dram_fifo/sim_sram_1/default.wcfg | 412 +++++++++++++++++++++ fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/run_isim | 17 + .../axi_dram_fifo/sim_sram_1/simulation_script.v | 113 ++++++ .../sim/axi_dram_fifo/sim_sram_2/Default.wcfg | 388 +++++++++++++++++++ fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim | 19 + .../axi_dram_fifo/sim_sram_2/simulation_script.v | 91 +++++ 6 files changed, 1040 insertions(+) create mode 100644 fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/default.wcfg create mode 100755 fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/run_isim create mode 100644 fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/simulation_script.v create mode 100644 fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/Default.wcfg create mode 100755 fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim create mode 100644 fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/simulation_script.v (limited to 'fpga/usrp3/sim/axi_dram_fifo') diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/default.wcfg b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/default.wcfg new file mode 100644 index 000000000..796071597 --- /dev/null +++ b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/default.wcfg @@ -0,0 +1,412 @@ + + + + + + + + + + + + + + + clk + clk + + + reset + reset + + + clear + clear + + + count_rx[31:0] + count_rx[31:0] + HEXRADIX + + + count_tx[31:0] + count_tx[31:0] + HEXRADIX + + + i_tdata[63:0] + i_tdata[63:0] + HEXRADIX + + + i_tlast + i_tlast + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + input_state[2:0] + input_state[2:0] + HEXRADIX + + + write_ctrl_ready + write_ctrl_ready + + + write_ctrl_valid + write_ctrl_valid + + + occupied_input[5:0] + occupied_input[5:0] + HEXRADIX + + + INPUT TIMEOUT + label + + input_timeout_count[7:0] + input_timeout_count[7:0] + + + input_timeout_reset + input_timeout_reset + + + input_timeout_triggered + input_timeout_triggered + + + + AXI_WADDR + label + + write_addr_state[1:0] + write_addr_state[1:0] + HEXRADIX + true + #ffff00 + + + m_axi_awid[0:0] + m_axi_awid[0:0] + HEXRADIX + + + m_axi_awaddr[31:0] + m_axi_awaddr[31:0] + HEXRADIX + + + m_axi_awlen[7:0] + m_axi_awlen[7:0] + HEXRADIX + + + m_axi_awsize[2:0] + m_axi_awsize[2:0] + HEXRADIX + + + m_axi_awburst[1:0] + m_axi_awburst[1:0] + HEXRADIX + + + m_axi_awvalid + m_axi_awvalid + + + m_axi_awready + m_axi_awready + + + + write_data_count[3:0] + write_data_count[3:0] + HEXRADIX + + + AXI_WDATA + label + + m_axi_wdata[63:0] + m_axi_wdata[63:0] + HEXRADIX + + + m_axi_wstrb[7:0] + m_axi_wstrb[7:0] + HEXRADIX + + + m_axi_wlast + m_axi_wlast + + + m_axi_wvalid + m_axi_wvalid + + + m_axi_wready + m_axi_wready + + + + AXI_WRESP + label + + m_axi_bid[0:0] + m_axi_bid[0:0] + HEXRADIX + + + m_axi_bresp[1:0] + m_axi_bresp[1:0] + HEXRADIX + + + m_axi_bvalid + m_axi_bvalid + + + m_axi_bready + m_axi_bready + true + #00ff00 + /axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bready + + + + space[10:0] + space[10:0] + HEXRADIX + + + occupied[10:0] + occupied[10:0] + HEXRADIX + true + #00ffff + + + AXI_RADDR + label + + read_addr_state[1:0] + read_addr_state[1:0] + HEXRADIX + true + #ffff00 + + + m_axi_arid[0:0] + m_axi_arid[0:0] + HEXRADIX + + + m_axi_araddr[31:0] + m_axi_araddr[31:0] + HEXRADIX + + + m_axi_arlen[7:0] + m_axi_arlen[7:0] + HEXRADIX + + + m_axi_arsize[2:0] + m_axi_arsize[2:0] + HEXRADIX + + + m_axi_arburst[1:0] + m_axi_arburst[1:0] + HEXRADIX + + + m_axi_arvalid + m_axi_arvalid + + + m_axi_arready + m_axi_arready + + + + AXI_RDATA + label + + read_data_state[1:0] + read_data_state[1:0] + HEXRADIX + true + #ffff00 + + + m_axi_rid[0:0] + m_axi_rid[0:0] + HEXRADIX + + + m_axi_rdata[63:0] + m_axi_rdata[63:0] + HEXRADIX + + + m_axi_rresp[1:0] + m_axi_rresp[1:0] + HEXRADIX + + + m_axi_rlast + m_axi_rlast + + + m_axi_rvalid + m_axi_rvalid + + + m_axi_rready + m_axi_rready + + + + read_ctrl_valid + read_ctrl_valid + true + #ffff00 + + + read_ctrl_ready + read_ctrl_ready + + + read_data_count[3:0] + read_data_count[3:0] + HEXRADIX + + + output_state[2:0] + output_state[2:0] + HEXRADIX + + + space_output[5:0] + space_output[5:0] + HEXRADIX + + + DRAM FIFO OUT + label + + o_tdata_output[63:0] + o_tdata_output[63:0] + HEXRADIX + + + o_tvalid_output + o_tvalid_output + + + o_tready_output + o_tready_output + + + + update_write + update_write + true + #ff00ff + + + write_count[3:0] + write_count[3:0] + HEXRADIX + + + update_read + update_read + true + #ff00ff + + + read_count[3:0] + read_count[3:0] + HEXRADIX + + + Output TImeout + label + + output_timeout_count[7:0] + output_timeout_count[7:0] + + + output_timeout_reset + output_timeout_reset + + + output_timeout_triggered + output_timeout_triggered + + + + Extract TLAST + label + + o_tdata_i0[63:0] + o_tdata_i0[63:0] + HEXRADIX + + + o_tvalid_i0 + o_tvalid_i0 + + + o_tready_i0 + o_tready_i0 + + + o_tdata_i1[63:0] + o_tdata_i1[63:0] + HEXRADIX + + + o_tvalid_i1 + o_tvalid_i1 + + + o_tready_i1 + o_tready_i1 + + + o_tlast_i1 + o_tlast_i1 + + + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tlast + o_tlast + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/run_isim b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/run_isim new file mode 100755 index 000000000..03eead1f7 --- /dev/null +++ b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/run_isim @@ -0,0 +1,17 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +#vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../packet_proc/source_flow_control_tb.v +vlogcomp -work work --sourcelibext .v \ + --sourcelibdir ../../../lib/axi \ + --sourcelibdir ../../../lib/fifo \ + --sourcelibdir ../../../lib/control \ + --sourcelibdir ../../../top/x300/coregen \ + ../../../lib/axi/axi_dram_fifo_tb.v + + + +fuse work.axi_dram_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_dram_fifo_tb.exe + +# run the simulation scrip +./axi_dram_fifo_tb.exe # -gui #-tclbatch simcmds.tcl + + diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/simulation_script.v b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/simulation_script.v new file mode 100644 index 000000000..eb72da360 --- /dev/null +++ b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/simulation_script.v @@ -0,0 +1,113 @@ +reg [31:0] count_rx, count_tx; +reg status; +reg fail; + + +// +// Use task library +// +`define USE_TASKS + + initial + begin + clk <= 1'b0; + reset <= 1'b0; + clear <= 1'b0; + i_tdata_r <= 0; + i_tlast_r <= 0; + i_tvalid_r <= 0; + o_tready_r <= 0; + end + + always + #5 clk <= ~clk; + + initial + begin + count_tx = 2; + count_rx = 2; + status = 0; + + + @(negedge clk); + reset <= 1'b1; + repeat(10) @(negedge clk); + reset <= 1'b0; + repeat(10) @(negedge clk); + + // Send 40 packets. + repeat(40) begin + send_raw_packet(count_tx); + repeat(2) @(posedge clk); + count_tx = count_tx + 1; + @(posedge clk); + end + repeat(100) @(posedge clk); + + + // Recieve 40 packets + repeat(40) begin + receive_raw_packet(count_rx,fail); + status = status || fail; + repeat(2) @(posedge clk); + count_rx = count_rx + 1; + @(posedge clk); + end + repeat(100) @(posedge clk); + + count_tx = 2; + count_rx = 2; + + // Send 40 packets. + repeat(40) begin + send_raw_packet(count_tx); + repeat(2) @(posedge clk); + count_tx = count_tx + 1; + @(posedge clk); + end + repeat(100) @(posedge clk); + // Now fork so send and receive run concurrently + fork + begin + // Send 40 packets. + repeat(40) begin + send_raw_packet(count_tx); + repeat(2) @(posedge clk); + count_tx = count_tx + 1; + @(posedge clk); + end + end + begin + // Recieve 80 packets + repeat(80) begin + receive_raw_packet(count_rx,status); + status = status || fail; + repeat(2) @(posedge clk); + count_rx = count_rx + 1; + @(posedge clk); + if (status !== 0) begin + repeat(100) @(posedge clk); + $display("FAILED."); + $finish; + end + end + end + join + // Now single threaded agian. + repeat(100) @(posedge clk); + + $display; + // Should not be able to get to here with FAIL status but check anyhow + if (status != 0) + $display("FAILED."); + else + $display("PASSED."); + + @(posedge clk); + $finish; + + end + + //initial + // o_tready = 1; + diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/Default.wcfg b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/Default.wcfg new file mode 100644 index 000000000..3e6d96fb4 --- /dev/null +++ b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/Default.wcfg @@ -0,0 +1,388 @@ + + + + + + + + + + + + + + + + + + + + + clk + clk + + + reset + reset + + + chdr_test_pattern + label + HEXRADIX + + start + start + + + i_tdata[63:0] + i_tdata[63:0] + HEXRADIX + + + i_tlast + i_tlast + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tlast + o_tlast + + + o_tready + o_tready + + + o_tvalid + o_tvalid + + + + embed_tlast + label + HEXRADIX + + i_tdata[63:0] + i_tdata[63:0] + HEXRADIX + + + i_tlast + i_tlast + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + state[1:0] + state[1:0] + HEXRADIX + + + + fast_fifo_i0 + label + HEXRADIX + + state[1:0] + state[1:0] + HEXRADIX + + + i_tdata[63:0] + i_tdata[63:0] + HEXRADIX + + + FullPathName + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + label + o_tready + o_tready + o_tready + + + + fifo_i1 + label + HEXRADIX + + i_tdata[63:0] + i_tdata[63:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + + AXI write bus + label + + axi_awaddr[31:0] + axi_awaddr[31:0] + HEXRADIX + + + axi_awlen[7:0] + axi_awlen[7:0] + HEXRADIX + + + axi_awvalid + axi_awvalid + + + axi_awready + axi_awready + + + axi_wdata[63:0] + axi_wdata[63:0] + HEXRADIX + + + axi_wvalid + axi_wvalid + + + axi_wready + axi_wready + + + axi_bvalid + axi_bvalid + + + axi_bready + axi_bready + + + + space[10:0] + space[10:0] + HEXRADIX + + + occupied[10:0] + occupied[10:0] + HEXRADIX + + + AXI read bus + label + HEXRADIX + + m_axi_araddr[31:0] + m_axi_araddr[31:0] + HEXRADIX + + + m_axi_arlen[7:0] + m_axi_arlen[7:0] + HEXRADIX + + + m_axi_arvalid + m_axi_arvalid + + + m_axi_arready + m_axi_arready + + + m_axi_rdata[63:0] + m_axi_rdata[63:0] + HEXRADIX + + + m_axi_rvalid + m_axi_rvalid + + + m_axi_rready + m_axi_rready + + + + fifo_i2 + label + + i_tdata[63:0] + i_tdata[63:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + + fast_fifo_i1 + label + HEXRADIX + + i_tdata[63:0] + i_tdata[63:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tready + o_tready + + + o_tvalid + o_tvalid + + + + axi_fast_extract + label + HEXRADIX + + i_tdata[63:0] + i_tdata[63:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tlast + o_tlast + + + o_tready + o_tready + + + o_tvalid + o_tvalid + + + + dram_fifo_output + label + HEXRADIX + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tlast + o_tlast + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim new file mode 100755 index 000000000..46141fcae --- /dev/null +++ b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim @@ -0,0 +1,19 @@ +/bin/rm -r isim + +vlogcomp -work work ${XILINX}/verilog/src/glbl.v + +vlogcomp -work work --sourcelibext .v \ + --sourcelibdir ../../../lib/axi \ + --sourcelibdir ../../../lib/fifo \ + --sourcelibdir ../../../lib/control \ + --sourcelibdir ../../../top/x300/coregen \ + ../../../lib/axi/axi_dram_fifo_tb.v + + + +fuse work.axi_dram_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_dram_fifo_tb.exe + +# run the simulation scrip +./axi_dram_fifo_tb.exe -gui #-tclbatch simcmds.tcl + + diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/simulation_script.v b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/simulation_script.v new file mode 100644 index 000000000..4a94820b7 --- /dev/null +++ b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/simulation_script.v @@ -0,0 +1,91 @@ +wire fail; +wire done; +reg start; +reg [15:0] control; + + + +axi_chdr_test_pattern axi_chdr_test_pattern_i + ( + .clk(clk), + .reset(reset), + + // + // CHDR friendly AXI stream input + // + .i_tdata(i_tdata), + .i_tlast(i_tlast), + .i_tvalid(i_tvalid), + .i_tready(i_tready), + // + // CHDR friendly AXI Stream output + // + .o_tdata(o_tdata), + .o_tlast(o_tlast), + .o_tvalid(o_tvalid), + .o_tready(o_tready), + // + // Test flags + // + .start(start), + .fail(fail), + .done(done), + .control(control) + ); + + + always + #5 clk <= ~clk; + + initial + begin + clk <= 1'b0; + reset <= 1'b0; + clear <= 1'b0; + start <= 1'b0; + control <= 16'h0101; + + + @(negedge clk); + reset <= 1'b1; + repeat(10) @(negedge clk); + reset <= 1'b0; + repeat(10) @(negedge clk); + // Now activate BIST + start <= 1'b1; + + // Wait until simulation is done. + while(!done) + @(negedge clk); + + $display; + + if (fail) + $display("FAILED."); + else + $display("Done 1st pass."); + + @(posedge clk); + start <= 1'b0; + repeat(10) @(negedge clk); + // Now activate BIST + start <= 1'b1; + + // Wait until simulation is done. + while(!done) + @(negedge clk); + + $display; + + if (fail) + $display("FAILED."); + else + $display("PASSED."); + + $finish; + + end + + //initial + // o_tready = 1; + -- cgit v1.2.3