Removed copy of FPGA source files.

4 files changed, 0 insertions, 360 deletions

diff --git a/fpga/usrp3/sim/axi_crossbar/sim_2x2/default.wcfg b/fpga/usrp3/sim/axi_crossbar/sim_2x2/default.wcfg
deleted file mode 100644
index f52bcc090..000000000
--- a/fpga/usrp3/sim/axi_crossbar/sim_2x2/default.wcfg
+++ /dev/null
@@ -1,188 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<wave_config>
-   <wave_state>
-   </wave_state>
-   <db_ref_list>
-      <db_ref path="./isim.wdb" id="1" type="auto">
-         <top_modules>
-            <top_module name="axi_crossbar_tb" />
-            <top_module name="glbl" />
-         </top_modules>
-      </db_ref>
-   </db_ref_list>
-   <WVObjectSize size="11" />
-   <wvobject fp_name="/axi_crossbar_tb/clk" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">clk</obj_property>
-      <obj_property name="ObjectShortName">clk</obj_property>
-   </wvobject>
-   <wvobject fp_name="/axi_crossbar_tb/reset" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">reset</obj_property>
-      <obj_property name="ObjectShortName">reset</obj_property>
-   </wvobject>
-   <wvobject fp_name="/axi_crossbar_tb/set_stb" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">set_stb</obj_property>
-      <obj_property name="ObjectShortName">set_stb</obj_property>
-   </wvobject>
-   <wvobject fp_name="/axi_crossbar_tb/set_addr" type="array" db_ref_id="1">
-      <obj_property name="ElementShortName">set_addr[15:0]</obj_property>
-      <obj_property name="ObjectShortName">set_addr[15:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-   </wvobject>
-   <wvobject fp_name="/axi_crossbar_tb/set_data" type="array" db_ref_id="1">
-      <obj_property name="ElementShortName">set_data[31:0]</obj_property>
-      <obj_property name="ObjectShortName">set_data[31:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-   </wvobject>
-   <wvobject fp_name="/axi_crossbar_tb/local_addr" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">local_addr</obj_property>
-      <obj_property name="ObjectShortName">local_addr</obj_property>
-   </wvobject>
-   <wvobject fp_name="divider67" type="divider">
-      <obj_property name="label">New Divider</obj_property>
-      <obj_property name="DisplayName">label</obj_property>
-      <obj_property name="BkColor">128 128 255</obj_property>
-      <obj_property name="TextColor">230 230 230</obj_property>
-   </wvobject>
-   <wvobject fp_name="group6" type="group">
-      <obj_property name="label">Input Port 0</obj_property>
-      <obj_property name="DisplayName">label</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[0].axi_fifo_short_in /i_tdata" type="array" db_ref_id="1">
-         <obj_property name="ElementShortName">i_tdata[64:0]</obj_property>
-         <obj_property name="ObjectShortName">i_tdata[64:0]</obj_property>
-         <obj_property name="Radix">HEXRADIX</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[0].axi_fifo_short_in /i_tvalid" type="logic" db_ref_id="1">
-         <obj_property name="ElementShortName">i_tvalid</obj_property>
-         <obj_property name="ObjectShortName">i_tvalid</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[0].axi_fifo_short_in /i_tready" type="logic" db_ref_id="1">
-         <obj_property name="ElementShortName">i_tready</obj_property>
-         <obj_property name="ObjectShortName">i_tready</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[0].axi_fifo_short_in /o_tdata" type="array" db_ref_id="1">
-         <obj_property name="ElementShortName">o_tdata[64:0]</obj_property>
-         <obj_property name="ObjectShortName">o_tdata[64:0]</obj_property>
-         <obj_property name="Radix">HEXRADIX</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[0].axi_fifo_short_in /o_tvalid" type="logic" db_ref_id="1">
-         <obj_property name="ElementShortName">o_tvalid</obj_property>
-         <obj_property name="ObjectShortName">o_tvalid</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[0].axi_fifo_short_in /o_tready" type="logic" db_ref_id="1">
-         <obj_property name="ElementShortName">o_tready</obj_property>
-         <obj_property name="ObjectShortName">o_tready</obj_property>
-      </wvobject>
-      <wvobject fp_name="divider64" type="divider">
-         <obj_property name="label">New Divider</obj_property>
-         <obj_property name="DisplayName">label</obj_property>
-         <obj_property name="BkColor">128 128 255</obj_property>
-         <obj_property name="TextColor">230 230 230</obj_property>
-      </wvobject>
-   </wvobject>
-   <wvobject fp_name="group10" type="group">
-      <obj_property name="label">Input Port 1</obj_property>
-      <obj_property name="DisplayName">label</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[1].axi_fifo_short_in /i_tdata" type="array" db_ref_id="1">
-         <obj_property name="ElementShortName">i_tdata[64:0]</obj_property>
-         <obj_property name="ObjectShortName">i_tdata[64:0]</obj_property>
-         <obj_property name="Radix">HEXRADIX</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[1].axi_fifo_short_in /i_tvalid" type="logic" db_ref_id="1">
-         <obj_property name="ElementShortName">i_tvalid</obj_property>
-         <obj_property name="ObjectShortName">i_tvalid</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[1].axi_fifo_short_in /i_tready" type="logic" db_ref_id="1">
-         <obj_property name="ElementShortName">i_tready</obj_property>
-         <obj_property name="ObjectShortName">i_tready</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[1].axi_fifo_short_in /o_tdata" type="array" db_ref_id="1">
-         <obj_property name="ElementShortName">o_tdata[64:0]</obj_property>
-         <obj_property name="ObjectShortName">o_tdata[64:0]</obj_property>
-         <obj_property name="Radix">HEXRADIX</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[1].axi_fifo_short_in /o_tvalid" type="logic" db_ref_id="1">
-         <obj_property name="ElementShortName">o_tvalid</obj_property>
-         <obj_property name="ObjectShortName">o_tvalid</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[1].axi_fifo_short_in /o_tready" type="logic" db_ref_id="1">
-         <obj_property name="ElementShortName">o_tready</obj_property>
-         <obj_property name="ObjectShortName">o_tready</obj_property>
-      </wvobject>
-      <wvobject fp_name="divider65" type="divider">
-         <obj_property name="label">New Divider</obj_property>
-         <obj_property name="DisplayName">label</obj_property>
-         <obj_property name="BkColor">128 128 255</obj_property>
-         <obj_property name="TextColor">230 230 230</obj_property>
-      </wvobject>
-   </wvobject>
-   <wvobject fp_name="group14" type="group">
-      <obj_property name="label">Output Port 0</obj_property>
-      <obj_property name="DisplayName">label</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[0].axi_fifo_short_out /i_tdata" type="array" db_ref_id="1">
-         <obj_property name="ElementShortName">i_tdata[64:0]</obj_property>
-         <obj_property name="ObjectShortName">i_tdata[64:0]</obj_property>
-         <obj_property name="Radix">HEXRADIX</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[0].axi_fifo_short_out /i_tvalid" type="logic" db_ref_id="1">
-         <obj_property name="ElementShortName">i_tvalid</obj_property>
-         <obj_property name="ObjectShortName">i_tvalid</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[0].axi_fifo_short_out /i_tready" type="logic" db_ref_id="1">
-         <obj_property name="ElementShortName">i_tready</obj_property>
-         <obj_property name="ObjectShortName">i_tready</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[0].axi_fifo_short_out /o_tdata" type="array" db_ref_id="1">
-         <obj_property name="ElementShortName">o_tdata[64:0]</obj_property>
-         <obj_property name="ObjectShortName">o_tdata[64:0]</obj_property>
-         <obj_property name="Radix">HEXRADIX</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[0].axi_fifo_short_out /o_tvalid" type="logic" db_ref_id="1">
-         <obj_property name="ElementShortName">o_tvalid</obj_property>
-         <obj_property name="ObjectShortName">o_tvalid</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[0].axi_fifo_short_out /o_tready" type="logic" db_ref_id="1">
-         <obj_property name="ElementShortName">o_tready</obj_property>
-         <obj_property name="ObjectShortName">o_tready</obj_property>
-      </wvobject>
-      <wvobject fp_name="divider66" type="divider">
-         <obj_property name="label">New Divider</obj_property>
-         <obj_property name="DisplayName">label</obj_property>
-         <obj_property name="BkColor">128 128 255</obj_property>
-         <obj_property name="TextColor">230 230 230</obj_property>
-      </wvobject>
-   </wvobject>
-   <wvobject fp_name="group18" type="group">
-      <obj_property name="label">Output Port 1</obj_property>
-      <obj_property name="DisplayName">label</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[1].axi_fifo_short_out /i_tdata" type="array" db_ref_id="1">
-         <obj_property name="ElementShortName">i_tdata[64:0]</obj_property>
-         <obj_property name="ObjectShortName">i_tdata[64:0]</obj_property>
-         <obj_property name="Radix">HEXRADIX</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[1].axi_fifo_short_out /i_tvalid" type="logic" db_ref_id="1">
-         <obj_property name="ElementShortName">i_tvalid</obj_property>
-         <obj_property name="ObjectShortName">i_tvalid</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[1].axi_fifo_short_out /i_tready" type="logic" db_ref_id="1">
-         <obj_property name="ElementShortName">i_tready</obj_property>
-         <obj_property name="ObjectShortName">i_tready</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[1].axi_fifo_short_out /o_tdata" type="array" db_ref_id="1">
-         <obj_property name="ElementShortName">o_tdata[64:0]</obj_property>
-         <obj_property name="ObjectShortName">o_tdata[64:0]</obj_property>
-         <obj_property name="Radix">HEXRADIX</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[1].axi_fifo_short_out /o_tvalid" type="logic" db_ref_id="1">
-         <obj_property name="ElementShortName">o_tvalid</obj_property>
-         <obj_property name="ObjectShortName">o_tvalid</obj_property>
-      </wvobject>
-      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[1].axi_fifo_short_out /o_tready" type="logic" db_ref_id="1">
-         <obj_property name="ElementShortName">o_tready</obj_property>
-         <obj_property name="ObjectShortName">o_tready</obj_property>
-      </wvobject>
-   </wvobject>
-</wave_config>
diff --git a/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_isim b/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_isim
deleted file mode 100755
index 6c3fde52c..000000000
--- a/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_isim
+++ /dev/null
@@ -1,15 +0,0 @@
-vlogcomp -work work ${XILINX}/verilog/src/glbl.v
-vlogcomp -i ../.. -work work ../../../lib/control/axi_crossbar_tb.v
-vlogcomp -work work ../../../lib/control/axi_crossbar.v
-vlogcomp -work work ../../../lib/control/axi_slave_mux.v
-vlogcomp -work work ../../../lib/control/axi_forwarding_cam.v
-vlogcomp -work work ../../../lib/control/setting_reg.v
-vlogcomp -work work ../../../lib/fifo/monitor_axi_fifo.v
-vlogcomp -work work ../../../lib/fifo/axi_fifo_short.v
-
-
-
-fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe
-
-# run the simulation scrip
-./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl
diff --git a/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_iverilog b/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_iverilog
deleted file mode 100755
index 268127de8..000000000
--- a/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_iverilog
+++ /dev/null
@@ -1,21 +0,0 @@
-
-iverilog \
--s axi_crossbar_tb \
--y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims \
--o axi_crossbar_tb \
--I .. \
-/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/glbl.v \
-../../lib/control/axi_crossbar_tb.v \
-../../lib/control/axi_crossbar.v \
-../../lib/control/axi_slave_mux.v \
-../../lib/control/axi_forwarding_cam.v \
-../../lib/control/setting_reg.v \
-../../lib/fifo/monitor_axi_fifo.v \
-../../lib/fifo/axi_fifo_short.v
-
-
-
-#fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe
-
-# run the simulation scrip
-#./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl
diff --git a/fpga/usrp3/sim/axi_crossbar/sim_2x2/simulation_script.v b/fpga/usrp3/sim/axi_crossbar/sim_2x2/simulation_script.v
deleted file mode 100644
index da0213c72..000000000
--- a/fpga/usrp3/sim/axi_crossbar/sim_2x2/simulation_script.v
+++ /dev/null
@@ -1,136 +0,0 @@
-// Simulate a 2x2 switch configuration
-localparam NUM_INPUTS = 2;
-localparam NUM_OUTPUTS = 2;
-
-//initial $dumpfile("axi_crossbar_tb.vcd");
-//initial $dumpvars(0,axi_crossbar_tb);
-
-reg [15:0] x;
-reg [31:0] seq_i0, seq_i1, seq_o0, seq_o1;
-
-
-/////////////////////////////////////////////
-//
-// Control and input data thread.
-//
-/////////////////////////////////////////////
-initial
-  begin
-     @(posedge clk);
-     reset <= 1;
-     repeat (5) @(posedge clk);
-     @(posedge clk);
-     reset <= 0;
-     @(posedge clk);
-     // 2x2 Switch so only mask one bit of SID for route dest.
-     // Each slave must have a unique address, logic doesn't check for this.
-     //
-     // Network Addr 0 & 1 go to Slave 0.
-     write_setting_bus(0,0);   // 0.X goes to Port 0
-     write_setting_bus(1,0);   // 1.X goes to Port 0
-     // Local Addr = 2
-     write_setting_bus(512,2);
-     // Host Addr 0 & 2 go to Slave 0...
-     write_setting_bus(256,0); // 2.0 goes to Port 0
-     write_setting_bus(258,0); // 2.2 goes to Port 0
-     // ...Host Addr 1 & 3 go to Slave 1...
-     write_setting_bus(257,1); // 2.1 goes to Port 1
-     write_setting_bus(259,1); // 2.3 goes to Port 1
-     //
-/* -----\/----- EXCLUDED -----\/-----
-     @(posedge clk);
-     fork
-	begin
-	   // input_port,size,tsf,sid
-	   //
-	   // Master0, addr 0.0 to Slave0
-	   enqueue_vita_pkt(0,10,0,{16'h0,8'h0,8'h0});
-	   // Master0, addr 2.0 to Slave0
-	   enqueue_vita_pkt(0,11,'h12345678,{16'h0,8'h2,8'h0});
-	   // Master0, addr 2.3 to Slave1
-	   enqueue_vita_pkt(0,14,'h45678901,{16'h0,8'h2,8'h3});
-	   // Master0, addr 2.2 to Slave0
-	   enqueue_vita_pkt(0,11,'h67890123,{16'h0,8'h2,8'h2});
-	end
-	begin
-	   // Master1, addr 1.0 to Slave0
-	   enqueue_vita_pkt(1,12,'h23456789,{16'h0,8'h1,8'h0});
-	   // Master1, addr 2.1 to Slave1
-	   enqueue_vita_pkt(1,13,'h34567890,{16'h0,8'h2,8'h1});
-	   // Master1, addr 2.3 to Slave1
-	   enqueue_vita_pkt(1,14,'h56789012,{16'h0,8'h2,8'h3});
-	end
-     join
- -----/\----- EXCLUDED -----/\----- */
-     //
-     @(posedge clk);
-     fork
-	begin
-	   // Master0 Sender Thread.
-	   //
-	   // Master0, addr 0.0 to Slave0
-	   for (seq_i0 = 0; seq_i0 < 10; seq_i0=seq_i0 + 1)
-	     enqueue_chdr_pkt_count(0,seq_i0,32+seq_i0,0,0,0,0,`SID(0,0,0,0));
-	   // Master1, addr 1.0 to Slave0
-	   for (seq_i0 = 20; seq_i0 < 30; seq_i0=seq_i0 + 1)
-	     enqueue_chdr_pkt_count(0,seq_i0,32+seq_i0,0,0,0,0,`SID(0,0,1,0));
-	end
-
-	begin
-	   // Master1 Sender Thread.
-	   //
-	   // Master1, addr 2.1 to Slave1
-	   for (seq_i1 = 10; seq_i1 < 20; seq_i1=seq_i1 + 1)
-	     enqueue_chdr_pkt_count(1,seq_i1,32+seq_i1,1,'h12345678+seq_i1*100,0,0,`SID(0,0,2,1));
-	   // Master0, addr 2.3 to Slave1
-	   for (seq_i1 = 30; seq_i1 < 40; seq_i1=seq_i1 + 1)
-	     enqueue_chdr_pkt_count(1,seq_i1,32+seq_i1,1,'h23456789+seq_i1*100,0,0,`SID(0,0,2,3));
-	end
-     join
-
-     repeat (1000) @(posedge clk);
-
-
-  end // initial begin
-
-
-   /////////////////////////////////////////////
-   //
-   // Control and input data thread.
-   //
-   /////////////////////////////////////////////
-   initial
-     begin
-	// Wait for reset to go high
-	while (reset!==1'b1)
-	  @(posedge clk);
-	// Wait for reset to go low
-	while (reset!==1'b0)
-	  @(posedge clk);
-	// Fork concurrent output checkers for each egress port.
-	fork
-	   begin
-	      // Slave0 Recevier thread.
-	      //
-	      // Master0, addr 0.0 to Slave0
-	      for (seq_o0 = 0; seq_o0 < 10; seq_o0=seq_o0 + 1)
-		dequeue_chdr_pkt_count(0,seq_o0,32+seq_o0,0,0,0,0,`SID(0,0,0,0));
-	      // Master1, addr 1.0 to Slave0
-	      for (seq_o0 = 20; seq_o0 < 30; seq_o0=seq_o0 + 1)
-		dequeue_chdr_pkt_count(0,seq_o0,32+seq_o0,0,0,0,0,`SID(0,0,1,0));
-	   end
-	   begin
-	      // Slave1 Receiver thread.
-	      //
-	      // Master1, addr 2.1 to Slave1
-	      for (seq_o1 = 10; seq_o1 < 20; seq_o1=seq_o1 + 1)
-		dequeue_chdr_pkt_count(1,seq_o1,32+seq_o1,1,'h12345678+seq_o1*100,0,0,`SID(0,0,2,1));
-	      // Master0, addr 2.3 to Slave1
-	      for (seq_o1 = 30; seq_o1 < 40; seq_o1=seq_o1 + 1)
-		dequeue_chdr_pkt_count(1,seq_o1,32+seq_o1,1,'h23456789+seq_o1*100,0,0,`SID(0,0,2,3));
-	   end
-	join
-
-	repeat (1000) @(posedge clk);
-	$finish;
-     end // initial begin