Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 219 insertions, 0 deletions

diff --git a/fpga/usrp3/sim/axi/sim_axis_lib.svh b/fpga/usrp3/sim/axi/sim_axis_lib.svh
new file mode 100644
index 000000000..bdee113de
--- /dev/null
+++ b/fpga/usrp3/sim/axi/sim_axis_lib.svh
@@ -0,0 +1,219 @@
+//
+// Copyright 2016 Ettus Research
+//
+`ifndef INCLUDED_SIM_AXIS_LIB
+`define INCLUDED_SIM_AXIS_LIB
+
+interface axis_t #(parameter DWIDTH = 32, parameter NUM_STREAMS = 1)(input clk);
+  logic [NUM_STREAMS*DWIDTH-1:0] tdata;
+  logic [NUM_STREAMS-1:0]        tvalid;
+  logic [NUM_STREAMS-1:0]        tlast;
+  logic [NUM_STREAMS-1:0]        tready;
+
+  modport master (
+    output tdata,
+    output tvalid,
+    output tlast,
+    input tready);
+
+  modport slave (
+    input tdata,
+    input tvalid,
+    input tlast,
+    output tready);
+endinterface
+
+// Interface to push data onto a master AXI-stream bus
+interface axis_master #(parameter DWIDTH = 32, parameter NUM_STREAMS = 1)(input clk);
+  axis_t #(.DWIDTH(DWIDTH), .NUM_STREAMS(NUM_STREAMS)) axis(.clk(clk));
+
+  // Check that stream is actually in use
+  function void check_stream(int stream);
+    assert (stream < NUM_STREAMS) else
+      $error("axis_master::check_stream(): Tried to perform operation on unused stream %0d", stream);
+  endfunction
+
+  // Reset signals / properties used by this interface
+  task automatic reset;
+    begin
+      axis.tvalid = 0;
+      axis.tlast  = 0;
+      axis.tdata  = 0;
+    end
+  endtask
+
+  // Push a word onto the AXI-Stream bus and wait for it to transfer
+  // Args:
+  // - word: The data to push onto the bus
+  // - eop (optional): End of packet (asserts tlast)
+  // - stream: Stream to use (Optional)
+  task automatic push_word (
+    input logic [DWIDTH-1:0] word,
+    input logic eop = 1'b0,
+    input int stream = 0);
+    begin
+      check_stream(stream);
+      if (clk) @(negedge clk);                // Align with negative edge
+      axis.tvalid[stream] = 1;
+      axis.tlast[stream] = eop;
+      axis.tdata[DWIDTH*stream +: DWIDTH] = word;
+      @(posedge clk);                             // Put sample on data bus
+      while(~axis.tready[stream]) @(posedge clk); // Wait until receiver ready
+      @(negedge clk);                             // Put sample on data bus
+      axis.tvalid[stream] = 0;
+      axis.tlast[stream] = 0;
+    end
+  endtask
+
+  // Push a bubble cycle onto the AXI-Stream bus
+  // Args:
+  // - stream: Stream to use (Optional)
+  task automatic push_bubble (input int stream = 0);
+    begin
+      check_stream(stream);
+      axis.tvalid[stream] = 0;
+      @(negedge clk);
+    end
+  endtask
+
+  // Push a packet with random data onto to the AXI Stream bus
+  // Args:
+  // - num_samps: Packet size.
+  task automatic push_rand_pkt (
+    input int num_samps,
+    input int stream = 0);
+    begin
+      check_stream(stream);
+      if (clk) @(negedge clk);
+      repeat(num_samps-1) begin
+        push_word({(((DWIDTH-1)/32)+1){$random}}, 0, stream);
+      end
+      push_word({(((DWIDTH-1)/32)+1){$random}}, 1, stream);
+    end
+  endtask
+
+  // Push a packet with a ramp on to the AXI Stream bus
+  // Args:
+  // - num_samps: Packet size.
+  // - ramp_start: Start value for the ramp
+  // - ramp_inc: Increment per clock cycle
+  // - stream: Stream to use (Optional)
+  task automatic push_ramp_pkt (
+    input integer num_samps,
+    input [DWIDTH-1:0] ramp_start,
+    input [DWIDTH-1:0] ramp_inc,
+    input int stream = 0);
+    begin
+      automatic integer counter = 0;
+      check_stream(stream);
+      if (clk) @(negedge clk);
+      repeat(num_samps-1) begin
+        push_word(ramp_start+(counter*ramp_inc), 0, stream);
+        counter = counter + 1;
+      end
+      push_word(ramp_start+(counter*ramp_inc), 1, stream);
+    end
+  endtask
+
+endinterface
+
+
+// Interface to push data onto a master AXI-stream bus
+interface axis_slave #(parameter DWIDTH = 32, parameter NUM_STREAMS = 1)(input clk);
+  axis_t #(.DWIDTH(DWIDTH), .NUM_STREAMS(NUM_STREAMS)) axis(.clk(clk));
+
+  // Check that stream is actually in use
+  function void check_stream(int stream);
+    assert (stream < NUM_STREAMS) else
+      $error("axis_slave::check_stream(): Tried to perform operation on unused stream %0d", stream);
+  endfunction
+
+  // Reset signals / properties used by this interface
+  task automatic reset;
+    begin
+      axis.tready = 0;
+    end
+  endtask
+
+  // Pull a word from the AXI Stream bus and
+  // return the data and last
+  // Args:
+  // - word: The data pulled from the bus
+  // - eop: End of packet (tlast)
+  // - stream: Stream to use (Optional)
+  task automatic pull_word (
+    output logic [DWIDTH-1:0] word,
+    output logic eop,
+    input int stream = 0);
+    begin
+      check_stream(stream);
+      if (clk) @(negedge clk);
+      axis.tready[stream] = 1;
+      while(~axis.tvalid[stream]) @(posedge clk);
+      word = axis.tdata[DWIDTH*stream +: DWIDTH];
+      eop = axis.tlast[stream];
+      @(negedge clk);
+      axis.tready[stream] = 0;
+    end
+  endtask
+
+  // Wait for a sample to be transferred on the AXI Stream
+  // bus and return the data and last. Note, this task only
+  // observes the bus and does not affect the AXI control
+  // signals.
+  // Args:
+  // - word: The data pulled from the bus
+  // - eop: End of packet (tlast)
+  // - stream: Stream to use (Optional)
+  task automatic copy_word (
+    output logic [DWIDTH-1:0] word,
+    output logic eop,
+    input int stream = 0);
+    begin
+      check_stream(stream);
+      while(~(axis.tready[stream]&axis.tvalid[stream])) @(posedge clk);  // Wait until sample is transferred
+      word = axis.tdata[DWIDTH*stream +: DWIDTH];
+      eop = axis.tlast[stream];
+      @(negedge clk);
+    end
+  endtask
+
+  // Wait for a bubble cycle on the AXI Stream bus
+  // Args:
+  // - stream: Stream to use (Optional)
+  task automatic wait_for_bubble (
+    input int stream = 0);
+    begin
+      check_stream(stream);
+      while(axis.tready[stream]&axis.tvalid[stream]) @(posedge clk);
+      @(negedge clk);
+    end
+  endtask
+
+  // Wait for a packet to finish on the bus
+  // Args:
+  // - stream: Stream to use (Optional)
+  task automatic wait_for_pkt (
+    input int stream = 0);
+    begin
+      check_stream(stream);
+      while(~(axis.tready[stream]&axis.tvalid[stream]&axis.tlast[stream])) @(posedge clk);
+      @(negedge clk);
+    end
+  endtask
+
+  // Drop a word on the bus
+  // Args:
+  // - stream:  Stream to use (Optional)
+  task automatic drop_word (
+    input int stream = 0);
+    begin
+      logic [DWIDTH-1:0] dropped_word;
+      logic dropped_eop;
+      pull_word(dropped_word, dropped_eop, stream);
+    end
+  endtask
+
+endinterface
+
+`endif
\ No newline at end of file