Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 205 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/xge/rtl/verilog/rx_dequeue.v b/fpga/usrp3/lib/xge/rtl/verilog/rx_dequeue.v
new file mode 100644
index 000000000..3603f6d0c
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/rx_dequeue.v
@@ -0,0 +1,205 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  File name "rx_dequeue.v"                                    ////
+////                                                              ////
+////  This file is part of the "10GE MAC" project                 ////
+////  http://www.opencores.org/cores/xge_mac/                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - A. Tanguay (antanguay@opencores.org)                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+ 
+ 
+`include "defines.v"
+ 
+module rx_dequeue(/*AUTOARG*/
+  // Outputs
+  rxdfifo_ren, pkt_rx_data, pkt_rx_val, pkt_rx_sop, pkt_rx_eop,
+  pkt_rx_err, pkt_rx_mod, pkt_rx_avail, status_rxdfifo_udflow_tog,
+  // Inputs
+  clk_156m25, reset_156m25_n, rxdfifo_rdata, rxdfifo_rstatus,
+  rxdfifo_rempty, rxdfifo_ralmost_empty, pkt_rx_ren
+  );
+ 
+input         clk_156m25;
+input         reset_156m25_n;
+ 
+input [63:0]  rxdfifo_rdata;
+input [7:0]   rxdfifo_rstatus;
+input         rxdfifo_rempty;
+input         rxdfifo_ralmost_empty;
+ 
+input         pkt_rx_ren;
+ 
+output        rxdfifo_ren;
+ 
+output [63:0] pkt_rx_data;
+output        pkt_rx_val;
+output        pkt_rx_sop;
+output        pkt_rx_eop;
+output        pkt_rx_err;
+output [2:0]  pkt_rx_mod;
+output        pkt_rx_avail;
+ 
+output        status_rxdfifo_udflow_tog;
+ 
+/*AUTOREG*/
+// Beginning of automatic regs (for this module's undeclared outputs)
+reg                     pkt_rx_avail;
+reg [63:0]              pkt_rx_data;
+reg                     pkt_rx_eop;
+reg                     pkt_rx_err;
+reg [2:0]               pkt_rx_mod;
+reg                     pkt_rx_sop;
+reg                     pkt_rx_val;
+reg                     status_rxdfifo_udflow_tog;
+// End of automatics
+ 
+reg           end_eop;
+ 
+/*AUTOWIRE*/
+ 
+ 
+// End eop to force one cycle between packets
+ 
+assign rxdfifo_ren = !rxdfifo_rempty && pkt_rx_ren && !end_eop;
+ 
+ 
+ 
+always @(posedge clk_156m25 or negedge reset_156m25_n) begin
+ 
+    if (reset_156m25_n == 1'b0) begin
+ 
+        pkt_rx_avail <= 1'b0;
+ 
+        pkt_rx_data <= 64'b0;
+        pkt_rx_sop <= 1'b0;
+        pkt_rx_eop <= 1'b0;
+        pkt_rx_err <= 1'b0;
+        pkt_rx_mod <= 3'b0;
+ 
+        pkt_rx_val <= 1'b0;
+ 
+        end_eop <= 1'b0;
+ 
+        status_rxdfifo_udflow_tog <= 1'b0;
+ 
+    end
+    else begin
+ 
+        pkt_rx_avail <= !rxdfifo_ralmost_empty;
+ 
+ 
+ 
+        // If eop shows up at the output of the fifo, we drive eop on
+        // the bus on the next read. This will be the last read for this
+        // packet. The fifo is designed to output data early. On last read,
+        // data from next packet will appear at the output of fifo. Modulus
+        // of packet length is in lower bits.
+ 
+        pkt_rx_eop <= rxdfifo_ren && rxdfifo_rstatus[`RXSTATUS_EOP];
+        pkt_rx_mod <= {3{rxdfifo_ren & rxdfifo_rstatus[`RXSTATUS_EOP]}} & rxdfifo_rstatus[2:0];
+ 
+ 
+        pkt_rx_val <= rxdfifo_ren;
+ 
+        if (rxdfifo_ren) begin
+ 
+            `ifdef BIGENDIAN
+	    pkt_rx_data <= {rxdfifo_rdata[7:0],
+                            rxdfifo_rdata[15:8],
+                            rxdfifo_rdata[23:16],
+                            rxdfifo_rdata[31:24],
+                            rxdfifo_rdata[39:32],
+                            rxdfifo_rdata[47:40],
+                            rxdfifo_rdata[55:48],
+                            rxdfifo_rdata[63:56]};
+            `else
+	    pkt_rx_data <= rxdfifo_rdata;
+            `endif
+ 
+        end
+ 
+ 
+        if (rxdfifo_ren && rxdfifo_rstatus[`RXSTATUS_SOP]) begin
+ 
+            // SOP indication on first word
+ 
+            pkt_rx_sop <= 1'b1;
+            pkt_rx_err <= 1'b0;
+ 
+        end
+        else begin
+ 
+            pkt_rx_sop <= 1'b0;
+ 
+ 
+            // Give an error if FIFO is to underflow
+ 
+            if (rxdfifo_rempty && pkt_rx_ren && !end_eop) begin
+                pkt_rx_val <= 1'b1;
+                pkt_rx_eop <= 1'b1;
+                pkt_rx_err <= 1'b1;
+            end
+ 
+        end
+ 
+ 
+        if (rxdfifo_ren && |(rxdfifo_rstatus[`RXSTATUS_ERR])) begin
+ 
+            // Status stored in FIFO is propagated to error signal.
+ 
+            pkt_rx_err <= 1'b1;
+ 
+        end
+ 
+ 
+        //---
+        // EOP indication at the end of the frame. Cleared otherwise.
+ 
+        if (rxdfifo_ren && rxdfifo_rstatus[`RXSTATUS_EOP]) begin
+            end_eop <= 1'b1;
+        end
+        else if (pkt_rx_ren) begin
+            end_eop <= 1'b0;
+        end
+ 
+ 
+ 
+        //---
+        // FIFO errors, used to generate interrupts
+ 
+        if (rxdfifo_rempty && pkt_rx_ren && !end_eop) begin
+            status_rxdfifo_udflow_tog <= ~status_rxdfifo_udflow_tog;
+        end
+ 
+    end
+end
+ 
+endmodule