Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 282 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/vita_200/new_rx_framer.v b/fpga/usrp3/lib/vita_200/new_rx_framer.v
new file mode 100644
index 000000000..df91aff72
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/new_rx_framer.v
@@ -0,0 +1,282 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module new_rx_framer
+  #(
+    parameter BASE=0,
+    parameter CHIPSCOPE=0,
+    parameter SAMPLE_FIFO_SIZE=10
+    )
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    input [63:0] vita_time,
+
+    input strobe,
+    input [31:0] sample,
+    input run,
+    input eob,
+    output full,
+    output reg [11:0] seqnum,
+    output [31:0] sid,
+
+    output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
+
+    output [31:0] debug
+    );
+
+   reg [15:0] 	  len;
+   reg [63:0] 	  hold_time;
+
+   wire [63:0] 	  dfifo_tdata;
+   wire 	  dfifo_tlast, dfifo_tvalid, dfifo_tready;
+
+   wire [80:0] 	  hfifo_tdata;
+   wire 	  hfifo_tvalid, hfifo_tready;
+
+   wire [63:0] 	  o_tdata_int;
+   wire 	  o_tlast_int, o_tvalid_int, o_tready_int;
+
+   wire [15:0] 	  sample_space;
+
+   wire [15:0] 	  maxlen;
+   reg [31:0] 	  holding;
+
+
+   // FIXME need to handle case where hdr fifo is full (i.e. too many tiny packets)
+   assign full = (sample_space == 16'd0) | (sample_space == 16'd1) | ~hdr_tready;
+
+   setting_reg #(.my_addr(BASE), .width(16)) sr_maxlen
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(maxlen),.changed());
+
+   wire sid_changed;
+   setting_reg #(.my_addr(BASE+1), .width(32)) sr_sid
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(sid),.changed(sid_changed));
+
+   localparam START = 0;
+   localparam SECOND = 1;
+   localparam FIRST = 2;
+
+   reg [1:0] 	  instate;
+   reg [15:0] 	  numsamps;
+   reg 		  nearly_eop;
+
+
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  instate <= START;
+	  numsamps <= 0;
+	  nearly_eop <= 0;
+
+       end
+     else if (run)
+       case(instate)
+	 //
+	 // Start a new packet in this state
+	 //
+	 START :
+	   if(strobe)
+	     if(eop)
+	       begin
+		  instate <= START;
+		  numsamps <= 0;
+		  nearly_eop <= 0;
+	       end
+	     else
+	       begin
+		  instate <= SECOND;
+		  numsamps <= numsamps + 1;
+		  nearly_eop <= (numsamps >= (maxlen-2));
+	       end // else: !if(eop)
+	 //
+	 // Second 32 bit sample in a 64bit word
+	 //
+	 SECOND :
+	   if(strobe)
+	     if(eop)
+	       begin
+		  instate <= START;
+		  numsamps <= 0;
+		  nearly_eop <= 0;
+	       end
+	     else
+	       begin
+		  instate <= FIRST;
+		  numsamps <= numsamps + 1;
+		  nearly_eop <= (numsamps >= (maxlen-2));
+	       end // else: !if(eop)
+	 //
+	 // First 32bit sample in a 64bit word.
+	 //
+	 FIRST :
+	   if(strobe)
+	     if(eop)
+	       begin
+		  instate <= START;
+		  numsamps <= 0;
+		  nearly_eop <= 0;
+	       end
+	     else
+	       begin
+		  instate <= SECOND;
+		  numsamps <= numsamps + 1;
+		  nearly_eop <= (numsamps >= (maxlen-2));
+	       end
+       endcase // case (instate)
+     else  begin
+	  instate <= START;
+	  numsamps <= 0;
+	  nearly_eop <= 0;
+     end
+
+
+   always @(posedge clk)
+     if(strobe && run)
+       begin
+	  holding <= sample;
+	  if(instate == START)
+	    hold_time <= vita_time;
+       end
+
+   always @(posedge clk)
+     if(reset | clear)
+       len <= 5;
+     else
+       if(strobe && run)
+	 if(sample_tlast)
+	   len <= 5;
+	 else
+	   len <= len + 1;
+
+   always @(posedge clk)
+     if(reset | clear | sid_changed)
+       seqnum <= 12'd0;
+     else
+       if(o_tlast_int & o_tvalid_int & o_tready_int)
+	 seqnum <= seqnum + 12'd1;
+
+
+
+   wire 	  eop = eob | nearly_eop | full;
+
+   wire [63:0] 	  sample_tdata = (instate == SECOND) ? {holding, sample} : {sample, 32'h0};
+   wire 	  sample_tlast = eop;
+   wire 	  sample_tvalid = run & strobe & ( (instate == SECOND) | eop );
+   wire 	  sample_tready;
+
+   wire [80:0] 	  hdr_tdata = {eob,len[13:0],2'b0,(instate == START) ? vita_time : hold_time};
+   wire 	  hdr_tvalid = sample_tlast && sample_tvalid && sample_tready;
+   wire 	  hdr_tready;
+
+   wire [80:0] 	  hfifo_tdata_tmp;
+   wire 	  hfifo_tvalid_tmp, hfifo_tready_tmp;
+
+
+
+   axi_fifo #(.WIDTH(65), .SIZE(SAMPLE_FIFO_SIZE)) datafifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({sample_tlast,sample_tdata}), .i_tvalid(sample_tvalid), .i_tready(sample_tready),
+      .o_tdata({dfifo_tlast,dfifo_tdata}), .o_tvalid(dfifo_tvalid), .o_tready(dfifo_tready),
+      .space(sample_space), .occupied());
+
+   axi_fifo_short #(.WIDTH(81)) hdrfifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(hdr_tdata), .i_tvalid(hdr_tvalid), .i_tready(hdr_tready),
+      .o_tdata(hfifo_tdata_tmp), .o_tvalid(hfifo_tvalid_tmp), .o_tready(hfifo_tready_tmp),
+      .space(), .occupied());
+
+   axi_fifo_short #(.WIDTH(81)) hdrfifo2
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(hfifo_tdata_tmp), .i_tvalid(hfifo_tvalid_tmp), .i_tready(hfifo_tready_tmp),
+      .o_tdata(hfifo_tdata), .o_tvalid(hfifo_tvalid), .o_tready(hfifo_tready),
+      .space(), .occupied());
+
+
+
+
+   // The output state machine is responsible for forming output packets.
+   // Output packets are formed by combining the entries in the header fifo,
+   // and the samples in the data fifo. A single entry in the header fifo
+   // contains both the compressed header and the 64 bit time stamp.
+
+   reg [1:0] 	  outstate;
+   localparam OUT_IDLE = 2'd0;
+   localparam OUT_HEAD = 2'd1;
+   localparam OUT_TIME = 2'd2;
+   localparam OUT_BODY = 2'd3;
+
+   always @(posedge clk)
+     if(reset | clear)
+       outstate <= OUT_IDLE;
+     else
+       case(outstate)
+	 OUT_IDLE :
+	   if(hfifo_tvalid) //having a header signals a complete packet
+	     outstate <= OUT_HEAD;
+	 OUT_HEAD :
+	   if(o_tvalid_int && o_tready_int)
+	     outstate <= OUT_TIME;
+	 OUT_TIME :
+	   if(o_tvalid_int && o_tready_int)
+	     outstate <= OUT_BODY;
+	 OUT_BODY :
+	   if(o_tvalid_int && o_tready_int && o_tlast_int)
+	     outstate <= OUT_IDLE;
+       endcase // case (outstate)
+
+   //output data mux feeds from single line of header fifo or the data fifo
+   assign o_tdata_int = (outstate == OUT_HEAD) ? { 3'b001, hfifo_tdata[80], seqnum, hfifo_tdata[79:64], sid} :
+			(outstate == OUT_TIME) ? hfifo_tdata[63:0] : dfifo_tdata;
+
+   //output the last signal from the data fifo
+   assign o_tlast_int = (outstate == OUT_BODY) ? dfifo_tlast : 1'b0;
+
+   //output valid connected to data valid in non-IDLE states
+   assign o_tvalid_int = (outstate != OUT_IDLE) & dfifo_tvalid;
+
+   //only pop from header fifo on the very last transaction
+   assign hfifo_tready = o_tvalid_int && o_tready_int && o_tlast_int;
+
+   //connect data fifo ready with out ready in the BODY state
+   assign dfifo_tready = (outstate == OUT_BODY) ? o_tready_int : 1'b0;
+
+   axi_fifo_short #(.WIDTH(65)) output_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({o_tlast_int, o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+      .o_tdata({o_tlast, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+      .space(), .occupied());
+/* -----\/----- EXCLUDED -----\/-----
+
+    assign debug[3:0] =  {instate, outstate};
+    assign debug[7:4] =  {1'b0, sample_tlast, sample_tvalid, sample_tready};
+    assign debug[11:8] =  {1'b0, 1'b0, hfifo_tvalid, hfifo_tready};
+    assign debug[15:12] =  {1'b0, dfifo_tlast, dfifo_tvalid, dfifo_tready};
+    assign debug[19:16] =  {1'b0, o_tlast_int, o_tvalid_int, o_tready_int};
+ -----/\----- EXCLUDED -----/\----- */
+
+   assign debug = {
+		   sample_tlast, //15
+		   sample_tvalid,//14
+		   sample_tready,//13
+		   dfifo_tvalid, //12
+		   dfifo_tready, //11
+		   hdr_tvalid,   //10
+		   hdr_tready,   //9
+		   hfifo_tvalid, //8
+		   hfifo_tready, //7
+		   eob,           //6
+		   nearly_eop,    //5
+		   full,          //4
+		   outstate[1:0], //3:2
+		   instate[1:0]   //1:0
+		   };
+
+
+endmodule // new_rx_framer