Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 183 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/vita_200/chdr_32f_to_16s.v b/fpga/usrp3/lib/vita_200/chdr_32f_to_16s.v
new file mode 100644
index 000000000..c18fd34e5
--- /dev/null
+++ b/fpga/usrp3/lib/vita_200/chdr_32f_to_16s.v
@@ -0,0 +1,183 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module chdr_32f_to_16s #
+(
+  parameter BASE = 0
+)
+(
+  input              clk,
+  input              rst,
+
+  // axi4 stream slave interface
+  input [63:0]       i_tdata,
+  input              i_tvalid,
+  input              i_tlast,
+  output             i_tready,
+
+  // axi4 stream master interface
+  output reg [63:0]  o_tdata,
+  output             o_tvalid,
+  output             o_tlast,
+  input              o_tready,
+
+  // settings bus slave interface
+  input              set_stb,
+  input [7:0]        set_addr,
+  input [31:0]       set_data,
+
+  output [63:0]      debug
+);
+
+
+  wire [31:0] float0 = i_tdata[63:32];
+  wire [31:0] float1 = i_tdata[31:0];
+
+  wire [15:0] fixed1_cur;
+  wire [15:0] fixed0_cur;
+
+  // Parametrize the converter as IEEE 754 single precision float to Q15
+  xxf_to_xxs #
+  (
+    .FBITS(32),
+    .MBITS(23),
+    .EBITS(8),
+    .RADIX(15),
+    .QWIDTH(16)
+  ) f2q0
+  (
+    .i_float(float0),
+    .o_fixed(fixed0_cur)
+  );
+
+  // Parametrize the converter as IEEE 754 single precision float to Q15
+  xxf_to_xxs #
+  (
+    .FBITS(32),
+    .MBITS(23),
+    .EBITS(8),
+    .RADIX(15),
+    .QWIDTH(16)
+  ) f2q1
+  (
+    .i_float(float1),
+    .o_fixed(fixed1_cur)
+  );
+
+  // As we need two cycles for one output cycle store the output in regs
+  reg [15:0] fixed1_old;
+  reg [15:0] fixed0_old;
+
+  wire handshake_ok = o_tready & i_tvalid;
+
+  always @ (posedge clk)
+    if (rst)
+      {fixed0_old, fixed1_old} <= {16'h0, 16'h0};
+    else if (handshake_ok)
+      {fixed0_old, fixed1_old} <= {fixed0_cur, fixed1_cur};
+
+  // Make routing (SID) available via settings bus
+  wire        set_sid;
+  wire [15:0] new_sid_dst;
+
+  setting_reg #
+  (
+    .my_addr(BASE),
+    .width(17)
+  ) new_destination
+  ( .clk(clk),
+    .rst(rst),
+    .strobe(set_stb),
+    .addr(set_addr),
+    .in(set_data),
+    .out({set_sid, new_sid_dst[15:0]}),
+    .changed()
+  );
+
+  // Parse CHDR info
+  wire        chdr_has_time = i_tdata[61];
+  // CHDR has either 8 bytes of header or 16 if VITA time is included.
+  wire [15:0] chdr_header_bytes = chdr_has_time ? 16 : 8;
+  // Calculate size of samples input in bytes by taking CHDR size filed
+  // and subtracting header length.
+  wire [15:0] sample_byte_count_in = i_tdata[47:32] - chdr_header_bytes;
+  // Calculate size of samples to be output by taking input size
+  // and dividing by two as sizeof(Q15) = 2*sizeof(float)
+  wire [15:0] sample_byte_count_out = sample_byte_count_in >> 1;
+  // Calculate size of output CHDR packet by adding back header size to new
+  // payload size.
+  wire [15:0] output_chdr_pkt_size = sample_byte_count_out + chdr_header_bytes;
+
+  localparam HEADER  = 2'd0;
+  localparam TIME    = 2'd1;
+  localparam PREPARE = 2'd2;
+  localparam OUTPUT  = 2'd3;
+
+
+  reg [1:0] state;
+
+  always @(posedge clk)
+    if (rst) begin
+      state <= HEADER;
+    end
+
+    else case(state)
+      HEADER:
+        // In case we see a i_last we just wait for the
+        // next header here, otherwise move on to the next states
+        if (handshake_ok & !i_tlast) begin
+          state <= chdr_has_time ? TIME : PREPARE;
+        end
+
+      TIME:
+        if (handshake_ok) begin
+          // If we get a premature end of burst go back
+          // to searching for the start of a new packet.
+          state <= i_tlast ? HEADER : PREPARE;
+        end
+
+      PREPARE:
+        if (handshake_ok) begin
+          state <= i_tlast ? HEADER : OUTPUT;
+        end
+
+      OUTPUT:
+        if (handshake_ok) begin
+          state <= i_tlast ? HEADER : PREPARE;
+        end
+
+      default:
+        state <= HEADER;
+    endcase
+
+  always @(*)
+    case(state)
+      // Populate header with CHDR fields
+      HEADER:
+        o_tdata = {i_tdata[63:48], output_chdr_pkt_size,
+                   set_sid ? {i_tdata[15:0], new_sid_dst[15:0]} : i_tdata[31:0]};
+      TIME:
+        o_tdata = i_tdata;
+      PREPARE:
+        // The bits [31:0] of o_tdata are useless. The header will take
+        // care of this by setting the correct length.
+        o_tdata = {fixed0_cur[15:0], fixed1_cur[15:0], 32'h0};
+      OUTPUT:
+        o_tdata = {fixed0_old[15:0], fixed1_old[15:0],
+                   fixed0_cur[15:0], fixed1_cur[15:0]};
+      default :
+        o_tdata = i_tdata;
+    endcase
+
+  // Either the input is valid and is directly output (HEADER, TIME, EOB),
+  // or we need to be in the 'OUTPUT' state ({fixed0_old, fixed1_old} contains correct old
+  // line)
+  assign o_tvalid = (i_tvalid && state != PREPARE) || i_tvalid && i_tlast;
+  assign i_tready = o_tready || (state == PREPARE && !i_tlast);
+  assign o_tlast  = i_tlast;
+
+endmodule