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| author | Ben Hilburn <ben.hilburn@ettus.com> | 2013-10-10 10:17:27 -0700 |
|---|---|---|
| committer | Ben Hilburn <ben.hilburn@ettus.com> | 2013-10-10 10:17:27 -0700 |
| commit | 0df4b801a34697f2058b4a7b95e08d2a0576c9db (patch) | |
| tree | be10e78d1a97c037a9e7492360a178d1873b9c09 /fpga/usrp3/lib/vita/build_16_to_8 | |
| parent | 6e7bc850b66e8188718248b76b729c7cf9c89700 (diff) | |
| download | uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.tar.gz uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.tar.bz2 uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.zip | |
Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.
Diffstat (limited to 'fpga/usrp3/lib/vita/build_16_to_8')
| -rwxr-xr-x | fpga/usrp3/lib/vita/build_16_to_8 | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/vita/build_16_to_8 b/fpga/usrp3/lib/vita/build_16_to_8 new file mode 100755 index 000000000..9c32aa7cd --- /dev/null +++ b/fpga/usrp3/lib/vita/build_16_to_8 @@ -0,0 +1,2 @@ +iverilog -y . -y ../dsp/ -y ../control/ -Wall chdr_16sc_to_8sc_tb.v -o chdr_16sc_to_8sc_tb + |