aboutsummaryrefslogtreecommitdiffstats
path: root/fpga/usrp3/lib/timing/pps.v
diff options
context:
space:
mode:
authormichael-west <michael.west@ettus.com>2014-07-30 11:54:26 -0700
committermichael-west <michael.west@ettus.com>2014-07-30 11:54:26 -0700
commit35fc42f9fcbc5a791bdabc92086a51a2279563f1 (patch)
treefd053dd7e462fd49759ae255334de6d5c5aefd59 /fpga/usrp3/lib/timing/pps.v
parentbca5edb57979983a9eb8d6cd1016961552ad217c (diff)
parenteafae66c030aa86e9da127de4f6d5ec4fd641c59 (diff)
downloaduhd-35fc42f9fcbc5a791bdabc92086a51a2279563f1.tar.gz
uhd-35fc42f9fcbc5a791bdabc92086a51a2279563f1.tar.bz2
uhd-35fc42f9fcbc5a791bdabc92086a51a2279563f1.zip
Merge branch 'maint' into uhd/bug492
Conflicts: host/lib/usrp/b200/b200_impl.cpp
Diffstat (limited to 'fpga/usrp3/lib/timing/pps.v')
-rw-r--r--fpga/usrp3/lib/timing/pps.v22
1 files changed, 22 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/timing/pps.v b/fpga/usrp3/lib/timing/pps.v
new file mode 100644
index 000000000..49d3641b7
--- /dev/null
+++ b/fpga/usrp3/lib/timing/pps.v
@@ -0,0 +1,22 @@
+//
+// Copyright 2014 Ettus Research LLC
+//
+
+module pps_generator
+ #(parameter CLK_FREQ=0, DUTY=25)
+ (input clk, input reset, output pps);
+
+ reg[31:0] count;
+
+ always @(posedge clk) begin
+ if (reset) begin
+ count <= 32'b1;
+ end else if (count >= CLK_FREQ) begin
+ count <= 32'b1;
+ end else begin
+ count <= count + 1'b1;
+ end
+ end
+
+ assign pps = (count < CLK_FREQ * DUTY / 100);
+endmodule //pps_generator