From b63507efb3cf1a8fa20794c452d57028e18da182 Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Tue, 22 Jul 2014 15:49:02 -0700 Subject: fpga: Updating FPGA code for UHD-3.7.2-rc1 --- fpga/usrp3/lib/timing/pps.v | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 fpga/usrp3/lib/timing/pps.v (limited to 'fpga/usrp3/lib/timing/pps.v') diff --git a/fpga/usrp3/lib/timing/pps.v b/fpga/usrp3/lib/timing/pps.v new file mode 100644 index 000000000..49d3641b7 --- /dev/null +++ b/fpga/usrp3/lib/timing/pps.v @@ -0,0 +1,22 @@ +// +// Copyright 2014 Ettus Research LLC +// + +module pps_generator + #(parameter CLK_FREQ=0, DUTY=25) + (input clk, input reset, output pps); + + reg[31:0] count; + + always @(posedge clk) begin + if (reset) begin + count <= 32'b1; + end else if (count >= CLK_FREQ) begin + count <= 32'b1; + end else begin + count <= count + 1'b1; + end + end + + assign pps = (count < CLK_FREQ * DUTY / 100); +endmodule //pps_generator -- cgit v1.2.3