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| author | Andrew Moch <Andrew.Moch@ni.com> | 2021-01-29 17:58:12 +0000 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2021-06-03 11:26:54 -0500 |
| commit | 04d29e85b0c0698e3de96b54fd3f6e04eb439f74 (patch) | |
| tree | 52b8f5e6ec0ef83e8e1515754740e4e2d631d8fc /fpga/usrp3/lib/sim | |
| parent | d099fc3b032250bcc70e4c24f78d5eb6508850e1 (diff) | |
| download | uhd-04d29e85b0c0698e3de96b54fd3f6e04eb439f74.tar.gz uhd-04d29e85b0c0698e3de96b54fd3f6e04eb439f74.tar.bz2 uhd-04d29e85b0c0698e3de96b54fd3f6e04eb439f74.zip | |
fpga: lib: Add AXI4 (full) interface
Add a SystemVerilog interface for connecting AXI4 ports, and an
associated header file with helper macros.
Diffstat (limited to 'fpga/usrp3/lib/sim')
0 files changed, 0 insertions, 0 deletions