Removed copy of FPGA source files.

13 files changed, 0 insertions, 318 deletions

diff --git a/fpga/usrp3/lib/sim/tx/.gitignore b/fpga/usrp3/lib/sim/tx/.gitignore
deleted file mode 100644
index 257fc3311..000000000
--- a/fpga/usrp3/lib/sim/tx/.gitignore
+++ /dev/null
@@ -1,5 +0,0 @@
-*.log
-*.exe
-*.vcd
-isim*
-fuse*
\ No newline at end of file
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_isim b/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_isim
deleted file mode 100755
index 8ecd3e31d..000000000
--- a/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_isim
+++ /dev/null
@@ -1,40 +0,0 @@
-vlogcomp -work work ${XILINX}/verilog/src/glbl.v
-vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../vita/new_tx_tb.v
-vlogcomp -work work ../../../dsp/duc_chain.v
-vlogcomp -work work ../../../dsp/hb_interp.v
-vlogcomp -work work ../../../dsp/small_hb_int.v
-vlogcomp -work work ../../../dsp/cic_interp.v
-vlogcomp -work work ../../../dsp/cic_int_shifter.v
-vlogcomp -work work ../../../dsp/cic_strober.v
-vlogcomp -work work ../../../dsp/cordic_stage.v
-vlogcomp -work work ../../../dsp/cordic_z24.v
-vlogcomp -work work ../../../dsp/clip.v
-vlogcomp -work work ../../../dsp/round.v
-vlogcomp -work work ../../../dsp/round_reg.v
-vlogcomp -work work ../../../dsp/sign_extend.v
-vlogcomp -work work ../../../dsp/add2_reg.v
-vlogcomp -work work ../../../dsp/add2_and_round_reg.v
-vlogcomp -work work ../../../dsp/srl.v
-vlogcomp -work work ../../../dsp/acc.v
-vlogcomp -work work ../../../dsp/clip_reg.v
-vlogcomp -work work ../../../dsp/add2_and_round.v
-vlogcomp -work work ../../../dsp/add2.v
-vlogcomp -work work ../../../vita/new_tx_control.v
-vlogcomp -work work ../../../vita/new_tx_deframer.v
-vlogcomp -work work ../../../vita/tx_responder.v
-vlogcomp -work work ../../../vita/context_packet_gen.v
-vlogcomp -work work ../../../vita/trigger_context_pkt.v
-vlogcomp -work work ../../../control/setting_reg.v
-vlogcomp -work work ../../../control/ram_2port.v
-vlogcomp -work work ../../../fifo/axi_fifo.v
-vlogcomp -work work ../../../fifo/axi_mux4.v
-vlogcomp -work work ../../../fifo/axi_fifo_short.v
-vlogcomp -work work ../../../timing/time_compare.v
-
-
-
-fuse work.new_tx_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o new_tx_tb.exe
-
-# run the simulation scrip
-#./new_tx_tb.exe -gui #-tclbatch simcmds.tcl
-./new_tx_tb.exe
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_iverilog b/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_iverilog
deleted file mode 100755
index 8ae57a610..000000000
--- a/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_iverilog
+++ /dev/null
@@ -1,16 +0,0 @@
-iverilog -y . \
--D SIM_SCRIPT=true \
-../../../vita/new_tx_tb.v \
--y ../../../vita/ \
--y ../../../fifo/ \
--y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
--y ../../../control/ \
--y ../../../timing/ \
--y ../../../dsp/  \
-/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
--y ../../../../../usrp2/models/ \
--Wall \
--o new_tx_tb.exe
-
-./new_tx_tb.exe
-
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/simulation_script.v b/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/simulation_script.v
deleted file mode 100644
index 9ded9d35e..000000000
--- a/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/simulation_script.v
+++ /dev/null
@@ -1,20 +0,0 @@
- initial
-     begin
-	tvalid <= 1'b0;
-	while(reset)
-	  @(posedge clk);
-	write_setting_bus(SR_ERROR_POLICY,32'h4);
-	write_setting_bus(SR_PACKETS,32'h8000_0002);
-
-	write_setting_bus(SR_INTERP,32'h1);
-
-	// Burst of len 2
-	send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
-
-	// Burst of 8 triggers Intra burst seq_id error
-	send_burst_with_seqid_error(8/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
-	
-	// Burst of 2
-	send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h00b/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
-     end // initial begin
-   
\ No newline at end of file
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_isim b/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_isim
deleted file mode 100755
index 8ecd3e31d..000000000
--- a/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_isim
+++ /dev/null
@@ -1,40 +0,0 @@
-vlogcomp -work work ${XILINX}/verilog/src/glbl.v
-vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../vita/new_tx_tb.v
-vlogcomp -work work ../../../dsp/duc_chain.v
-vlogcomp -work work ../../../dsp/hb_interp.v
-vlogcomp -work work ../../../dsp/small_hb_int.v
-vlogcomp -work work ../../../dsp/cic_interp.v
-vlogcomp -work work ../../../dsp/cic_int_shifter.v
-vlogcomp -work work ../../../dsp/cic_strober.v
-vlogcomp -work work ../../../dsp/cordic_stage.v
-vlogcomp -work work ../../../dsp/cordic_z24.v
-vlogcomp -work work ../../../dsp/clip.v
-vlogcomp -work work ../../../dsp/round.v
-vlogcomp -work work ../../../dsp/round_reg.v
-vlogcomp -work work ../../../dsp/sign_extend.v
-vlogcomp -work work ../../../dsp/add2_reg.v
-vlogcomp -work work ../../../dsp/add2_and_round_reg.v
-vlogcomp -work work ../../../dsp/srl.v
-vlogcomp -work work ../../../dsp/acc.v
-vlogcomp -work work ../../../dsp/clip_reg.v
-vlogcomp -work work ../../../dsp/add2_and_round.v
-vlogcomp -work work ../../../dsp/add2.v
-vlogcomp -work work ../../../vita/new_tx_control.v
-vlogcomp -work work ../../../vita/new_tx_deframer.v
-vlogcomp -work work ../../../vita/tx_responder.v
-vlogcomp -work work ../../../vita/context_packet_gen.v
-vlogcomp -work work ../../../vita/trigger_context_pkt.v
-vlogcomp -work work ../../../control/setting_reg.v
-vlogcomp -work work ../../../control/ram_2port.v
-vlogcomp -work work ../../../fifo/axi_fifo.v
-vlogcomp -work work ../../../fifo/axi_mux4.v
-vlogcomp -work work ../../../fifo/axi_fifo_short.v
-vlogcomp -work work ../../../timing/time_compare.v
-
-
-
-fuse work.new_tx_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o new_tx_tb.exe
-
-# run the simulation scrip
-#./new_tx_tb.exe -gui #-tclbatch simcmds.tcl
-./new_tx_tb.exe
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_iverilog b/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_iverilog
deleted file mode 100755
index 8ae57a610..000000000
--- a/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_iverilog
+++ /dev/null
@@ -1,16 +0,0 @@
-iverilog -y . \
--D SIM_SCRIPT=true \
-../../../vita/new_tx_tb.v \
--y ../../../vita/ \
--y ../../../fifo/ \
--y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
--y ../../../control/ \
--y ../../../timing/ \
--y ../../../dsp/  \
-/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
--y ../../../../../usrp2/models/ \
--Wall \
--o new_tx_tb.exe
-
-./new_tx_tb.exe
-
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/simulation_script.v b/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/simulation_script.v
deleted file mode 100644
index 5dc608bc2..000000000
--- a/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/simulation_script.v
+++ /dev/null
@@ -1,20 +0,0 @@
- initial
-     begin
-	tvalid <= 1'b0;
-	while(reset)
-	  @(posedge clk);
-	write_setting_bus(SR_ERROR_POLICY,32'h2);
-	write_setting_bus(SR_PACKETS,32'h8000_0002);
-
-	write_setting_bus(SR_INTERP,32'h1);
-
-	// Burst of len 2
-	send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
-
-	// Burst of 8 triggers Intra burst seq_id error
-	send_burst_with_seqid_error(8/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
-	
-	// Burst of 2
-	send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h00b/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
-     end // initial begin
-   
\ No newline at end of file
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/run_isim b/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/run_isim
deleted file mode 100755
index 8ecd3e31d..000000000
--- a/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/run_isim
+++ /dev/null
@@ -1,40 +0,0 @@
-vlogcomp -work work ${XILINX}/verilog/src/glbl.v
-vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../vita/new_tx_tb.v
-vlogcomp -work work ../../../dsp/duc_chain.v
-vlogcomp -work work ../../../dsp/hb_interp.v
-vlogcomp -work work ../../../dsp/small_hb_int.v
-vlogcomp -work work ../../../dsp/cic_interp.v
-vlogcomp -work work ../../../dsp/cic_int_shifter.v
-vlogcomp -work work ../../../dsp/cic_strober.v
-vlogcomp -work work ../../../dsp/cordic_stage.v
-vlogcomp -work work ../../../dsp/cordic_z24.v
-vlogcomp -work work ../../../dsp/clip.v
-vlogcomp -work work ../../../dsp/round.v
-vlogcomp -work work ../../../dsp/round_reg.v
-vlogcomp -work work ../../../dsp/sign_extend.v
-vlogcomp -work work ../../../dsp/add2_reg.v
-vlogcomp -work work ../../../dsp/add2_and_round_reg.v
-vlogcomp -work work ../../../dsp/srl.v
-vlogcomp -work work ../../../dsp/acc.v
-vlogcomp -work work ../../../dsp/clip_reg.v
-vlogcomp -work work ../../../dsp/add2_and_round.v
-vlogcomp -work work ../../../dsp/add2.v
-vlogcomp -work work ../../../vita/new_tx_control.v
-vlogcomp -work work ../../../vita/new_tx_deframer.v
-vlogcomp -work work ../../../vita/tx_responder.v
-vlogcomp -work work ../../../vita/context_packet_gen.v
-vlogcomp -work work ../../../vita/trigger_context_pkt.v
-vlogcomp -work work ../../../control/setting_reg.v
-vlogcomp -work work ../../../control/ram_2port.v
-vlogcomp -work work ../../../fifo/axi_fifo.v
-vlogcomp -work work ../../../fifo/axi_mux4.v
-vlogcomp -work work ../../../fifo/axi_fifo_short.v
-vlogcomp -work work ../../../timing/time_compare.v
-
-
-
-fuse work.new_tx_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o new_tx_tb.exe
-
-# run the simulation scrip
-#./new_tx_tb.exe -gui #-tclbatch simcmds.tcl
-./new_tx_tb.exe
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/run_iverilog b/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/run_iverilog
deleted file mode 100755
index 8ae57a610..000000000
--- a/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/run_iverilog
+++ /dev/null
@@ -1,16 +0,0 @@
-iverilog -y . \
--D SIM_SCRIPT=true \
-../../../vita/new_tx_tb.v \
--y ../../../vita/ \
--y ../../../fifo/ \
--y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
--y ../../../control/ \
--y ../../../timing/ \
--y ../../../dsp/  \
-/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
--y ../../../../../usrp2/models/ \
--Wall \
--o new_tx_tb.exe
-
-./new_tx_tb.exe
-
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/simulation_script.v b/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/simulation_script.v
deleted file mode 100644
index 368a817b6..000000000
--- a/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/simulation_script.v
+++ /dev/null
@@ -1,25 +0,0 @@
- initial
-     begin
-	tvalid <= 1'b0;
-	while(reset)
-	  @(posedge clk);
-	write_setting_bus(SR_ERROR_POLICY,32'h4);
-	write_setting_bus(SR_PACKETS,32'h8000_0002);
-
-	write_setting_bus(SR_INTERP,32'h1);
-
-	// Burst of len 2
-	send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
-
-	// Burst of 2
-	send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
-
-	// Inter burst sequence error
-	send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h015/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
-
-	// Burst of 2
-	send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h400/*time*/,12'h0017/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
-
-
-     end // initial begin
-   
\ No newline at end of file
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/run_isim b/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/run_isim
deleted file mode 100755
index 8ecd3e31d..000000000
--- a/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/run_isim
+++ /dev/null
@@ -1,40 +0,0 @@
-vlogcomp -work work ${XILINX}/verilog/src/glbl.v
-vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../vita/new_tx_tb.v
-vlogcomp -work work ../../../dsp/duc_chain.v
-vlogcomp -work work ../../../dsp/hb_interp.v
-vlogcomp -work work ../../../dsp/small_hb_int.v
-vlogcomp -work work ../../../dsp/cic_interp.v
-vlogcomp -work work ../../../dsp/cic_int_shifter.v
-vlogcomp -work work ../../../dsp/cic_strober.v
-vlogcomp -work work ../../../dsp/cordic_stage.v
-vlogcomp -work work ../../../dsp/cordic_z24.v
-vlogcomp -work work ../../../dsp/clip.v
-vlogcomp -work work ../../../dsp/round.v
-vlogcomp -work work ../../../dsp/round_reg.v
-vlogcomp -work work ../../../dsp/sign_extend.v
-vlogcomp -work work ../../../dsp/add2_reg.v
-vlogcomp -work work ../../../dsp/add2_and_round_reg.v
-vlogcomp -work work ../../../dsp/srl.v
-vlogcomp -work work ../../../dsp/acc.v
-vlogcomp -work work ../../../dsp/clip_reg.v
-vlogcomp -work work ../../../dsp/add2_and_round.v
-vlogcomp -work work ../../../dsp/add2.v
-vlogcomp -work work ../../../vita/new_tx_control.v
-vlogcomp -work work ../../../vita/new_tx_deframer.v
-vlogcomp -work work ../../../vita/tx_responder.v
-vlogcomp -work work ../../../vita/context_packet_gen.v
-vlogcomp -work work ../../../vita/trigger_context_pkt.v
-vlogcomp -work work ../../../control/setting_reg.v
-vlogcomp -work work ../../../control/ram_2port.v
-vlogcomp -work work ../../../fifo/axi_fifo.v
-vlogcomp -work work ../../../fifo/axi_mux4.v
-vlogcomp -work work ../../../fifo/axi_fifo_short.v
-vlogcomp -work work ../../../timing/time_compare.v
-
-
-
-fuse work.new_tx_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o new_tx_tb.exe
-
-# run the simulation scrip
-#./new_tx_tb.exe -gui #-tclbatch simcmds.tcl
-./new_tx_tb.exe
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/run_iverilog b/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/run_iverilog
deleted file mode 100755
index 8ae57a610..000000000
--- a/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/run_iverilog
+++ /dev/null
@@ -1,16 +0,0 @@
-iverilog -y . \
--D SIM_SCRIPT=true \
-../../../vita/new_tx_tb.v \
--y ../../../vita/ \
--y ../../../fifo/ \
--y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
--y ../../../control/ \
--y ../../../timing/ \
--y ../../../dsp/  \
-/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
--y ../../../../../usrp2/models/ \
--Wall \
--o new_tx_tb.exe
-
-./new_tx_tb.exe
-
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/simulation_script.v b/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/simulation_script.v
deleted file mode 100644
index fddffb871..000000000
--- a/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/simulation_script.v
+++ /dev/null
@@ -1,24 +0,0 @@
- initial
-     begin
-	tvalid <= 1'b0;
-	while(reset)
-	  @(posedge clk);
-	write_setting_bus(SR_ERROR_POLICY,32'h2);
-	write_setting_bus(SR_PACKETS,32'h8000_0002);
-
-	write_setting_bus(SR_INTERP,32'h1);
-
-	// Burst of len 2
-	send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
-
-	// Burst of 2
-	send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
-
-	// Inter burst sequence error
-	send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h015/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
-
-	// Burst of 2
-	send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h400/*time*/,12'h0017/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
-
-     end // initial begin
-   
\ No newline at end of file