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| author | Andrew Moch <Andrew.Moch@ni.com> | 2020-06-18 16:26:59 +0100 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-06-24 09:55:14 -0500 |
| commit | dd9847c5c3c3fac17658b526a7d8894711af086e (patch) | |
| tree | d4b4e41bdbe1f37b8c4c310770c2c552f862932a /fpga/usrp3/lib/sim/packet_proc | |
| parent | a3ff904432d831702d47534f37a437304f5c55c1 (diff) | |
| download | uhd-dd9847c5c3c3fac17658b526a7d8894711af086e.tar.gz uhd-dd9847c5c3c3fac17658b526a7d8894711af086e.tar.bz2 uhd-dd9847c5c3c3fac17658b526a7d8894711af086e.zip | |
fpga: lib: Pipeline and add clken to ip_hdr_checksum
Adds LATENCY parameter to control the ammount of pieplineing. Adds a
clock enable to control the advance of the pipeline.
Used in xport when calculating new UDP headers for CHDR traffic.
Diffstat (limited to 'fpga/usrp3/lib/sim/packet_proc')
| -rw-r--r-- | fpga/usrp3/lib/sim/packet_proc/ip_hdr_checksum/ip_hdr_checksum_tb.v | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/fpga/usrp3/lib/sim/packet_proc/ip_hdr_checksum/ip_hdr_checksum_tb.v b/fpga/usrp3/lib/sim/packet_proc/ip_hdr_checksum/ip_hdr_checksum_tb.v index 82deca656..191a62f0a 100644 --- a/fpga/usrp3/lib/sim/packet_proc/ip_hdr_checksum/ip_hdr_checksum_tb.v +++ b/fpga/usrp3/lib/sim/packet_proc/ip_hdr_checksum/ip_hdr_checksum_tb.v @@ -1,9 +1,9 @@ // -// Copyright 2014 Ettus Research LLC -// Copyright 2018 Ettus Research, a National Instruments Company +// Copyright 2020 Ettus Research, a National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // + module ip_hdr_checksum_tb(); initial $dumpfile("ip_hdr_checksum_tb.vcd"); @@ -28,7 +28,8 @@ module ip_hdr_checksum_tb(); ip_hdr_checksum ip_hdr_checksum (.clk(clk), .in(in), - .out(out)); + .out(out), + .clken(1)); initial begin |