Pushing the bulk of UHD-3.7.0 code.

1 files changed, 15 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/sim/axi_crossbar/run_sim b/fpga/usrp3/lib/sim/axi_crossbar/run_sim
new file mode 100755
index 000000000..41d07a635
--- /dev/null
+++ b/fpga/usrp3/lib/sim/axi_crossbar/run_sim
@@ -0,0 +1,15 @@
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -work work ../../control/axi_crossbar_tb.v
+vlogcomp -work work ../../control/axi_crossbar.v
+vlogcomp -work work ../../control/axi_slave_mux.v
+vlogcomp -work work ../../control/axi_forwarding_cam.v
+vlogcomp -work work ../../control/setting_reg.v
+vlogcomp -work work ../../fifo/monitor_axi_fifo.v
+vlogcomp -work work ../../fifo/axi_fifo_short.v
+
+
+
+fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe
+
+# run the simulation scrip
+./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl