aboutsummaryrefslogtreecommitdiffstats
path: root/fpga/usrp3/lib/sim/axi_crossbar/run_sim
diff options
context:
space:
mode:
authorMartin Braun <martin.braun@ettus.com>2014-10-07 11:25:20 +0200
committerMartin Braun <martin.braun@ettus.com>2014-10-07 11:25:20 +0200
commitfd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch)
tree3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp3/lib/sim/axi_crossbar/run_sim
parent3b66804e41891e358c790b453a7a59ec7462dba4 (diff)
downloaduhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.gz
uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.bz2
uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.zip
Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp3/lib/sim/axi_crossbar/run_sim')
-rwxr-xr-xfpga/usrp3/lib/sim/axi_crossbar/run_sim15
1 files changed, 0 insertions, 15 deletions
diff --git a/fpga/usrp3/lib/sim/axi_crossbar/run_sim b/fpga/usrp3/lib/sim/axi_crossbar/run_sim
deleted file mode 100755
index 41d07a635..000000000
--- a/fpga/usrp3/lib/sim/axi_crossbar/run_sim
+++ /dev/null
@@ -1,15 +0,0 @@
-vlogcomp -work work ${XILINX}/verilog/src/glbl.v
-vlogcomp -work work ../../control/axi_crossbar_tb.v
-vlogcomp -work work ../../control/axi_crossbar.v
-vlogcomp -work work ../../control/axi_slave_mux.v
-vlogcomp -work work ../../control/axi_forwarding_cam.v
-vlogcomp -work work ../../control/setting_reg.v
-vlogcomp -work work ../../fifo/monitor_axi_fifo.v
-vlogcomp -work work ../../fifo/axi_fifo_short.v
-
-
-
-fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe
-
-# run the simulation scrip
-./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl