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| author | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
| commit | fd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch) | |
| tree | 3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp3/lib/sim/axi_crossbar/run_iverilog | |
| parent | 3b66804e41891e358c790b453a7a59ec7462dba4 (diff) | |
| download | uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.gz uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.bz2 uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.zip | |
Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp3/lib/sim/axi_crossbar/run_iverilog')
| -rwxr-xr-x | fpga/usrp3/lib/sim/axi_crossbar/run_iverilog | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/fpga/usrp3/lib/sim/axi_crossbar/run_iverilog b/fpga/usrp3/lib/sim/axi_crossbar/run_iverilog deleted file mode 100755 index a23b4e4a9..000000000 --- a/fpga/usrp3/lib/sim/axi_crossbar/run_iverilog +++ /dev/null @@ -1,21 +0,0 @@ - -iverilog \ --s axi_crossbar_tb \ --y ~/XILINX_verilog/ISE/verilog/src/unisims \ --o axi_crossbar_tb \ -~/XILINX_verilog/ISE/verilog/src/glbl.v \ -../../control/axi_crossbar_tb.v \ -../../control/axi_crossbar.v \ -../../control/axi_slave_mux.v \ -../../control/axi_fifo_header.v \ -../../control/arb_qualify_master.v \ -../../control/setting_reg.v \ -../../fifo/monitor_axi_fifo.v \ -../../fifo/axi_fifo_short.v - - - -#fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe - -# run the simulation scrip -#./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl |