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| author | michael-west <michael.west@ettus.com> | 2014-03-25 15:59:03 -0700 |
|---|---|---|
| committer | michael-west <michael.west@ettus.com> | 2014-03-25 15:59:03 -0700 |
| commit | 04292f9b109479b639add31f83fd240a6387f488 (patch) | |
| tree | 4b8723a4ae63626029704f901ee0083bb23bc1e9 /fpga/usrp3/lib/sim/axi_crossbar/run_iverilog | |
| parent | 09915aa57bc88099cbcbbe925946ae65bc0ad8f0 (diff) | |
| parent | ff8a1252f3a51369abe0a165d963b781089ec66c (diff) | |
| download | uhd-04292f9b109479b639add31f83fd240a6387f488.tar.gz uhd-04292f9b109479b639add31f83fd240a6387f488.tar.bz2 uhd-04292f9b109479b639add31f83fd240a6387f488.zip | |
Merge branch 'master' into mwest/b200_docs
Diffstat (limited to 'fpga/usrp3/lib/sim/axi_crossbar/run_iverilog')
| -rwxr-xr-x | fpga/usrp3/lib/sim/axi_crossbar/run_iverilog | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/sim/axi_crossbar/run_iverilog b/fpga/usrp3/lib/sim/axi_crossbar/run_iverilog new file mode 100755 index 000000000..a23b4e4a9 --- /dev/null +++ b/fpga/usrp3/lib/sim/axi_crossbar/run_iverilog @@ -0,0 +1,21 @@ + +iverilog \ +-s axi_crossbar_tb \ +-y ~/XILINX_verilog/ISE/verilog/src/unisims \ +-o axi_crossbar_tb \ +~/XILINX_verilog/ISE/verilog/src/glbl.v \ +../../control/axi_crossbar_tb.v \ +../../control/axi_crossbar.v \ +../../control/axi_slave_mux.v \ +../../control/axi_fifo_header.v \ +../../control/arb_qualify_master.v \ +../../control/setting_reg.v \ +../../fifo/monitor_axi_fifo.v \ +../../fifo/axi_fifo_short.v + + + +#fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe + +# run the simulation scrip +#./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl |