Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 169 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/rfnoc/fosphor/fifo_srl.v b/fpga/usrp3/lib/rfnoc/fosphor/fifo_srl.v
new file mode 100644
index 000000000..700da18d3
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/fosphor/fifo_srl.v
@@ -0,0 +1,169 @@
+/*
+ * fifo_srl.v
+ *
+ * Very small/light-weight FIFO using SRL.
+ * Only for synchronous design. Has a fixed depth of 15 or 31 entries and
+ * always work in the so-called first-word-fall-thru mode.
+ *
+ * Copyright (C) 2014  Ettus Corporation LLC
+ * Copyright 2018 Ettus Research, a National Instruments Company
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ *
+ * vim: ts=4 sw=4
+ */
+
+`ifdef SIM
+`default_nettype none
+`endif
+
+module fifo_srl #(
+	parameter integer WIDTH = 4,
+	parameter integer LOG2_DEPTH = 5,	// 4 or 5
+	parameter integer AFULL_LEVEL = -1	// -1 -> No AFULL
+
+)(
+	input  wire [WIDTH-1:0] di,
+	input  wire wren,
+	output wire full,
+	output wire afull,
+
+	output reg  [WIDTH-1:0] do,
+	input  wire rden,
+	output reg  empty,
+
+	input  wire clk,
+	input  wire rst
+);
+
+	genvar i;
+
+	// Signals
+	wire [WIDTH-1:0] srl_q;
+	reg  [LOG2_DEPTH-1:0] srl_addr;
+	wire srl_addr_ce;
+
+	wire srl_write;
+	wire srl_read;
+
+	wire srl_full;
+	wire srl_afull;
+	reg  srl_empty;
+	wire srl_aempty;
+
+	// Instanciate the SRLs
+	generate
+		if (LOG2_DEPTH == 6) begin
+			wire [WIDTH-1:0] srl0_q31, srl0_q, srl1_q;
+
+			for (i=0; i<WIDTH; i=i+1)
+			begin : srl_64
+				SRLC32E srl_I0 (
+					.Q(srl0_q[i]),
+					.Q31(srl0_q31[i]),
+					.A(srl_addr[4:0]),
+					.CE(srl_write),
+					.CLK(clk),
+					.D(di[i])
+				);
+
+				SRLC32E srl_I1 (
+					.Q(srl1_q[i]),
+					.A(srl_addr[4:0]),
+					.CE(srl_write),
+					.CLK(clk),
+					.D(srl0_q31[i])
+				);
+
+				MUXF7 mux_I (
+					.O(srl_q[i]),
+					.I0(srl0_q[i]),
+					.I1(srl1_q[i]),
+					.S(srl_addr[5])
+				);
+			end
+		end else if (LOG2_DEPTH == 5) begin
+			for (i=0; i<WIDTH; i=i+1)
+				SRLC32E srl_I (
+					.Q(srl_q[i]),
+					.A(srl_addr),
+					.CE(srl_write),
+					.CLK(clk),
+					.D(di[i])
+				);
+		end else if (LOG2_DEPTH == 4) begin
+			for (i=0; i<WIDTH; i=i+1)
+				SRL16E srl_I (
+					.Q(srl_q[i]),
+					.A0(srl_addr[0]),
+					.A1(srl_addr[1]),
+					.A2(srl_addr[2]),
+					.A3(srl_addr[3]),
+					.CE(srl_write),
+					.CLK(clk),
+					.D(di[i])
+				);
+		end
+	endgenerate
+
+	// Address counter
+	assign srl_addr_ce = srl_write ^ srl_read;
+
+	always @(posedge clk)
+	begin
+		if (rst)
+			srl_addr <= {LOG2_DEPTH{1'b1}};
+		else if (srl_addr_ce) begin
+			if (srl_write)
+				srl_addr <= srl_addr + 1;
+			else
+				srl_addr <= srl_addr - 1;
+		end
+	end
+
+	// SRL status
+	assign srl_full = srl_addr == {{(LOG2_DEPTH-1){1'b1}}, 1'b0};
+
+	generate
+		if (AFULL_LEVEL != -1) begin
+			assign srl_afull = (srl_addr >= AFULL_LEVEL) && ~&(srl_addr);
+		end else begin
+			assign srl_afull = 1'b0;
+		end
+	endgenerate
+
+	assign srl_aempty = &(~srl_addr);
+
+	always @(posedge clk)
+	begin
+		if (rst)
+			srl_empty <= 1'b1;
+		else if (srl_addr_ce)
+			srl_empty <= srl_aempty & srl_read;
+	end
+
+	// Output register (to capture whatever comes out from SRL)
+	always @(posedge clk)
+	begin
+		if (srl_read)
+			do <= srl_q;
+	end
+
+	// Control and flag generation
+		// Write/Full is easy
+	assign srl_write = wren;
+	assign full = srl_full;
+	assign afull = srl_afull;
+
+		// Read/Empty is tricky
+	always @(posedge clk)
+	begin
+		if (rst)
+			empty <= 1'b1;
+		else if (rden | srl_read)
+			empty <= srl_empty;
+	end
+
+	assign srl_read = (rden | empty) & ~srl_empty;
+
+endmodule // fifo_srl