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| author | Andrew Moch <Andrew.Moch@ni.com> | 2020-03-19 19:55:53 +0100 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-03-23 08:23:51 -0500 |
| commit | 5c7237fb407cfccaee205980d97e40ce10768c2a (patch) | |
| tree | dbdba3dcefff2d3cdeab27fa371c203b3398aa81 /fpga/usrp3/lib/rfnoc/file_source.v | |
| parent | b721621237c0cd4150e9310cf443d4fb3a735388 (diff) | |
| download | uhd-5c7237fb407cfccaee205980d97e40ce10768c2a.tar.gz uhd-5c7237fb407cfccaee205980d97e40ce10768c2a.tar.bz2 uhd-5c7237fb407cfccaee205980d97e40ce10768c2a.zip | |
fpga: Fix errors found by linting with vsim
Diffstat (limited to 'fpga/usrp3/lib/rfnoc/file_source.v')
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/file_source.v | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/fpga/usrp3/lib/rfnoc/file_source.v b/fpga/usrp3/lib/rfnoc/file_source.v index 160cd9984..87ded79bd 100644 --- a/fpga/usrp3/lib/rfnoc/file_source.v +++ b/fpga/usrp3/lib/rfnoc/file_source.v @@ -35,7 +35,6 @@ module file_source #( end end - wire [31:0] sid; reg [11:0] seqnum; wire [15:0] rate; reg [1:0] state; |