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author | Martin Braun <martin.braun@ettus.com> | 2020-01-23 16:10:22 -0800 |
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committer | Martin Braun <martin.braun@ettus.com> | 2020-01-28 09:35:36 -0800 |
commit | bafa9d95453387814ef25e6b6256ba8db2df612f (patch) | |
tree | 39ba24b5b67072d354775272e687796bb511848d /fpga/usrp3/lib/rfnoc/chdr_framer.v | |
parent | 3075b981503002df3115d5f1d0b97d2619ba30f2 (diff) | |
download | uhd-bafa9d95453387814ef25e6b6256ba8db2df612f.tar.gz uhd-bafa9d95453387814ef25e6b6256ba8db2df612f.tar.bz2 uhd-bafa9d95453387814ef25e6b6256ba8db2df612f.zip |
Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.
This commit also updates the license files and paths therein.
We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.
== Original Codebase and Rebasing ==
The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/
It can be used for bisecting, reference, and a more detailed history.
The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.
If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:
- Create a directory to store patches (this should be an empty
directory):
mkdir ~/patches
- Now make sure that your FPGA codebase is based on the same state as
the code that was merged:
cd src/fpga # Or wherever your FPGA code is stored
git rebase v4.0.0.0-pre-uhd-merge
Note: The rebase command may look slightly different depending on what
exactly you're trying to rebase.
- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:
git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches
Note: Make sure that only patches are stored in your output directory.
It should otherwise be empty. Make sure that you picked the correct
range of commits, and only commits you wanted to rebase were exported
as patch files.
- Go to the UHD repository and apply the patches:
cd src/uhd # Or wherever your UHD repository is stored
git am --directory fpga ~/patches/*
rm -rf ~/patches # This is for cleanup
== Contributors ==
The following people have contributed mainly to these files (this list
is not complete):
Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Diffstat (limited to 'fpga/usrp3/lib/rfnoc/chdr_framer.v')
-rw-r--r-- | fpga/usrp3/lib/rfnoc/chdr_framer.v | 128 |
1 files changed, 128 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/rfnoc/chdr_framer.v b/fpga/usrp3/lib/rfnoc/chdr_framer.v new file mode 100644 index 000000000..271c8e3d5 --- /dev/null +++ b/fpga/usrp3/lib/rfnoc/chdr_framer.v @@ -0,0 +1,128 @@ +// +// Copyright 2014 Ettus Research LLC +// Copyright 2018 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// FIXME handle odd length inputs +// +// Warning: Currently only 32 / 64-bit input widths are supported. +// If 64-bit is selected, there will be a bubble state. +// + +module chdr_framer + #(parameter SIZE=10, + parameter WIDTH=32, // 32 or 64 only! TODO: Extend to other widths. + parameter USE_SEQ_NUM=0) // Use provided seq number in tuser + (input clk, input reset, input clear, + input [WIDTH-1:0] i_tdata, input [127:0] i_tuser, input i_tlast, input i_tvalid, output i_tready, + output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready); + + wire header_i_tvalid, header_i_tready; + wire [63:0] body_i_tdata; + wire body_i_tlast, body_i_tvalid, body_i_tready; + + wire [127:0] header_o_tdata; + wire header_o_tvalid, header_o_tready; + wire [63:0] body_o_tdata; + wire body_o_tlast, body_o_tvalid, body_o_tready; + reg [15:0] length; + reg [11:0] seqnum; + + assign i_tready = header_i_tready & body_i_tready; + assign header_i_tvalid = i_tlast & i_tvalid & i_tready; + assign body_i_tlast = i_tlast; + + // Handle 32 and 64 widths + generate + if (WIDTH == 32) begin + reg even; + always @(posedge clk) + if(reset | clear) + even <= 0; + else + if(i_tvalid & i_tready) + if(i_tlast) + even <= 0; + else + even <= ~even; + + reg [31:0] held_i_tdata; + always @(posedge clk) begin + if (i_tvalid & i_tready) held_i_tdata <= i_tdata; + end + assign body_i_tvalid = i_tvalid & i_tready & (i_tlast | even); + assign body_i_tdata = even ? { held_i_tdata, i_tdata } : {i_tdata, i_tdata}; // really should be 0 in bottom, but this simplifies mux + end else begin + assign body_i_tvalid = i_tvalid; + assign body_i_tdata = i_tdata; + end + endgenerate + + // FIXME handle lengths of partial 32-bit words + always @(posedge clk) + if(reset | clear) + length <= (WIDTH == 32) ? 4 : 8; + else if(header_i_tready & header_i_tvalid) + length <= (WIDTH == 32) ? 4 : 8; + else if(i_tvalid & i_tready) + length <= (WIDTH == 32) ? length + 4 : length + 8; + + axi_fifo_flop2 #(.WIDTH(128)) header_fifo_flop2 + (.clk(clk), .reset(reset), .clear(clear), + .i_tdata({i_tuser[127:112],length,i_tuser[95:0]}), .i_tvalid(header_i_tvalid), .i_tready(header_i_tready), + .o_tdata(header_o_tdata), .o_tvalid(header_o_tvalid), .o_tready(header_o_tready), + .occupied(), .space()); + + axi_fifo #(.WIDTH(65), .SIZE(SIZE)) body_fifo + (.clk(clk), .reset(reset), .clear(clear), + .i_tdata({body_i_tlast,body_i_tdata}), .i_tvalid(body_i_tvalid), .i_tready(body_i_tready), + .o_tdata({body_o_tlast,body_o_tdata}), .o_tvalid(body_o_tvalid), .o_tready(body_o_tready), + .occupied(), .space()); + + reg [3:0] chdr_state; + localparam ST_IDLE = 0; + localparam ST_HEAD = 1; + localparam ST_TIME = 2; + localparam ST_BODY = 3; + + always @(posedge clk) + if(reset | clear) + chdr_state <= ST_IDLE; + else + case(chdr_state) + ST_IDLE : + if(header_o_tvalid & body_o_tvalid) + chdr_state <= ST_HEAD; + ST_HEAD : + if(o_tready) + if(header_o_tdata[125]) // time + chdr_state <= ST_TIME; + else + chdr_state <= ST_BODY; + ST_TIME : + if(o_tready) + chdr_state <= ST_BODY; + ST_BODY : + if(o_tready & body_o_tlast) + chdr_state <= ST_IDLE; + endcase // case (chdr_state) + + always @(posedge clk) + if(reset | clear) + seqnum <= 12'd0; + else + if(o_tvalid & o_tready & o_tlast) + seqnum <= seqnum + 12'd1; + + wire [15:0] out_length = header_o_tdata[111:96] + (header_o_tdata[125] ? 16'd16 : 16'd8); + + assign o_tvalid = (chdr_state == ST_HEAD) | (chdr_state == ST_TIME) | (body_o_tvalid & (chdr_state == ST_BODY)); + assign o_tlast = (chdr_state == ST_BODY) & body_o_tlast; + assign o_tdata = (chdr_state == ST_HEAD) ? {header_o_tdata[127:124], (USE_SEQ_NUM ? header_o_tdata[123:112] : seqnum), out_length, header_o_tdata[95:64] } : + (chdr_state == ST_TIME) ? header_o_tdata[63:0] : + body_o_tdata; + assign body_o_tready = (chdr_state == ST_BODY) & o_tready; + assign header_o_tready = ((chdr_state == ST_TIME) | ((chdr_state == ST_HEAD) & ~header_o_tdata[125])) & o_tready; + +endmodule // chdr_framer |