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| author | Wade Fife <wade.fife@ettus.com> | 2020-03-31 15:05:51 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-04-14 16:37:43 -0500 |
| commit | a8c4f021277cf3b0a0897fa9da0252541512f3a6 (patch) | |
| tree | b876ccc5414c00b9377157198577ece31db8792b /fpga/usrp3/lib/rfnoc/blocks | |
| parent | eed2d2348cab7dc786673f0649373809d04027d5 (diff) | |
| download | uhd-a8c4f021277cf3b0a0897fa9da0252541512f3a6.tar.gz uhd-a8c4f021277cf3b0a0897fa9da0252541512f3a6.tar.bz2 uhd-a8c4f021277cf3b0a0897fa9da0252541512f3a6.zip | |
fpga: rfnoc: Add option to sample sideband info at start of packet
The axis_data_to_chdr block previously only sampled the sideband
information at the end of the packet. This adds a parameter that
controls if the sideband information should be sampled at the beginning
of the packet or the end of the packet. In the former case, large
internal packet buffers are not required.
Diffstat (limited to 'fpga/usrp3/lib/rfnoc/blocks')
0 files changed, 0 insertions, 0 deletions