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| author | Wade Fife <wade.fife@ettus.com> | 2020-06-08 16:22:29 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-06-29 13:41:15 -0500 |
| commit | 38caced6946243f0390c541df54160c45e4959cc (patch) | |
| tree | 1215c33a22d622fe8c36e8823ad2b71af4e0ea6f /fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/Makefile | |
| parent | 5244c06ae71589a08f337371d91798a6ac3d292b (diff) | |
| download | uhd-38caced6946243f0390c541df54160c45e4959cc.tar.gz uhd-38caced6946243f0390c541df54160c45e4959cc.tar.bz2 uhd-38caced6946243f0390c541df54160c45e4959cc.zip | |
fpga: rfnoc: Add RFNoC Window block
Diffstat (limited to 'fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/Makefile')
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/Makefile | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/Makefile b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/Makefile new file mode 100644 index 000000000..f05034702 --- /dev/null +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/Makefile @@ -0,0 +1,45 @@ +# +# Copyright 2020 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir. Note: +# UHD_FPGA_DIR must be passed into this Makefile. +BASE_DIR = ../../../../top +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Include makefiles and sources for the DUT and its +# dependencies. +include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs +include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs +include Makefile.srcs + +DESIGN_SRCS += $(abspath \ +$(RFNOC_CORE_SRCS) \ +$(RFNOC_UTIL_SRCS) \ +$(RFNOC_OOT_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +SIM_TOP = rfnoc_block_window_tb glbl +SIM_SRCS = \ +$(abspath rfnoc_block_window_tb.sv) \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak |