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| author | Wade Fife <wade.fife@ettus.com> | 2020-06-19 15:40:12 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-07-30 12:51:41 -0500 |
| commit | 1e94f85b8bafc3f9acab7ef35d2675fa7e61f6f4 (patch) | |
| tree | 12ba30a59c8057e355971797d5cc7bf6910f520b /fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/Makefile | |
| parent | b0b3849a18e1f2d3cb255a507b01ac5e7a9416a0 (diff) | |
| download | uhd-1e94f85b8bafc3f9acab7ef35d2675fa7e61f6f4.tar.gz uhd-1e94f85b8bafc3f9acab7ef35d2675fa7e61f6f4.tar.bz2 uhd-1e94f85b8bafc3f9acab7ef35d2675fa7e61f6f4.zip | |
fpga: rfnoc: Add Signal Generator RFNoC block
Diffstat (limited to 'fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/Makefile')
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/Makefile | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/Makefile b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/Makefile new file mode 100644 index 000000000..8fffd1c2e --- /dev/null +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/Makefile @@ -0,0 +1,49 @@ +# +# Copyright 2020 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir. Note: +# UHD_FPGA_DIR must be passed into this Makefile. +BASE_DIR = ../../../../top +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Include makefiles and sources for the DUT and its +# dependencies. +include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs +include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs +include $(LIB_IP_DIR)/cordic_rotator/Makefile.inc +include Makefile.srcs + +DESIGN_SRCS += $(abspath \ +$(RFNOC_CORE_SRCS) \ +$(RFNOC_UTIL_SRCS) \ +$(RFNOC_OOT_SRCS) \ +$(LIB_IP_CORDIC_ROTATOR_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +SIM_TOP = rfnoc_block_siggen_all_tb glbl +SIM_SRCS = \ +$(abspath $(IP_BUILD_DIR)/cordic_rotator/sim/cordic_rotator.vhd) \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ +$(abspath rfnoc_block_siggen_tb.sv) \ +$(abspath rfnoc_block_siggen_all_tb.sv) \ + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak |